A Lossless Clamp Circuit for Tapped-Inductor Buck Converters*
Kaiwei Yao, Jia Wei and Fred C. Lee
Center for Power Electronics Systems
The Bradley Department of Electrical and Computer Engineering
Virginia Polytechnic Institute and State University
Blacksburg, VA 24061 USA
Abstract —Tapped-inductor buck converters allow great
improvements in the performance of 12V-input voltage
regulator modules (VRMs). However, the converters’ inductor
leakage energy problem limits their applications. This paper
proposes a simple clamp circuit, which can effectively clamp the
switch turn-off voltage spike and totally recover the leakage
energy. Simulation and experimental results prove the
significant improvement afforded by the proposed clamp circuit.
I. INTRODUCTION
Semiconductor integration technology is developing so fast
that present microprocessors can run at clock frequency
greater than 1GHz. Moore’s Law predicts that this trend will
continue in the next decade. However, this development
depends on a clean low-voltage, high-current power supply.
Because of this requirement, a special DC-DC power supply,
the voltage regulator module (VRM), is needed for good
voltage regulation. Since the required power continues to
increase, 12V proves to be a better level than 5V for the
VRM’s input voltage [1]. The conduction loss in the input
bus can be significantly reduced since the input current is
much smaller. Also, the input filter capacitance can be
reduced because the same capacitance can store much more
energy at higher voltage levels. All of these factors mean that
a 12V-input VRM can achieve high efficiency, small size and
low cost.
If there is no requirement for isolation, the buck converter
is the simplest circuit for realizing step-down DC-DC
conversion. As a result, this topology is widely used for both
5V- and 12V-input VRMs. In order to handle large output
current and achieve the current ripple cancellation effect,
multi-phase interleaving technology is used. Fig. 1 shows this
state-of-the-art topology for VRM applications.
Vo
Q11
5V
L1
Q21
Vin
Co
12V
Processor
Load
However, since the output voltage is low (from 1.1V to
1.85V for the VRM 9.0 standard), the step-down ratio is very
large for 12V input voltage. The duty cycle is
D=Vo/Vin,
(1)
which is so small that the turn-on period of the top switch
will be extremely short, especially when the switching
frequency is high. As a result, gate driving for the top
switches would be problematic.
Another problem for the 12V-input buck converter is the
asymmetric transient response that occurs because of the
great difference between the rising and falling speeds of the
inductor current [2]. During the turn-on period of the top
switch, the inductor current rising speed is:
di/dt|rise=(Vin-Vo)/L.
(2)
The inductor current falling speed during the freewheeling
period is:
di/dt|fall=Vo/L.
(3)
Since the inductor current falling speed is the slowest, it will
limit the transient response of the VRM.
Finally, the most serious problem for the 12V-input buck
converter is its low efficiency, especially for high-frequency
applications. Since the top switch turn-off current equals the
output peak current, the turn-off loss is significant. Also, the
bottom switch body diode reverse-recovery problem is a
major contributor to the poor efficiency at high frequency.
As a result, some other topologies are proposed in order to
improve the performance of the 12V-input VRM [2-5]. Of
these, the tapped-inductor (TI) buck converter is very
attractive for its simple structure. It involves only a slight
modification of the original buck converter. Section II
describes both the advantages and disadvantages of this
converter’s use in VRM applications. Section III introduces a
lossless clamp circuit with the modified TI buck converter in
order to solve the existing problems. The design of multiphase interleaving TI buck VRM is discussed in Section IV,
and the simulation and experimental results in Section V
verify the significant performance improvement.
II. TAPPED-INDUCTOR BUCK CONVERTER
Q1m
Lm
Q2m
Fig. 1. Multi-phase interleaving buck converter.
* This work was supported primarily by the VRM consortium. Also, this
work made use of ERC shared facilities supported by the National Science
Foundation under Award Number EEC-9731677.
Fig. 2 shows a TI buck converter, in which a tapped
inductor takes place the output filter inductor in the
conventional buck converter. This allows different
inductances between the charging and discharging periods.
Inductance of winding w1 and w2 is effective during the
charging period, while inductance of only winding w1 is
effective during the discharging period. In another word, the
265
TI buck converter adds a second coupled winding w2 in the
conventional buck converter. The turns ratio is defined as:
n=(w1+w2)/w1.
(4)
This modification introduces an extra degree of freedom, in
that the tapped inductor turns ratio “n” may be selected for
the most benefit to the VRM applications.
For the TI buck converter in Fig. 1, n should always be
greater than one.
n:1
speeds are the same, which means symmetric transient
response can be achieved.
The most significant improvement of the TI buck converter
is that it can have less switching losses. First, the switching
current of the top switch is much smaller compared with that
in the conventional buck converter. If the inductance is large
and the current ripple is relatively small (and can therefore be
ignored), the top switch switching current is:
Io
.
(8)
i =
off
Vo
w2
Q2
Q1
Vin
12V
n − (n − 1) ⋅ D
The increased turns ratio allows the switching current to be
greatly reduced. For example, the switching current can be
reduced by about half when n=2.
w1
Co
12
Current Slew Rate (A/s)
Fig. 2. A TI-Buck converter.
2.1. The advantages of the TI buck converter
From the voltage-second balance on the inductor, the
switching duty cycle of the TI buck converter can be derived.
n ⋅ Vo
.
(5)
D=
Vin + ( n − 1) ⋅ Vo
If n=1, (5) shows the same result as (1), which is the duty
cycle of the conventional buck converter. When n>1, the duty
cycle increases with the increase of n. Fig. 3 shows the trend
clearly with 1.5V output voltage. For example, the duty cycle
is almost doubled when n=2. As a result, the TI buck
converter can extend the duty cycle with the same input and
output voltage. The problem in the conventional buck
converter about the small duty cycle can be solved.
0.6
Duty Cycle
0.5
0.4
(Vin=12V, Vo=1.5V)
10
8
Curre nt Rising Speed
6
4
Curre nt Falling Speed
2
0
1
2
3
4
5
6
(n) Turns Ratio
7
8
Fig. 4. Relationship between inductor current slew rate and turns ratio.
Another way the loss can be reduced is that the bottom
switch body diode reverse-recovery problem is greatly
relieved by the leakage inductance of the tapped inductor.
When the top switch is turned on, the di/dt of the diode
reverse-recovery current is limited by the leakage inductance.
However, in the conventional buck converter, the only
limitation for this di/dt is the very small parasitic inductance.
Smaller di/dt means smaller reverse-recovery peak current
and less reverse-recovery loss.
2.2. The existing problems in the TI buck converter
0.3
0.2
Buck Converter
0.1
(Vin=12V, Vo=1.5V)
0
1
2
3
4
5
6
(n) Turns Ratio
7
8
Fig. 3. D-n relationship in the TI buck converter.
Since the charging and discharging inductances are
different in the TI buck converter, it is possible to achieve the
same inductor current rising and falling speeds by choosing a
suitable turns ratio. When the top switch is turned on, the
inductor current rising speed is:
di/dt|rise=(Vin-Vo)/(n2 Lw1).
(6)
When the top switch is turned off, the inductor current falling
speed is:
(7)
di/dt|fall=Vo/Lw1.
In both (6) and (7), Lw1 represents the inductance of winding
w1.
Fig. 4 shows the inductor current rising and falling speeds
(the current slew rate) as related to the turns ratio with 1.5V
output voltage and normalized inductance over winding w1.
When n is about 2.5, the inductor current rising and falling
Although the TI buck converter has many benefits,
including extended duty cycle, symmetric transient response
and less switching loss, there are two problems limiting its
wide applications in practice.
First, there is the gate-driving problem. Fig. 2 raises the
question of how to drive the top switch. A transformerisolated gate driver will degrade the simplicity of the original
power converter besides the fact that this driving method is
not good in very high-frequency applications. The simple
bootstrap gate driver can still be used. However, the source
voltage of the top switch becomes negative when the top
switch is turned off. The driving voltage level for the top
switch will be:
Vgtop=Vcc+(n-1) Vo,
(9)
where Vcc is the control voltage level, which is normally
equal to Vin. If the n is too large, the driving voltage may be
too high for the applications.
The most serious problem for the TI buck converter is the
leakage energy. It is impossible for the tapped inductor to
achieve a perfect coupling effect so that leakage inductor
exists in the circuit. When the top switch is turned off, the
266
current in the leakage inductor of winding w2 cannot be
reflected to winding w1, so it continuously goes through the
drain-to-source capacitor of the top switch. All of the energy
stored in the leakage inductor will be transferred to this small
capacitance, causing a huge voltage spike across the top
switch. This voltage spike not only increases the switching
loss, but also can destroy the top switch.
Some methods have been proposed to solve these
problems, especially the leakage energy problem [3,6].
Although all the proposed methods feature the lossless
characteristic (which is better than the conventional RLC
clamp circuit), they employ a coupled third winding, which
increases the circuit complexity. A simple clamp circuit,
which solves all the problems in the TI buck converter, is
proposed in the next section.
∆VCs =
n:1
Vo
Vin
12V
w1
Co
Q2
Fig. 5. Modified structure of the TI buck converter.
Based on this modified circuit structure, a simple lossless
clamp circuit with two diodes and a capacitor is proposed, as
shown in Fig. 6. Fig. 7 shows the key operation waveforms.
The operation principle is as follows.
w2
w1
Vo
Q1
Ds1
Vin
iL2
Cs
-
+i
Cs
Ds2
Bootstrap
Gate
Driver
Co
Q2
Clamp Circuit
Fig. 6. Lossless clamp circuit for the TI buck converter.
During top switch Q1’s turn-on period, the steady-state
voltage across the clamp capacitor Cs is:
VCs0=(Vin-Vo)/n+Vo.
(10)
Here, the diode forward voltage drop is ignored. When top
switch Q1 is turned off, the current in the leakage inductor
will go through Cs and Ds1 so that the leakage inductor
energy will be stored in clamp capacitor Cs. If Cs is large
enough, the increased voltage across Cs is relatively small
and the value is about:
.
(11)
2 ⋅ Cs ⋅ VCs 0
VgQ1
iCs
VCs
VCs0
VdsQ1
The gate-driving problem is easy to solve by simply
rearranging the connections of the tapped inductor and power
devices. Fig. 5 shows this circuitry change. The tapped
inductor looks more like two coupled inductors. With this
change, the source of the top switch is connected with the
drain of the bottom switch, so that the bootstrap gate driver
can be used without any limitation from the turns ratio.
2
As a result, the turn-off voltage stress across top switch Q1 is
effectively clamped as:
Vdspeak=Vin+VCs0+∆VCs.
(12)
When turns ratio n is greater than 2, this voltage stress across
the top switch is less than 23V, so the 30V power MOSFETs
can still be used.
III. A NOVEL LOSSLESS CLAMP CIRCUIT
w2 Q1
Bootstrap
Gate
Driver
Lleak ⋅ ioff
∆VCs
Vdspeak
0V
Fig. 7. Key operation waveforms for the lossless clamp circuit.
When top switch Q1 is turned on, the extra energy stored
in the clamp capacitor will be discharged to the output
through Ds2 and winding w1. The voltage across Cs will go
back to VCs0, the steady-state value. Therefore, all the leakage
energy is totally recovered to the output.
The voltage stress across the bottom switch Q2 is:
(13)
Vds2peak= VCs0+∆VCs.
This value is less than Vin. Low-voltage power MOSFETs
(less than 30V) with much smaller Rdson can be used to
reduce conduction losses.
The currents through Ds1 and Ds2 are very narrow pulse
currents related to the leakage energy, so Ds1 and Ds2 can be
small. If the tapped inductor is designed to have small
leakage inductance, a 1 to 2 microfarad capacitance is large
enough for the clamping function. The Cs package can be
extremely small. Briefly put, this clamp circuit features
simple structure, small size and low cost.
However, there is a limitation for the application of this
lossless clamp circuit with some turns ratio design. For an
ideal TI buck converter without leakage inductance and
clamp circuit, when top switch Q1 is turned off, the voltage
across winding w2 is:
VL_w2=(n-1) Vo.
(14)
This voltage must be smaller than the VCs0 in (10) to maintain
correct operation. Otherwise, instead of the intended small
pulse current, a large current will continue charging and
discharging Cs. From (10) and (14), the limitation for this
clamp circuit application is:
Vin
(15)
n≤
+1 .
Vo
For 12V-input VRM applications, the Vin-to-Vo ratio is
normally larger than 6, and n should be less than 3 for
symmetric transient response. So the limitation is not a
problem for this circuit’s use in VRM design.
Fig. 8 shows the simulation results for this clamp circuit
using a 2uF clamp capacitor. The tapped inductor is designed
267
with n=2, 300nH for the inductance of winding w1, and 0.95
coupling coefficient. The output is 1.5V with 12.5A DC
current. The switching frequency is 300KHz. The simulation
results prove the operation of this clamp circuit. All the
results are in agreement with the previous analysis. The small
errors are due to the diode forward conduction drop in the
simulation circuit.
w2 because this is the simplest structure for a tapped
inductor. Another reason for the small turn ratio is the
moving zero in the right half plane (RHP) [8,9]. This RHP
zero reduces the system feedback loop phase margin and can
impact the transient response.
Ro ⋅ [ n + 2 ⋅ D ⋅ (1 − n)]
(16)
Z
=
Le ⋅ (n − 1) ⋅ D
n 2 ⋅ Lw1
Le =
[ D + n ⋅ (1 − D)]2
RHP
VgQ1
(17)
Here, Ro is the output load. The RHP zero moves with the
output load; full load is the worst case. Fig. 9 shows the
relationship between the RHP zero and the turns ratio at full
load condition. A large turns ratio moves the RHP zero to the
low frequency range. Also, larger Lw1 means lower RHP zero
frequency. Since a higher-frequency RHP zero has less
influence on the system feedback, the turns ratio is designed
to be 2:1 instead of 3:1.
iCs
VCs
VdsQ1
RHP Ze ro (Hz)
VdsQ2
22V
7V
1 .10
6
1 .10
5
1 .10
4
1 .10
3
Lw1 =300nH
Lw1 =600nH
Vo
2
3
4
5
6
7
8
(n) Turns Ratio
Fig. 8. Simulation results for the lossless clamp circuit.
Fig. 9. The influence of turns ratio on RHP zero.
IV. VRM DESIGN WITH THE TI BUCK CONVERTER
A 12V-input and 1.5V/50A-output VRM is designed
incorporating the TI buck converter. A four-phase
interleaving structure is used for the large output current and
current ripple cancellation. For multi-phase current sharing,
the lossless method is used [7]. The 30V power MOSFETs
Si4884DY and Si4874DY are selected as the top and bottom
switches respectively. Here, device selection is not optimal
since 12V power MOSFETs with lower Rdson could be used
as the bottom switch. Switching frequency is 300KHz for
best device operation.
The most important aspect is the tapped-inductor design,
which is related to the efficiency, transient response and
VRM size. Planar core structure is selected for the low
profile, high power density design. The inductor winding can
be realized with the PCB copper trace in order to both
simplify assembly and reduce cost. Also, the solder point
resistance can be eliminated, which is very helpful for large
winding current.
Fig. 4 shows that the best turns ratio for the tapped
inductor is about 2.5 for a symmetric transient response.
Since large currents go through winding w1 during the
freewheeling period, w1 should be one-turn winding to
reduce the conduction loss. As a result, one-turn or two-turn
windings can be used for w2 in order to achieve almost
symmetric transient response. One-turn design is selected for
The inductance of winding w1 is designed to be 300nH as
a trade-off between the transient response and efficiency. A
small inductance can increase the current slew rate (6 and 7)
but will also increase the RMS current and switching current
through the power MOSFETs. Fig. 9 shows that a smaller
inductance can relieve the influence of the RHP zero.
Magnetic integration technology [10] is adapted for twophase tapped inductors in order to shrink the inductor size. To
achieve flux cancellation in the center leg of an EI core, the
phase difference should be 180 degrees. Fig. 10 shows the
integrated inductor structure with PCB as windings. Here,
Phillips EI-18-3F3 core is selected. There is no air gap in the
central leg, so these two inductors are totally decoupled.
W1 for L1
Gap
Core
W1 for L2
PC Board
W2 for L1
W2 for L2
Fig. 10. The integrated magnetic structure.
For the four-phase interleaving TI buck VRM, each phase
has a clamp circuit. Schottky diodes with low current ratings
are used for diodes Ds1 and Ds2 since they can reduce the
conduction loss and overall size. A 2.2uF 1206 package
ceramic capacitor is selected as clamp Cs. The clamp circuit
is so small that it has little influence on the whole VRM size.
268
V. SIMULATION AND EXPERIMENTAL RESULTS
iQ1
A four-channel interleaving buck converter was also built
for comparison with the four-channel TI buck converter. Both
have the same power rating, power devices and components
except for the inductor design. Since the discharging period is
the worst case of transient response for both the buck and the
TI buck converters, it can be derived from (3 and 7) that the
same discharging inductance can achieve the same transient
response [2]. Also, the same crossover frequencies for the
feedback loops are required.
Fig. 11 shows the simulation comparison of switching
currents between the buck and TI buck converters. The total
conduction losses of the top and bottom switches are almost
the same since the RMS current of the top switch is slightly
reduced but the RMS current of the bottom switch is slightly
increased. However, the turn-off current of the top switch in
TI buck converter is reduced significantly, which can help to
reduce the switching loss. It is obvious that the duty cycle is
almost doubled in the TI buck converter.
20.23A
iS1
Buck
(irms=4.88A)
10.51A
VgQ2
VdsQ1
VdsQ2
(a)
VgQ1
VgQ2
iQ1
7V
TI Buck
VdsQ2
(irms=3.58A)
19V
VdsQ1
iS2
Buck
TI Buck
(irms=12.3A)
(irms=12.85)
(b)
Fig. 12. The TI buck converter: (a) without clamp and (b) with clamp.
Fig. 11. The switching current comparison between buck and TI buck.
Phase 1
Fig. 12 shows the experimental result comparison for the
TI buck converter with and without the clamp circuit at fullload condition. Without the clamp circuit, there is a huge
voltage spike across the top switch when it is turned off. The
energy in the leakage inductor has no way to go except into
the drain-to-source capacitor of the top switch. In the test at
full-load condition, the voltage spike is so high that the top
switch is destroyed. However, with the clamp circuit, this
leakage energy can be stored in the clamp capacitor and
recovered to the output. The voltage stress across the top
switch is perfectly clamped below 20V.
Fig. 13 shows the current-sharing tests in the four-phase
input currents at both zero-load and full-load conditions.
Since the PCB winding is used, the inductor parasitic
resistance of these four inductors can be closely matched,
which is the key factor in perfect current sharing [7]. During
the test, the four phases’ input currents are almost the same
for the whole load range.
Fig. 14 shows the test efficiency comparison between the
four-phase buck VRM and the four-phase TI buck VRM. The
superiority of the TI buck converter with clamp circuit is
significant. Curve 2 only goes to 40A output because without
the clamp circuit, the top device is destroyed at higher output
current.
269
3A/div
Phase 3
3A/div
Phase 4
3A/div
Phase 2
3A/div
(a)
6A/div
6A/div
6A/div
6A/div
Phase 1
Phase 3
Phase 4
Phase 2
(b)
Fig. 13. Current sharing in the four-channel TI buck VRM:
(a) Io=0A and (b) Io=50A.
90
Efficiency (%)
ACKNOWLEDGEMENTS
1
85
2
80
The authors would like to thank Siliconix for supplying
free device samples.
3
75
70
1. TI Buck with Clamp
65
2. TI Buck w/o Clamp
REFERENCES
[1]
3. Buck Converter
60
0
10
20
30
40
[2]
50
Load Current (A)
[3]
Fig. 14. The efficiency comparison.
Fig. 12 shows that the voltage stress of the bottom switch
is only about 7V. As a result, 12V power MOSFETs can be
used to further reduce the Rdson. For example, the 12V trench
MOSFET Si4838DY (with the same package as the 30V
Si4874DY) can reduce the Rdson from 7mΩ to 3mΩ and the
gate driving voltage level drops from 10V to 4.5V. The whole
VRM efficiency will be improved by about 3% with this new
device.
[4]
[5]
[6]
[7]
VI. CONCLUSION
[8]
The TI buck converter is introduced in this paper, and a
novel lossless clamp circuit is proposed to solve the
converter’s leakage energy problem. With the help of the
simple clamp circuit, which features small size, low cost,
perfect switch voltage stress clamping, and full energy
recovery, the TI buck converter proves to be an excellent
candidate for 12V-input VRM applications.
[9]
[10]
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