IQ modulators advance reconfigurable radio

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IQ modulators advance reconfigurable radio
While true software-defined radio has yet to be implemented cost effectively
for general applications, improvements in signal-processing functions such
as IQ modulators move the RF industry ever closer to that goal.
By Eamon Nash
T
reconfigurable radio defies a broadly agreed
definition. A reconfigurable radio might
be defined as one or more of the following:
1. A common PCB that can be selectively
populated during manufacture to provide
operation at a particular frequency using
one of a number of possible air interfaces.
2. Fixed hardware that can operate at one
frequency using one or more air interfaces.
3. Fixed hardware that can operate at
multiple frequencies using one air interface.
4. Fixed hardware that can operate at
multiple frequencies using multiple air
interfaces.
Most systems engineers would agree
that the last point above describes a true
SDR. Figure 1 shows a conceptualization of
a direct-conversion signal chain. First, the
challenges associated with designing such
a signal chain will be considered, and then
upconverter architecture implementations
will be examined.
The data to be transmitted is first encoded
in a digital baseband processor. In a reconfigurable radio, this processor will require
he popularity of reconfigurable radios
is increasing as wireless infrastructure
equipment manufacturers try to design
platforms that cover multiple frequencies
and air interfaces. The market continues to
strive to achieve the ideal of a softwaredefined radio (SDR). While this research
continues, incremental developments are
taking place that provide common platform
designs. Designs are then configured during
manufacture, providing an overall savings
in development costs.
Because of their simplicity and the limited
number of spurious components they generate,
direct-conversion signal chains are becoming a popular architectural choice in many
radios, especially in reconfigurable platforms.
IQ modulators and demodulators are key
components in direct-conversion transmitters and receivers. This article will focus on
using IQ modulators in reconfigurable radio
transmitters.
Definitions
Like many evolving technologies, the term
a certain level of flexibility so that it can
be reprogrammed as the air interface
changes. While this function could be implemented using a standard digital signal processor (DSP) or using a field-programmable
gate array (FPGA), the main challenge is
to put in place enough processing power so
that the system is capable of encoding the
most complex of the air interfaces to be
supported. The downside of this approach
is that when the processor is encoding a low
data rate signal into a relatively simple air
interface (e.g., QPSK), processing power will
exceed demand.
Once the data has been encoded and filtered
in the digital domain, it is converted to an
analog signal that can be in complex (I,Q) or
real format (low IF). In either case, this signal
must be filtered to remove Nyquist sampling
images and broadband noise. This presents
the first hardware challenge to implementing
a complete software radio since different air
interfaces will require different filter bandwidths and shapes. As a result, some kind
of programmable filtering will be necessary.
I
Baseband
generator
Digital
to
analog
conversion
Power
amp
Upconverter
Q
Baseband
filter
Band
filter
Local
oscillator(s)
Figure 1. A reconfigurable radio transmitter.
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DAC
Baseband
Data
Bit to Symbol
Encoder
Pulse
Shaping
Filter
90°
0°
�
RF(t)
DAC
Figure 2. QPSK modulation using an IQ modulator.
There is, however, an alternative to this.
If a DAC is selected with high resolution
and a very high sampling rate, its broadband
noise will be low and Nyquist images will
appear at high frequencies. As a result, it may
be adequate to implement a fixed baseband
filter whose corner frequency is higher than
the broadest bandwidth to be transmitted
but still low enough to remove the Nyquist
images. As in the case of the baseband
34
processor, the downside of this approach is
that high-performance hardware (i.e., the
DAC’s LSBs) will sometimes go unused.
The next step is to upconvert the baseband
signal to the radio frequency. In general,
one or more local oscillators are required
to mix the RF signal with the baseband
signal. Although it is not difficult to design
a frequency-agile oscillator, which can
operate within a particular frequency band,
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design of broadband oscillators is more
challenging. Generally, the design is limited
by the tuning range of the voltage-controlled
oscillator (VCO). Since VCO tuning ranges
are typically 100 MHz to 200 MHz (for
VCOs operating in the 1 GHz to 3 GHz range),
an alternative approach must be taken
if the radio is to operate across a multiGigahertz range. One option is to operate the
PLL/VCO at a high base frequency and use
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10.0
0.0
Output Power (dBm)
FMOD-4
FMOD-2
FMOD-3
FMOD-1
FMOD-0
-10.0
-20.0
Sideband Suppression (dBc)
-30.0
-40.0
-50.0
-60.0
-70.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Frequency - GHz
Figure 3. Five pin-compatible IQ modulators combine to provide high-quality broadband operation
up to 4.5 GHz.
Q
D
LO
CK
D
Q
Q
LO
IOUT
CK
Q
QOUT
IQ modulator operation
vs. frequency
time
Figure 4. A digital circuit can be used to implement a broadband phase splitter. However, a 2XLO
must be applied with a precise 50% duty cycle.
programmable frequency dividers to set the
frequency at the input of the upconverter.
In addition to this requirement, the phase
noise requirements and phase lock time of
the oscillator will change with the air interface. Once again this calls for design of an
oscillator whose phase noise and lock time
conform to the requirements of the most
demanding air interface.
Inside the upconverter, reconfigurability
creates additional challenges. If a superheterodyne upconverter is chosen, careful
frequency planning will be required if
broadband frequency agility is required. In
addition, the filters that are required at each
36
quadrature phase shift keyed (QPSK) carrier.
The IQ modulator consists of two multipliers
(mixers) whose outputs are combined and a
signal splitter whose outputs are in quadrature
(i.e., separated by 90°).
So, we can think of the IQ modulator
as a pair of multipliers that are each driven
by fixed vectors separated by 90°. Because
the outputs of the two multipliers are combined, the signals applied to their second
inputs (the I and Q inputs) give us the ability
to generate arbitrary RF vectors and to control
their instantaneous amplitude and phase.
We begin with a simple bitstream (in the
context of IQ modulation, it is simpler to
think of the bitstream consisting of -1 and
+1 logic states instead of using the more
conventional labels of 1 and 0). This bitstream is split into two equivalent bit-streams,
each with half of the data rate of the original.
These bitstreams are oversampled and lowpass filtered (in the digital domain) to reduce
the sidelobes and bandwidth of the final
carrier. The two digital bitstreams are then
applied to two digital-to-analog converters
(DAC). The output signal from each DAC
will again be low-pass filtered to remove DAC
images (and possibly some of the DAC’s
broadband noise). Finally, the two baseband
signals are applied to the in-phase (I) and
quadrature (Q) inputs of the IQ modulator.
A phase locked loop (PLL) drives the
local oscillator (LO) input of the IQ modulator.
As previously noted, this signal is split into
two equal components separated in phase
by 90°. When these quadrature LOs are
multiplied with the filtered baseband signals,
the combined result is a modulated carrier
with four phase states or symbols. Each symbol represents two databits from the original
datastream (i.e., two bits per symbol).
intermediate frequency (IF) will have to
have programmable bandwidth to deal with
the variable bandwidth of the signal being
transmitted.
Regardless of the architecture of the
upconverter, a number of unwanted components will appear at its output; the architecture
will merely influence the location and number
of these unwanted components. There will
always be some broadband noise that may or
may not require filtering.
Operation of an IQ modulator
Figure 2 shows a representation of how
an IQ modulator generates and transmits a
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In an ideal reconfigurable transmitter, a
single IQ modulator would be used to cover
all frequencies and air interfaces. However,
in practice, most IQ modulators do not
exhibit broadband performance. Consider
the phase splitter that generates the quadrature
signals that drive the two mixers. Polyphase
filters, which are commonly used to generate
precise quadrature in IQ modulators, have
limited bandwidth. In practice, good quadrature balance (< 0.5º) is achievable over 1.5
to 2 octaves of frequency using a polyphase
filter. Outside of this range the two outputs
of the phase splitter will no longer be 90º out
of phase with respect to each other. This will
result in the symbols being modulated at the
wrong phase angle. In addition, if there is
any gain imbalance between the I and Q arms
at the modulator input, the symbols will have
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10
0
SSB Output Power (dBm)
-10
-20
-30
Sideband Suppression (dBc)
-40
-50
-60
-70
0
500
1000
1500
2000
Output Frequency (MHz)
Output Power
(dBm)
Figure 5. A modulator with a 2XLO phase splitter provides excellent quadrature across multiple
octaves.
GSM
10
0
WCDMA
7 dB Headroom P
OUT
(GSM)
OP1dB
(ADL5372)
22 dB
Headroom
POUT
(WCDMA)
-10
-20
Noise (dBm/Hz)
ACP (dBc)
-30
-40
ACP Limit
-50
-60
-70
ACP Limit
(400 KHz Offset)
11 dB Margin
ACP-ADL5372
-150
ACP-ADL5372
Noise Limit
(6 MHz Offset)
-140
-145
29 dB Margin
Noise Limit
(20 MHz Offset)
12 dB Margin
Noise-ADL5372
-155
12 dB Margin
Noise-ADK5362
-160
Figure 6. Level planning and specification compliance for an IQ modulator operating in GSM and
WCDMA modes.
slightly different power levels. These amplitude
and phase errors in the modulator will combine
to degrade the error vector magnitude (EVM)
of the modulated carrier. Sideband suppression
is a commonly used metric that expresses the
combined effect of imprecise quadrature and
imbalance between the I and Q channels of
the modulator.
In general, the gain and output power of
an IQ modulator will also vary with frequency.
Since the noise floor of an IQ modulator
tends to remain flat over a broad frequency
range, this results in a dynamic range that will
vary with frequency.
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Figure 3 shows the nominal output power
(approximately 6 dB below the 1 dB compression point) and sideband suppression for a
family of five pin-compatible IQ modulators.
Each device has been designed to provide
optimum output power and sideband suppression over a relatively narrow frequency
range. The output power and sideband suppression of the family remains relatively
constant over a frequency range from 250 MHz
to 4.5 GHz. Note that these devices each deliver
a frequency-independent output noise floor of 158 dBm/Hz, resulting in a dynamic range that is
relatively flat across a broad frequency range.
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Figure 4 shows a simplified schematic of
an alternative phase splitter design that is
used in some IQ modulators. This is essentially a digital circuit that uses D-type
flip-flops and an inverter to generate precise
quadrature. Unlike a polyphase filter circuit
where there is a natural frequency limitation,
no such limitation exists here. As a result,
excellent quadrature can be achieved over a
multi-octave frequency range. However, the
circuit does require an external LO operating
at twice the frequency of the desired LO
(commonly referred to as a 2XLO). In
addition, the duty cycle of the externally
applied LO is critical. Anything other than
a 50% duty cycle at the input will result
in quadrature errors at the output.
Figure 5 shows the output power and
sideband suppression of an IQ modulator
(ADL5385) that uses a 2XLO. The absolute
frequency range over which this device
operates is much smaller than the FMOD
family. However, in terms of octaves, it is
clearly a more broadband part with excellent
operation (sideband suppression ≤ -40 dBc)
from 50 MHz to beyond 1500 MHz (five
octaves). Notice also that the output power
vs. frequency is relatively flat. This does
come at the cost of slightly lower output
compression (approximately +10 dBm)
compared to the narrowband devices (approximately +12 dBm) while still maintaining
a broadband noise floor of -158 dBm/Hz.
Fixed frequency
reconfigurable radio design
Up to now, we have considered the
challenges associated with operation across
multiple frequencies. However, the design
of reconfigurable systems that operate in
a single band also presents level planning
challenges. As the air interface changes,
the headroom between signal levels and
compression points must vary so that the
various distortion and signal-to-noise targets
can be achieved.
Consider a software radio design example
in the context of the requirements on the
IQ modulator. Assume a common transmitter that can switch between the GSM and
WCDMA air interfaces operating at 1960
MHz or 2140 MHz. In the context of this
discussion, this range can still be considered “narrowband.” Figure 6 shows a
representation of the power, distortion and
noise levels at the output of the modulator along with the requirements from the
GSM and WCDMA air interface standards.
For this example, an IQ modulator which
is optimized for operation in the 1.5 GHz
to 2.5 GHz range (FMOD-2) should be
chosen. For GSM operation, the first step is
to choose an output power level. An output
power level of +5 dBm, which is well below
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the ADL5372’s +12 dB output compression point would be a
conservative value. Examining the spectral mask at 400 KHz offset
from the carrier, it is apparent that there is a comfortable margin
of 11 dB on the 60 dBc requirement. Note that in practice, the
modulator could operate quite a bit closer to the compression point
since the GMSK carrier has a constant envelope and its spectral
mask shows little sensitivity to headroom.
More critical is the noise spectral density at 6 MHz offset from the
carrier. In a typical +47 dBm transmitter, the requirement at the antenna
is a noise level of less than -36 dBm peak hold in 100 kHz measurement bandwidth. With the modulator running at +5 dBm output power,
this corresponds to a noise spectral density of -140 dBm/Hz (or -145
dBc/Hz). With the IQ modulator delivering only -152 dBm/Hz (-157
dBc/Hz), there is once again plenty of margin.
For WCDMA operation, a significantly lower output power level
must be chosen to provide more headroom to the modulator’s output
compression point. This will have a direct impact on adjacent-channel
leakage ratio (ACLR). While the requirement for this specification
is 45 dBc at the antenna, components at this point in the signal chain
are generally expected to dramatically exceed this requirement. In
this case, a single-carrier output power level of -10 dBm is chosen,
resulting in an ACLR of -75 dBc.
The maximum broadband noise that the WCDMA standard will
tolerate at the antenna is -30 dBm, measured in a 1 MHz bandwidth.
Assuming that the system operates at an output power of +45 dBm and
the modulator is running at -10 dBm, this corresponds to a noise power
level at the modulator output of -85 dBm in 1 MHz bandwidth or
-145 dBm/Hz. At -157 dBm/Hz, we have 12 dB margin.
In the GSM and WCDMA case, the broadband noise has significant
margin on the overall requirement at the antenna, even with the carriers generously backed off from the modulator’s compression point.
Therefore, it is arguable that a transmitter could be built with limited
noise filtering. As noted before, some baseband filtering will always
be required to filter out DAC sampling images. At the modulator
output, however, only the harmonics of the LO and receive-band
noise require filtering, because the unfiltered broadband noise is
already well below the required limit.
Advancing toward true SDR
Significant obstacles still stand in the way of mass manufacture and deployment of infrastructure-grade software-defined
radios. However, advances in IQ modulators are bringing this goal
closer. The increased dynamic range of modern IQ modulators
allow for transmission of various air interfaces at different power
levels while maintaining adequate noise and distortion margin.
Broadband frequency agility can be achieved by choosing one of a
family of pin-compatible devices during manufacture. Alternatively,
by choosing an IQ modulator with a 2XLO, broadband operation
can be achieved across multiple octaves with a single device, bringing
the goal of a true SDR closer to reality. RFD
ABOUT THE AUTHOR
Eamon Nash is applications engineering manager for RF standard
products at Analog Devices. He has worked at Analog Devices for
16 years, first as a field applications engineer, based in Germany,
covering mixed signal and DSP products, then as product-line applications engineer specializing in RF building-block components
for wireless applications. He holds a Bachelor of Engineering
degree in electronics from the University of Limerick, Ireland. He
can reached at (781) 937-1239 or eamon.nash@analog.com.
Copyright© 2006 AR Worldwide. The orange stripe on AR Worldwide products is Reg. U.S. Pat. & Tm. Off.
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