Design and Implementation of a Low Cost
Power Factor Improvement Device
Sajid Muhaimin Choudhury
Department of EEE, Bangladesh University of Engineering and Technology
Dhaka-1000, Bangladesh
smc@ieee.org
I. INTRODUCTION
Power factor correction has two parts: reduction of the
harmonic content and aligning of the phase angle of incoming
current so that it is in phase with the line voltage [1]. For low
power factor loads, cost can be significantly minimized by
using a power factor improvement device, and a very well
established method for doing so is using shunt capacitors [2].
Now most of the PFIs are based on ASIC or Microcontrollers.
Here, a simplified approach was taken to design a power
factor improvement device without ASIC or Microcontrollers.
For this PFI device, only three capacitor banks were used but
provisions were kept for easily increasing number of banks.
For each different values of resistance, the phase shift was
measured and the inductive reactance was calculated. The
effect of the change of load current is illustrated in Fig. 1. An
interpolating function for the inductance as a function of
power-factor was determined in MATLAB using the
experimental results, as shown in Fig. 2.
Inductive Reactance vs Load Current
8
7.5
Inductive Reactance (kΩ )
Abstract— A low cost single phase Power Factor Improvement
(PFI) device was designed and implemented for small signal low
power loads. The designed PFI keeps the power factor of a load
within a specified but adjustable range (0.85-0.90) if the load is
within its capacity. The design involved designing of a small
signal model load, selecting appropriate capacitors, and
designing appropriate switching circuits to select proper
combination of capacitors. The power factor improvement device
was simple, low cost and it is an innovative way to demonstrate
the logic of switching the capacitors. The components used were
standard logic chips and no Microcontroller or Application
Specific Integrated Circuit (ASIC) was used.
6.5
6
5.5
5
4.5
4
0
0.2
0.4
0.6
0.8
Load Current (mA)
1
1.2
1.4
Fig. 1 Experimental Inductive reactance vs Load Curve plot
II. DESIGN
Inductive Reactance vs Load Power Factor
8
7.5
y = - 16*x 2 + 31*x - 7.1
7
Inductive Reactance (kΩ )
A. Load Design
The PFI was constructed for small signals only, in mW
range. For such small signals very high values of inductors
were required. To reduce the cost, the load was constructed
using resistors, and the primary coil of a small 12V-240V
transformer with secondary side open. The iron core of the
transformer has high magnetic permeability. So the
magnetizing reactance can give appropriate low power factor
to test the PFI. But as the iron core has non-linear
characteristics, its inductance changes with the change of
current. So the load was constructed and tested, and the
inductance was determined experimentally for different
currents, and thus different power factor for fixed resistor and
line voltage.
The magnitude of voltage and currents of the load were
determined using a Digital Multimeter and an oscilloscope
was used to determine the phase-shift. The cosine of the
phase-shift gave the power factor. The impedance can be
written as X L = R tan θ
7
6.5
6
5.5
5
data 1
quadratic
4.5
4
0.5
0.6
0.7
0.8
Load Power Factor (cos Θ)
0.9
Fig. 2 Experimental Inductive Reactance vs Load Power Factor
Characteristics of constructed load
1
The relation between inductive reactance and power factor
can be written as:
X L = −1.6 cos 2 θ + 31cos θ − 7.1
Where, cos θ is the power factor of the load.
B. Capacitor Design
The capacitors are selected in such a manner, so that it can
improve the overall power-factor of the system, for different
values of low load power factors.
L
V1
C
R
0
For a good PFI design, the (N-1) curves (excluding the
curve for zero capacitance) should be in such a way that in the
operation range, any vertical line should intersect with at least
one curve in the desired power factor range. In this case,
system will be stable and no recurrent changes between two
capacitance levels will continue to occur. For the simulation,
the power factor range was assumed to be 0.85-0.90. For
practical cases, the range can be chosen as two values very
close to unity.
For the design, the rated load and minimum power factor
(worst case) for which the PFI could operate was chosen, and
the corresponding reactive power was calculated. If there are
N capacitor banks, the reactive power supplied by the smallest
capacitor at line voltage is 1/2N times the reactive power of the
worst case. Capacitance is thus calculated using the formula,
QC
C =
2πf V 2
where QC is the reactive power supplied by the smallest
capacitor bank at rated voltage. Each of the successive
capacitor banks has twice the capacitance of its immediate
smaller bank. For the load, the values of capacitance bank are
shown in Table I
TABLE I
VALUES OF CAPACITANCE BANKS
Fig. 3 Simplified load model
For the simplified load in Fig. 3, an expression for overall
power-factor angle can be written as:
1
⎛
⎞
θTotal = tan −1 ⎜ tan θ(1 − ω2 LC) −
ω2 LC ⎟
tan
θ
⎝
⎠
Here the ω = 2πf where f is the line frequency
Using the expression, the effect of shunt capacitance on
over all power-factor was simulated as shown in Fig. 4.
Load Power Factor vs Overall Power Factor
1
Capacitor Bank-1
0.032 μF
Capacitor Bank-2
0.065 μF
Capacitor Bank-3
0.132 μF
C. Logic Circuit Design
To implement the PFI, the phase difference between
voltage and current is required. The wave-shape of the current
was determined by measuring the voltage across a small series
resistor. For large loads instrumentation transformers can be
used, by considering appropriate phase-shifts.
0.95
Overall Factor (cosΦ)
0.9
Zero
C rossing
Detector
0.85 C = 1.89E-4 →
0.8 C =
C=
0.75
C=
0.7 C =
1.62E-4 →
1.35E-4 →
1.08E-4 →
S ubtractor
8.10E-5 →
H alf-wave
R ectifier
C = 5.40E-5 →
C = 2.70E-5 →
0.6
C = 0.00E+000 →
PW M signal
duty cycle
proportional
to phase shift
0.65
Zero
C rossing
D etector
0.55
0.5
0.5
0.55
0.6
0.65
0.7
0.75
Load Power Factor (cos Θ)
0.8
Fig. 4 Simulation of Model Load
0.85
0.9
Fig. 5. Phase shift to PWM Converter
The first step of phase shift measurement is shown on
Fig. 5. The voltage and current wave-shapes were converted
to square waves, and the current wave shape was subtracted
from the voltage wave-shape. When the subtracted wave was
half wave rectified, it gave a Pulse Width Modulated (PWM)
wave with duty-cycle proportional to the phase-shift. Only
problem is the duty cycle is same for leading and lagging
waves. For this Mekhilef et al. [3] used a separate counter to
determine the interval between positive cycle and negative
cycle. An alternative approach was used which involved phase
shifting of the current wave by 90° using a phase-shifter. Thus
for 90° lagging power factor, the PWM had zero duty cycle,
and the duty cycle increased linearly as the phase-shift was
increased from -90° to leading power factor.
The resulting PWM signal was then chopped using a high
frequency clock. The effect is illustrated in Fig. 6. Now the
number of high frequency pulses in one period gives a
measurement of the duty-cycle and thus the phase shift.
The algorithm of logical decision making is illustrated
using a flowchart in Fig. 8
B egin
Power factor M easurement
High
Frequency
C hopper
C ompare
the logical
voltage with the
extreme values
of the range of
the pf
pf is less than
targeted pf
Fig. 6 Effect of the Chopper circuit
A counter was used to count the number of pulses. The
original PWM signal was used to reset the counter as well as
to load the count value into a D flip-flop. The procedure is
illustrated graphically in Fig. 7.
PW M signal
duty cycle
proportional
to phase shift
Counter
R eset
R egister
L oad
High
Frequency
Clock
Fig. 7 Basic Principle of the Chopper circuit
The frequency of the chopper pulse train was selected in
such a manner, so that, for maximum phase shift the counter
counts very close to its upper limit, but less than its upper
limit. This was done to avoid overflowing of the counter, and
also to avoid unnecessary digitalization error. If line
frequency is f, then the maximum duty cycle would be 1/2f.
For an n-bit counter, and an n-bit register, there can be 2n - 1
number of counts. At 90° leading, the PWM has about 50%
duty cycle, and the pulse duration is 1/(2fline). Thus the
frequency of chopper is bounded by:
f Chopper ≤ 2f line (2n − 1)
At each falling edge of the PWM signal, the register was
loaded and the counter was reset. As a result the register is
refreshed fline times each second. The value of the register
indicates the duty cycle and thus the amount of phase shift
between the voltage and current wave. This value was then
used in logical decision making. To find the relation between
the count and the phase shift a calibration curve was obtained
as shown in Fig. 11.
pf is greater
than targeted
I ncrease C apacitance
D ecrease C apacitance
Fig. 8 Logic of the Control Circuit
Using the calibration curve, the value of register count for
two boundaries of the allowed power factor was calculated.
Two binary magnitude comparators were used to compare the
count of the phase shift detector with the calculated boundary
count values. If the count is outside the specified range, the
number of active capacitor banks will be changed.
To connect or disconnect the capacitor banks, relays were
used. To control the switching of relays, an up-down counter
was used; each bit of the up-down counter represented a
capacitor bank. At the same time, if the load power factor is
outside the desired operation range, all capacitor banks will be
connected in parallel to the load, and logic circuitry will
prevent further increase of the value of the up-down counter.
III. IMPLEMENTATION
The completed circuit implemented on breadboard is shown
on Fig. 9. As a power supply, centre tapped transformer was
used with bridge rectifier and filter capacitors. The tapping of
the used transformer was not very accurate, and there were
some problems regarding ground voltage levels while
operating the circuit. Nevertheless, the circuit could improve
the power factor of the model load. The resistive part of the
model load was a potentiometer and it was varied to test the
functionality of the circuit. Table II shows some ratings of the
load and circuit.
TABLE II
RATINGS OF CONSTRUCTED CIRCUIT
Input voltage
Max. Input Current
Min. Input pf
Min Switching time
6Vrms, line to line, single-phase, 50Hz
1.2mA
0.5 lagging
0.5 sec (adjustable)
Counter Count vs Phase Shift (Θ)
300
Data Point
Linear Interpolation
250
y = 1.4*x + 140
Counter Count
200
150
100
50
Fig. 9 The circuit constructed on bread board
0
-100
IV. OPERATION TESTING
At first the constructed load was tested to ensure that its
power factor could be varied within a wide range. The
experimental results of the load are shown in Fig. 10.
Load Real, Reactive and Apparent Power vs Load Current
7
0
Phase Shift (Θ)
TABLE III
FUNCTIONALITY TEST
Load
Δθ
Load
pf
Overall
5
Δθ
Overall
pf
0.8
4
0.6
3
0.4
2
0.2
1
54.0°
52.2°
50.4°
48.6°
46.8°
45.0°
43.2°
0.5877
0.6129
0.6374
0.6613
0.6845
0.7071
0.7289
31.5°
27.0°
30.6°
27.9°
28.8°
31.5°
27.9°
0.8526
0.8910
0.8607
0.8837
0.8763
0.8526
0.8837
0
0
0
0.2
0.4
0.6
0.8
Load Current (mA)
100
The results of overall functionality testing are shown in
table III. The design was done to keep power factor within
0.85 to 0.90
1
0
50
Fig. 11 Calibration curve of the phase-shift to digital count converter
Power Factor (in seperate scale)
Apparent Power (mVA)
Real Power (mW)
Reactive Power (mVAR)
6
-50
1
1.2
Fig. 10 Load Calibration Curves
The calibration curve for the phase-shift to digital count
converter is shown in Fig. 11. The experimental data were
interpolated in MATLAB The relation between the Count of
the counter and phase shift can be written as:
Counter Count = 1.4 * Phase-shift – 140
Phase shift = 0.74 * Counter Count – 80
Capacitor
Banks
(1=on, 0=off)
111
111
110
110
101
100
100
V. CONCLUSIONS
Implementation of a very simple and low cost power factor
improvement device is illustrated in this paper. Due to its very
simple nature the PFI does not deal with the problems that can
occur due to harmonics as done by Ayyanar et al. [4]. The key
feature of this design is simplicity and low cost without
microcontroller or ASIC.
REFERENCES
[1]
[2]
[3]
[4]
M. Chin 2005, ‘Power Fundamentals & Recommendations’, pp 5-7,
SPCR.
Retrieved
September
26th
March,
2008
from
http://www.silentpcreview.com/article28-page5.html
M. H. Shwehdi, M. R. Sultan “Power Factor Correction Capacitors;
Essentials and Cautions” Power Engineering Society Summer Meeting,
2000, Page 1317 vol. 3
S. Mekhilef and N. A. Rahim, ‘FPGA Based ASIC Power-Factor
Control For Three-Phase Inverter’, Proceedings of 2003 IEEE
Conference on Control Applications. Volume 1, 23-25 June 2003
Page:595 vol.1
Ayyanar, R.; Mohan, N.; Jian Sun ‘Single-stage three-phase powerfactor-correction circuit using three isolated single-phase SEPIC
converters operating in CCM’ IEEE 31st Annual Power Electronics
Specialists Conference, 2000. PESC 00. 2000 Volume 1, 18-23 June
2000 Page(s):353 - 358 vol.1