Vol. 34, No. 4
Journal of Semiconductors
April 2013
SRAM standby leakage decoupling analysis for different leakage reduction
techniques
Dong Qing(董庆) and Lin Yinyin(林殷茵)Ž
State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China
Abstract: SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors. Generally, four kinds of techniques are often utilized for SRAM standby leakage reduction:
Vdd lowering (VDDL), Vss rising (VSSR), BL floating (BLF) and reversing body bias (RBB). In this paper, we
comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It
is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and
temperature. This has been verified on a 65 nm SRAM test macro.
Key words: SRAM; standby power; leakage reduction
DOI: 10.1088/1674-4926/34/4/045008
EEACC: 1265D; 2570
1. Introduction
Standby power is a critical concern for application processors which spend much more time in standby (sleep) mode than
in wake mode. Although logic circuits can be gated to minimize the power, the SRAM array has to remain powered to retain dataŒ1 . Therefore, the SRAM array usually consumes the
most part of total standby powerŒ2 . It is of great importance to
reduce SRAM cell leakage to satisfy the need for low power
operation.
Many design techniquesŒ3 10 have been recently presented for SRAM cell leakage reduction, and they can be generalized as four types: (1) VDDL; (2) VSSR; (3) BLF; (4)
RBB. All of these techniques are useful in lowering the SRAM
standby power; however it is still unclear which one has the
best performance.
Istandby D Isub .PU/ C Isub .PD/ C Isub .PG/
C Igate .PU/ C Igate .PD/ C Igate .PG/
C Ijunc .PU/ C Ijunc .PD/ C Ijunc .PG/:
(1)
Figure 2 illustrates the relationship between temperature
and these leakage currents of an HVT 65 nm SRAM cell. Obviously, Ijunc and Igate nearly have no temperature correlation;
however Isub increases exponentially as the temperature rises.
From 27 to 85 ıC, Isub will multiply by 10X, which compels the
In this paper, we first decouple each leakage component of
a SRAM cell under standby mode and explore the relationship
between leakage composition and temperature. Then, we comprehensively analyze the results of each leakage component under the four different techniques. By analysis and comparison,
we can conclude that the performance of the four techniques
depends on the leakage composition and temperature. A 256
kB SRAM test macro has been fabricated in a 65 nm technology for demonstration.
2. SRAM standby leakage analysis
Figure 1 shows the SRAM standby leakage paths. Each
kind of transistor (PU, PD or PG) contributes 3 types of leakage: sub-threshold leakage (Isub ), junction leakage (Ijunc ) and
gate leakage (Igate ). The total SRAM standby leakage can be
expressed as:
Fig. 1. All standby leakage paths in the SRAM cell.
* Project supported by the National High Technology Research and Development Program of China (Nos. 2008AA031401, 2011AA010404),
the National ST Project (No. 2011ZX02502), and the Shanghai STC Project (No. 12XD1400800).
† Corresponding author. Email: yylin@fudan.edu.cn
Received 15 August 2012, revised manuscript received 5 November 2012
© 2013 Chinese Institute of Electronics
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Dong Qing et al.
Fig. 2. The relationship between temperature and each type of leakage
currents.
total standby leakage to escalate rapidly. Furthermore, the Isub
of NFET (PD and PG) increase much faster than that of PFET
(PU). The different temperature correlation of the 9 kinds of
leakage can greatly alter their proportion in total Istandby . At
27 ıC, Ijunc is slightly more than Isub (Fig. 3). But when the
temperature rises to 85 ıC, Isub occupies the most part (more
than 87%) while Ijunc and Igate can be negligible. Therefore,
leakage reduction techniques should consider both the temperature and the leakage composition.
3. Leakage reduction techniques analysis
To reduce the transistor leakage, designers tend to control the voltage values of the 4 transistor terminals namely the
gate, source, drain and body (including NW and PW). Isub can
be lowered by decreasing jVds j and increasing jVth j which can
be controlled by the reverse body bias. However, the reverse
body bias which enlarges the jVbd j will considerably raise the
Ijunc . As for the Igate , it can be divided into 2 parts: Igate.on/ and
Igate.off/ . Igate.on/ , deriving from GIDL, is proportional to jVgd j;
while Igate.off/ is much less than the other leakage by 1–2 orders
of magnitude.
As the four leakage reduction techniques take distinct control on SRAM transistor terminals, their leakage reduction effects are entirely different. Figure 4 shows the change of each
leakage with VDDL. It is clearly that lowering the VDD can
reduce the Igate of PU, PD and PG exponentially because of
the decreasing voltage difference between the gate and drain
with VDD dropping. In addition, the Isub of PU and PD are
also reduced with less jVds j, but VDD dropping will make the
voltage of storage node “1” lower than the BL and generate an
extra Isub path of the right PG. Moreover, Ijunc of PD and PG
decrease with falling jVbd j; while the Ijunc (PU) will increase
quickly with rising jVbd j owing to a stable 1.2 V PFET body
bias (NW). The change of Ijunc (PU) makes total Istandby decrease first and then increase under a lowering VDD. Figure 5
illustrates the VSSR’s effect on each leakage. The Igate can be
well reduced by raising the VSS. In addition, all the Isub are
decreased with no extra Isub path generated. Similar to VDDL,
VSSR can enlarge the Ijunc of NFET, and Ijunc will dominate
the total Istandby over 0.4 V VSS which is the optimized point
Fig. 3. (Color online) Leakage composition under different temperatures.
for Istandby . In Fig. 6, BLF can effectively deal with Ijunc (PG)
and Igate (PG) reduction. Total Isub can still be reduced though
extra Isub is induced on right PG. Figure 7 shows the result of
NW RBB, and Fig. 8 presents that of PW RBB. RBB will decrease Isub but increase Ijunc . Thus, if Isub is more than Ijunc ,
RBB is a good choice for Istandby minimization; otherwise it
will cause greater power consumption.
According to the above analysis, if Isub occupies much
more than the other 2 kinds of leakage type, VDDL, VSSR,
and RBB can be effective in total leakage reduction. And if
Isub of NFET is dominant, VSSR will be more promising. But
when Ijunc represents the biggest part, RBB will have a negative effect, and choosing the VDDL or VSSR depends on the
proportion of Ijunc (NFET) and Ijunc (PFET). If the leakage of
PG is a problem, BLF is demanding.
4. Test macro implementation
A 256 kB SRAM is designed for leakage reduction evaluation. The SRAM array consists of 4 banks, with each bank
containing 256 rows and 256 columns. In Fig. 9, each voltage terminal of the SRAM array is wired out for separate control. NW and PW are decoupled from VDD and VSS to realize
RBB. The test macro has been fabricated in a 65 nm technology
and the die photo is shown in Fig. 10. We measured the standby
power under the previously mentioned 4 techniques: (1) lowering VDD by 0.4 V; (2) raising VSS by 0.4 V; (3) floating BL
by 0.4 V; (4) reversing NW and PW by 0.4 V. Moreover, we
propose a combined leakage reduction method (lowering VDD
by 0.4 V C forward NW by 0.4 V C floating BL by 0.4 V). In
this method, VDDL can decrease all the Igate , Isub (PU) and Isub
(PD); the forward NW can avoid the Ijunc increasing; BLF can
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Dong Qing et al.
Fig. 4. (Color online) Leakage reduction effects of the VDDL.
Fig. 5. (Color online) Leakage reduction effects of the VSSR.
Fig. 6. (Color online) Leakage reduction effects of the BLF.
minimize the Isub (PG). This method is optimized for leakage
reduction below 32 nm technology which suffers more from
Ijunc .
5. Results and discussion
Figure 11 shows the measured results of leakage reduc-
tion under the 4 techniques and the proposed combinational
method. As expected, the combinational method possesses the
best leakage reduction performance under 0 and 27 ıC, because
Ijunc is larger than other kinds of leakage at low temperature.
For the same reason, RBB even increases the standby power
rather than decreasing it at low temperature. However, as the
temperature rises, Isub will increase exponentially and plays the
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Dong Qing et al.
Fig. 7. (Color online) Leakage reduction effects of the NW RBB.
Fig. 8. (Color online) Leakage reduction effects of the PW RBB.
Fig. 10. Die photo of SRAM test macro.
Fig. 9. Schematic diagram of a SRAM test macro.
4X.
dominant role. Thus, the combinational method is not as desirable at low temperature, but RBB and VSSR are preferable
because of their outstanding ability of NFET Isub control. At
85 ıC, RBB and VSSR can reduce the standby power by nearly
As CMOS scaled to below 32 nm technology, many new
process techniques have been induced for leakage reduction
like HKMGŒ3 and Fin-FET, both of which can greatly decrease
GIDL and the sub-threshold leakage. But junction leakage is
not easily effectively cut down. Therefore, junction leakage re-
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Dong Qing et al.
References
Fig. 11. Measured results of leakage reduction techniques.
duction should be paid more attention, especially for application processors which hardly work at extremely high temperatures. The proposed combinational method is quite promising
for all-round leakage reduction of SRAM in advanced process.
6. Conclusion
This paper presents a comprehensive decoupling analysis
of the four leakage reduction techniques influence on each kind
of leakage. From this perspective, it is concluded that the performance of these methods depends on the leakage composition of the SRAM cell and temperature. A 65 nm SRAM
test macro was fabricated to compare the 4 leakage reduction
techniques with a proposed combinational method. The combinational method is promising for Ijunc dominant SRAM cell
leakage reduction while VSSR and RBB are desirable for Isub
dominant.
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