FD‐SOI Technology Benefits
for SRAM at the 22nm Node
Tsu‐Jae King Liu
Department of Electrical Engineering and Computer Sciences
University of California, Berkeley, CA USA
Acknowledgements
Changhwan Shin, Min Hee Cho, Yasumasa Tsukamoto
Borivoje Nikolić
Bich‐Yen Nguyen and Carlos Mazure
SOI Workshop at IMEC, 16 October 2009
Outline
• Introduction
– Transistor scaling challenges
– Advanced transistor structures
• Thin‐BOX FD‐SOI Technology
• 6‐T SRAM Cell Performance
• Yield‐Aware SRAM Cell Design
• Summary
2
Historical Voltage Scaling
• Threshold voltage VTH cannot be scaled down aggressively.
Æ Supply voltage (VDD) has not been scaled proportionately.
log IDS
VDD
ION
IOFF
VDD – VTH
0 V
TH
VTH
VDD
VGS
Source: P. Packan (Intel), 2007 IEDM Short Course
K. Bernstein et al., IBM J. Res. Dev. 50‐4/5, 2006:
3
Sources of Variability
• Sub‐wavelength lithography:
– Resolution enhancement
techniques are costly and increase
process sensitivity
• Gate line‐edge roughness (LER):
– doesn’t scale with gate length
250nm
180nm
90nm and Below
Design
OPC
PSM
0°
Mask
180°
OPC
0°
180°
Wafer
photoresist line
• Random dopant fluctuations (RDF):
– Atomistic effects become significant
in nanoscale FETs
SiO2
Source
A. Brown et al.,
IEEE Trans.
Nanotechnology,
p. 195, 2002
Gate
Drain
• Gate work function variation (WFV)
A. Asenov, Symp. VLSI Tech. Dig., p. 86, 2007
4
6-T SRAM Cell
Impact of Misalignment
Desired layout
(6‐T SRAM cell)
PD
PU
Actual layout w/ lateral misalignment
(gate length variations)
PG
Lg reduced
PG
PU
Lg increased
PD
Actual layout
(corner rounding)
Actual layout w/ vertical misalignment
(channel width variations due to active jogs)
W reduced
W increased
5
Impact of Variability on SRAM
• VTH mismatch results in reduced static noise margin.
Ælowers cell yield, and limits VDD scaling
Circuit Schematic of 6‐T SRAM Cell
Butterfly Curve
Y. Tsukamoto et al., Proc. IEEE/ACM ICCAD, p. 398, 2005
ÆImmunity to short‐channel and narrow‐channel effects, as well
as random variations, is needed to achieve high SRAM cell yield.
6
Thin‐Body MOSFETs
• Short‐channel effects (SCE) can be suppressed by using
an adequately thin body region.
– Channel doping can be reduced Æ reduced RDF effects
… but then an alternative method of VTH adjustment is needed.
Ultra-Thin Body (UTB)
Lg
Double-Gate (DG)
Gate
Gate
Source
Drain
Buried Oxide
tSi
Drain
Source
tSi
Gate
Substrate
tSi < (1/4) × Lg
tSi < (2/3) ×Lg
7
Thin‐BOX Benefit
Adapted from X. Sun et al., IEEE Electron Device Letters Vol. 29, pp. 491‐493, May 2008.
• Thinner BOX Æ reduced drain‐induced barrier lowering
Æ relaxed tSi requirement
2.0 Curves for constant DIBL=100mV/V
LG=28nm, EOT=1.1nm, VDD=1V
ground-plane tri-gate SOI
tri-gate SOI
H
tSiSi //LLeffeff
1.5
J.G. Fossum et al., 2004 IEDM
WSi
1.0
Gate
Drain
Source
Buried Oxide
Substrate
0.5
tSi
TBOX = 10nm
TBOX = ∞
0.0
0.5
1.0
1.5
WSi /Leff
2.0
8
Threshold Voltage Adjustment
• VTH can be adjusted via substrate doping, for reduced σVTH:
TBOX = 10nm
T. Ohtou et al., IEEE‐EDL 28, p. 740, 2007
• VTH can be dynamically adjusted via back‐biasing.
– Reverse back biasing (to increase VTH) is beneficial for lowering SCE.
S. Mukhopadhyay et al., IEEE‐EDL 27, p. 284, 2006
9
Outline
• Introduction
• Thin‐BOX FD‐SOI Technology
– Device design
– Variation analysis
• 6‐T SRAM Cell Performance
• Yield‐Aware SRAM Cell Design
• Summary
Thin‐BOX FD‐SOI MOSFET Design
Adapted from K. Cheng et al., 2009 Symp. VLSI Technology
• Thin body (tSi < Lg/4) to suppress short‐channel effects
• Raised‐source/drain regions to reduce series resistance
(formed by low‐temperature selective epitaxial growth with in‐situ doping)
• ΦM set to meet LOP off‐state leakage (IOFF) specification
• Electrical channel length (Leff) selected for maximum ION
Schematic cross‐sectional view
Design parameters
10 20cm -3
W SPACER
= 15nm
Faceted
Raised
in-situ-doped
Raised-source
-Source
WS/Dn+ T S/D
T BOX
SiO 2
-10 20cm -3
LLGATE
GATE
Faceted
Raised
in-situ-doped
Raised-drain
-Drain
T Si n+
Sub (p -doped 10 18 cm-3)
WS/D = 72nm; TS/D = 22.6nm
NMOS
PMOS
Lg (nm)
25
25
Tox (nm)
1
1
tSi (nm)
6
6
TBOX (nm)
10
10
ФM (eV)
4.45
4.85
Leff (nm)
35.6
30.7
11
Performance Comparison
1m
ION= 581 μA/μm
@ VDD=1.0V
IDS (A/um)
1E-5
VTH,LIN= 0.366 V
1E-7
1E-8
600
SS= 81 mV/dec
1E-6
1E-4
800
400
VTH,SAT= 0.322 V
IDS (A/um)
1E-4
200
IOFF= 3 nA/μm
1E-9
0.0
0.2
0.4
VGS (V)
0.8
Optimized to maximize ION for IOFF=3nA/um,
Nbody=1018 cm-3
ION= 861 μA/μm
@ VDD=1.0V
800
600
SS= 75 mV/dec
1E-6
VTH,LIN= 0.347 V
1E-7
1E-9
0.0
1.0
Model
Sentaurus
1E-5
1E-8
BULK
0.6
1m
1E-3
IDS (uA/um)
Model
Sentaurus
400
VTH,SAT= 0.298 V
200
FD‐SOI
IOFF= 3 nA/μm
0.2
0.4
IDS (uA/um)
1E-3
0.6
VGS (V)
0.8
1.0
Analytical model fit to simulated I‐V, used to iteratively solve for DC SRAM metrics:
V
ID S = μ s C ox
= μ l C ox
DS
W (VG S ‐ VT H ) 2
VT H
in saturation region
(1 + λVD S ) + Isub (1 ‐ e )
2m L 1 + VG S ‐ VT H
E sat L
m VD S 2
VD S (VG S ‐ VT H ‐
)
VDS
V0
W
VT H
(1 + λVD S ) + Isub (1 ‐ e )
in linear region
VG S ‐ V TH
L
1+
E sat L
= I sub (1 ‐ e
VD S
VTH
)e
VG S ‐ VTH
S
in sub‐threshold region
12
Impact of Random Variations
• Gate‐LER‐induced variations were simulated by sampling profiles
from an SEM image of a photoresist line.
– 100 different gate line profiles, LER (3σ) = 3.98nm, correlation length = 21.8nm
• RDF‐induced variations were simulated using KMC model.
• ΦΜ variations were estimated based on Dadgour et al., 2008
IEDM.
Bulk MOSFET: σ(VTH) = 50mV
FD‐SOI MOSFET: σ(VTH) = 26mV
Nominal case
Nominal case
σ(VTH)|RDF+LER = 49.6mV
σ(VTH)|RDF+LER = 22.4mV
W = 55nm
13
Outline
• Introduction
• Thin‐BOX FD‐SOI Technology
• 6‐T SRAM Cell Performance
– Nominal cell design
– SRAM performance
• Yield‐Aware SRAM Cell Design
• Summary
6‐T SRAM Cell Layout
Half‐Bit Cell Layout
PD
X
Layout Parameters
Symbol
Size
[nm]
PG CH length
LPG
25
PD CH length
LPD
25
CONT size
X
30
Gate-to-CONT
Y
20
Design rules
PU
A/2
Y
LPD WPU
B WPD
C
Cell
Height
Total
D/2
WPG
LPG
PG
• Based on published
22nm CMOS design rules
Cell
Width
190
POLY-to-POLY
A
30
POLY-to-DIF ext
B
20
PD Width
WPD
55
N/P isolation
C
50
PU width
WPU
32
DIF-DIF (min)
D
50
PG width
WPG
40
Total
SRAM cell area
394
0.07486 μm2
15
Nominal Read and Write Margins
• RSNM of the FD‐SOI cell is lower due to lower nominal |VTH|,
but Iw is ~70% higher and Iread is ~60% higher.
ÆThe FD‐SOI cell design offers a better design trade‐off.
Butterfly curves
Write‐N‐curves
60
1.0
FD-SOI
BULK
0.8
In1 (uA)
Vn2 (V)
SNM
0.6
0.4
0.2
40
Iw,SOI=18.9uA
30
Iw,BULK=11.0uA
20
SNMSOI=186mV
10
SNMBULK=207mV
0.0
FD-SOI
BULK
50
0.0
0.2
0.4
0.6
Vn1 (V)
0.8
1.0
IW
0
0.0
0.2
0.4
0.6
0.8
1.0
Vn1 (V)
16
Impact of WPG
• For fixed cell area, WPG can be adjusted in order to optimize
the trade‐off between SNM, Iw, and Iread .
• The FD‐SOI cell can achieve comparable SNM as the bulk cell
if WPG is decreased to 27.2 nm.
– Iw is still 15% higher than that for the bulk cell.
– Iread is still 34% higher than that for the bulk cell.
FD-SOI
BULK
30
225
IW (uA)
SNM (mV)
250
200
175
Nominal
Design
150
FD-SOI
BULK
35
25
15
∆IIw
10
1.0
1.5
2.0
2.5
Cell Ratio
decreasing WPG
3.0
3.5
4.0
0
0.0
Nominal
Design
15
∆II read
10
5
5
125
FD-SOI
BULK
20
Nominal
Design
20
25
Iread (uA)
275
100
30
40
300
0.5
1.0
1.5
Pull-up Ratio
decreasing WPG
2.0
2.5
0
10 15 20 25 30 35 40 45 50 55 60
WPG (nm)
17
Impact of VDD Scaling
• The FD‐SOI benefit of improved write‐ability and speed
for comparable read stability is retained as VDD is reduced.
Iw
SNM
20
240
FD-SOI
BULK
220
30
FD-SOI
BULK
15
200
140
Iread (uA)
160
10
5
120
15
10
5
100
80
FD-SOI
BULK
25
20
180
IW (uA)
SNM (mV)
Iread
0.5
0.6
0.7
0.8
VDD (V)
0.9
1.0
0
0.5
0.6
0.7
0.8
VDD (V)
0.9
1.0
0
0.5
0.6
0.7
0.8
VDD (V)
0.9
1.0
18
Outline
• Introduction
• Thin‐BOX FD‐SOI Technology
• 6‐T SRAM Cell Performance
• Yield‐Aware SRAM Cell Design
– Iso‐area comparison
– Iso‐yield comparison
– Minimum operating voltage
• Summary
SRAM Yield Modeling Approach
• Consider the transistor parameter variation space:
– Each transistor dimension is assumed to be an independent
parameter with Gaussian distribution (±10% at 3σ)
ÆVTH variation due to variations in Lg, W, TOX, TSi and LER, RDF, WFV
• Too much variation can result in DC read or write failure.
• Cell Sigma is defined to be
the minimum amount of
variation that causes a DC
read or write failure.
– 18 dimensions of variation
(W, L, VTH for 6 transistors)
Failing
Cells
Passing
Cells
Variation in PG1 VT (σ)
Variation in PD1 VT (σ)
2‐D Variation Space Example
20
Iso‐Area Comparison
• Optimal cell designs:
– WPG = 35 nm for the bulk cell
– WPG = 40 nm for the FD‐SOI cell
FD-SOI
BULK
Yield Iw (sigma)
11
10
9
8
7
6
5
4
3
2
1
0
WPG=40nm
• The FD‐SOI cell can satisfy
the 6σ yield requirement.
+ 2.15
WPG=35nm
+ 1.20
VDD=0.9V
0
1
2
3
4
5
6
7
8
Yield SNM (sigma)
9 10 11
• The bulk cell cannot satisfy
the 6σ yield requirement.
– ~1.2σ worse SNM yield and
~2.2σ worse Iw yield than the
FD‐SOI cell
21
Iso‐Yield Comparison
VDD=0.9V
Yield Iw (sigma)
11
10
9
8
7
6
5
4
3
2
1
0
• In order for the bulk cell to
achieve >6σ yield, it must be
upsized so that WPD = 95 nm
and WPU = 50 nm.
Æ cell area is increased by 30%
(from ~0.07 μm2 to ~0.1 μm2)
iso-area BULK
iso-yield BULK
FD-SOI
0
1
2
3
4
5
6
7
8
Yield SNM (sigma)
9 10 11
22
Minimum Operating Voltage
• The FD‐SOI cell achieves lower Vmin because it provides for
higher transistor drive current and reduced variability.
– Vmin ~ 0.6V for the FD‐SOI cell.
– Vmin ~ 0.8V for the bulk cell.
Yield Iw (sigma)
11
10
9
8
7
6
5
4
3
2
1
0
Enlared BULK ( VDD=0.9V)
Enlared BULK ( VDD=0.8V)
Enlared ( VDD=0.7V)
0
1
2
3
4
5
6
11
10
9
8
7
6
5
4
3
2
1
0
FD‐SOI Cell
Yield Iw (sigma)
Bulk Cell
7
8
Yield SNM (sigma)
9 10 11
FD-SOI ( VDD=0.9V)
FD-SOI ( VDD=0.8V)
FD-SOI ( VDD=0.7V)
FD-SOI ( VDD=0.6V)
0
1
2
3
4
5
6
7
8
Yield SNM (sigma)
9 10 11
23
Outline
• Introduction
• Thin‐BOX FD‐SOI Technology
• 6‐T SRAM Cell Performance
• Yield‐Aware SRAM Cell Design
• Summary
Summary
• Thin‐BOX FD‐SOI and bulk CMOSFET designs were optimized
via 3‐D process and device simulations, for LOP 22nm CMOS.
– FD‐SOI achieves higher drive current and reduced VTH variation.
• For fixed cell area, FD‐SOI technology provides for improved
SNM yield (by 1.49σ) and Iw yield (by 2.51σ).
• For fixed yield, FD‐SOI provides an area savings of 30%.
– Vmin for 6σ yield is ~0.6V for the FD‐SOI cell vs. ~0.8V for the bulk cell.
Æ Thin‐BOX FD‐SOI is promising for continued planar 6‐T
SRAM cell area and voltage scaling!
25
Acknowledgements
• SOITEC
• DARPA/SRC Focus Center Research Program
– Center for Circuits and Systems Solutions
• Korea Foundation for Advanced Studies
• Samsung Electronics
26