BANDWIDTH C ONSIDERATIONS OF H IGH
E FFICIENCY M ICROWAVE P OWER A MPLIFIERS
Vorgelegt von
M.Sc. Ahmed Altanany
aus. Palästina
Von der Fakultät IV - Elektrotechnik und Informatik
der Technischen Universität Berlin
zur Erlangung des akademischen Grades
Doktor der Ingenieurwissenschaften (Dr.-Ing.)
Genehmigte Dissertation
Promotionsausschuss:
Vorsitzender:
Berichtender:
Berichtender:
: Prof. Dr.-Ing. Sibylle Dieckerhoff
: Prof. Dr.-Ing. Georg Böck
: Prof. Dr.-Ing. Reinhard Knöchel
- Technische Universität Berlin
- Technische Universität Berlin
- Christian-Albrechts-Universität zu Kiel
Tag der wissenschaftlichen Aussprache:
10. Dezember 2014
Berlin 2015
ii
To my parents
who have given me the opportunity of an education from the best institutions and support
throughout my life.
To my lovely wife and daughters
who have always stood by me and dealt with all of my absence from many family occasions with
a smile.
iv
Acknowledgement
First and foremost, it is with immense gratitude that I acknowledge the support and help of
my supervisor Prof. Dr.-Ing. Georg Böck. I would like to thank him for encouraging my research
and for allowing me to grow as a research scientist in his eminent group. His advice on both
research as well as on my career have been invaluable. I could never have imagined a better
advisor for my Ph.D study.
I would also like to thank Prof. Dr.-Ing. Reinhard Knöchel who accepted to be a second
examiner for this Ph.D. thesis as well as Prof. Dr.-Ing. Sibylle Dieckerhoff being the chairman of
the dissertation committee.
It gives me great pleasure in acknowledging the support and help of Dr. Chafik Meliani and
Dr. Olof Bengtsson from the Leibniz Institut für innovative Mikroelektronik (IHP) and Leibniz
Ferdinand Braun institute (FBH) for their valuable discussions and help. Without their guidance
and persistence help this dissertation would not have been perfected.
I owe my deepest gratitude to the Federal ministry of economics and technology in Germany
for funding this project. Without their fund this work would never been in completed.
I am indebted to my many colleagues in TU-Berlin who supported me during all the last
years. The technical discussions we had have inspired the flow of this work to reach its current
status. The perfect atmosphere in and the social activities gave me the energy to put my ideas to
the world’s demands. My deep thanks
My completion of this work could not have been accomplished without the support of my
friends overseas and specially my cousin Mohammed El-Tanani.
I can not find words to express my gratitude to my family and parents. Their continuous
encouragement and motivation have given me a perfect launch to achieve successful results. Their
wishes lighten my path towards my goal.
Finally, my deepest gratitude to my wife and daughters for their patient during my study and
for giving me a push to start writing.
Thank you all
Ahmed Altanany
5th June 2015
vi
Abstract
The dissipated power of mobile base stations is mainly consumed by the power amplifiers (PAs)
and their cooling devices. On-going research and developments in the wireless field leads to
new communication standards and operating frequencies. As a result, the bandwidth becomes an
important figure in modern wireless base stations. Moreover, the new standards have high peak
to average power ratios (PAPR), which require high efficiency at saturation and at back-off power
levels as well. Hence, high average efficiency, linearity and bandwidth are the key parameters
for the current developments and the optimum trade-off between these parameters is in the focal
point of current developments. Switch-mode power amplifiers are strong candidates for highly
efficient PAs because of their theoretical drain efficiency of 100 % at saturation.
Investigations on highly efficient power amplifier techniques such as switch mode and harmonically tuned PAs have been the subject of research for many years. However, there have been
only a small number of researches that have extended the amplifier bandwidth while keeping
high the efficiency. Extending the bandwidth of highly efficient power amplifiers is the scope of
this work. Several techniques are presented and limiting factors on the achievable efficiency and
bandwidth are analysed. It is shown, that the output capacitor of the transistor is the main limiting
factor on efficiency and gain. The GaN HEMT is a promising device technology for the SMPA.
This is due to its high breakdown voltage, high power density, high cut-off frequency and low
thermal resistance. However, designing high frequency and high output power switch-mode PAs
for maximum efficiency remains a challenge. The reason is that the output capacitance increases
with the transistor size. Hence, the influence on efficiency enhancement by proper impedance
matching at harmonic frequencies drops. Nevertheless, with respect to that issue GaN HEMTS
are advantageous over Si-LDMOS.
This work presents four different broadband power amplifiers using GaN HEMTs working at
different output power levels and different frequency bands from VHF- over UHF- to L- and Sband. The amplifiers were designed, built up and the simulations were verified by measurements.
Techniques for bandwidth extension while keeping up output power level and efficiency are
investigated and discussed. These amplifiers achieve outstanding results approaching 88 % of
maximum drain efficiency for the PA in UHF band and 85 % of peak drain efficiency for the
PA in L-Band. The output powers of the low frequency amplifiers were 50 W and for the high
frequency amplifiers 10 W.
viii
Kurzfassung
Die Verlustleistung mobiler Basisstationen wird hauptsächlich durch den Leistungsverstärker
und seine Kühleinrichtungen generiert. Die kontinuierlich fortschreitende Innovation auf dem
Gebiet der drahtlosen Kommunikationstechnik führt zu immer neuen Betriebsfrequenzen und
Standards, die u.a. auch durch zunehmende CREST-Faktoren gekennzeichnet sind. Dies erfordert
Leistungsverstärker mit hoher Effizienz und Bandbreite, nicht nur bei maximaler Ausgangsleistung, sondern auch bei reduzierten Leistungspegeln (Back-Off Betrieb). Dem bestmöglichen
Kompromiss zwischen Linearität und Effizienz bei gleichzeitig hoher Bandbreite, kommt daher
bei modernen Leistungsverstärkern eine herausragende Bedeutung zu. Sogenannte Schaltverstärker sind besonders geeignete Kandidaten zur Bewältigung dieser Herausforderungen, da ihr
theoretischer Wirkungsgrad bei maximaler Ausgangsleistung gegen 100 % geht.
Mikrowellen-Schaltverstärker stehen seit Jahren im Zentrum der Forschung. Allerdings
gibt es bislang nur wenige Arbeiten, die einem hohen Wirkungsgrad bei gleichzeitig hoher
Bandbreite erreichen. Die simultane Optimierung dieser beiden Performanz-Parameter ist die
Zielrichtung dieser Arbeit. Limitierende Faktoren hinsichtlich Effizienz und Bandbreite werden
analysiert. Einen in dieser Hinsicht besonders nachteiligen Einfluss übt die Ausgangskapazität
des Transistors aus. Der GaN-HEMT Technologie ist wegen ihrer hohen Durchbruchspannung
und Leistungsdichte und wegen ihres geringen Wärmewiderstandes eine vielversprechende Technologie für die Realisierung von hocheffizienten Mikrowellen-Leistungsverstärkern. Ihr Entwurf
für hohe Frequenzen, Ausgangsleistungen und Bandbreiten bei gleichzeitig hoher Effizienz
bleibt dennoch eine Herausforderung. Der hauptsächliche Grund dafür ist die mit zunehmender
Transistorgröße und Frequenz ansteigende Ausgangskapazität, die wegen zunehmendem Kurzschluss der harmonischen Frequenzanteile eine Optimierung der Kurvenform von Strom und
Spannung im intrinsischen Transistor weitgehend verhindert. Diese Gegebenheit führt zu einer
stetigen Abnahme des Wirkungsgrades mit zunehmender Betriebsfrequenz. Wegen der höheren
Kapazitäten von Si-LDMOS Transistoren gegenüber GaN HEMTs, besitzen Letztere mit zunehmender Frequenz grundsätzlich Vorteile. Aufgrund dessen wird hier ausschließlich auf die
GaN-HEMT Technologie zurückgegriffen.
Diese Arbeit beschäftigt sich mit dem Entwurf von vier Breitband-Leistungsverstärkern für
das VHF-, UHF-, L und S-Band. Die entworfenen Verstärker wurden realisiert und charakterisiert.
Die Verstärker zeigen mit nahezu 88 % maximaler Drain-Effizienz im UHF-Band und 85 %
im L-Band ein hervorragendes Verhalten. Die Ausgangsleistung der beiden niederfrequenten
Verstärker betrug 50 W, die der hochfrequenten 10 W.
x
Contents
List of Figures
xv
List of Tables
xxiii
Acronyms
xxv
Symbols and Units
1
2
xxvii
Introduction
1
1.1
Wireless Communication Networks . . . . . . . . . . . . . . . . . . . . . . .
1
1.2
Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2.1
Broadband Power Amplifier . . . . . . . . . . . . . . . . . . . . . . .
2
1.2.2
Efficient Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . .
2
1.2.3
RF Power Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
1.2.3.1
GaN HEMT Technology . . . . . . . . . . . . . . . . . . .
5
1.2.3.2
GaN HEMT modelling . . . . . . . . . . . . . . . . . . . .
6
1.3
State of the Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9
1.4
Thesis Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10
Power Amplifier Characteristics
13
2.1
Power Amplifier Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.1.1
Basic Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13
2.1.2
Gain Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
2.1.3
Efficiency Definitions . . . . . . . . . . . . . . . . . . . . . . . . . .
15
Linearity and Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
2.2.1
Single Tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
2.2.1.1
AM-AM/AM-PM . . . . . . . . . . . . . . . . . . . . . . .
17
2.2.1.2
Total harmonic distortion . . . . . . . . . . . . . . . . . . .
18
Multi Tone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
2.2
2.2.2
xii
CONTENTS
2.2.2.1
Intermodulation distortion . . . . . . . . . . . . . . . . . . .
19
2.2.2.2
Intercept point . . . . . . . . . . . . . . . . . . . . . . . . .
20
Dynamic Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
21
2.3
Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.4
Stability problem with PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22
2.4.1
23
2.2.3
3
Power Amplifier Operation
25
3.1
Load line and PA matching . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
3.1.1
Source/Load Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
Power Amplifier Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
3.2.1
Classical classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.2.2
High efficiency classes . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.2.2.1
Switched-mode Classes . . . . . . . . . . . . . . . . . . . .
32
3.2.2.2
Harmonically tuned PA . . . . . . . . . . . . . . . . . . . .
37
Efficiency and power limitations in power amplifiers . . . . . . . . . . . . . .
41
3.3.1
The knee Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.3.2
Parasitic effects on gain and power
. . . . . . . . . . . . . . . . . . .
43
3.3.2.1
Cgs influence on power, gain and efficiency . . . . . . . . . .
46
3.3.2.2
Cds influence on power, gain and efficiency . . . . . . . . . .
47
3.3.2.3
Cgd influence on power, gain and efficiency . . . . . . . . . .
49
3.3.2.4
Cds and Cgd influence on the efficiency . . . . . . . . . . . .
50
3.2
3.3
4
Single Band Power Amplifiers
51
4.1
Inverse Class-D PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.1.1
Design of CMCD PA . . . . . . . . . . . . . . . . . . . . . . . . . . .
51
4.1.2
Results of the Designed CMCD PA . . . . . . . . . . . . . . . . . . .
54
4.1.2.1
Small Signal Measurements . . . . . . . . . . . . . . . . . .
54
4.1.2.2
Large Signal Measurements . . . . . . . . . . . . . . . . . .
55
Inverse Class-F PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
4.2.1
Design of Inverse Class-F PA . . . . . . . . . . . . . . . . . . . . . .
57
4.2.2
Large Signal Performance . . . . . . . . . . . . . . . . . . . . . . . .
58
Power Amplifier Classes for Broadband Operation . . . . . . . . . . . . . . .
59
4.2
4.3
5
Oscillation suppression techniques . . . . . . . . . . . . . . . . . . . .
VHF and UHF Broadband PA
61
5.1
Gain-Bandwidth Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
61
5.1.1
The Real Frequency Technique . . . . . . . . . . . . . . . . . . . . . .
65
5.1.2
Implemented Matching Technique and Design Steps . . . . . . . . . .
66
VHF Broadband Class-E PA . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
5.2
xiii
CONTENTS
5.2.1
Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . .
69
5.2.1.1
DC-Feed Design . . . . . . . . . . . . . . . . . . . . . . . .
73
5.2.1.2
Input Matching Network . . . . . . . . . . . . . . . . . . .
74
5.2.1.3
Stability Circuit . . . . . . . . . . . . . . . . . . . . . . . .
75
5.2.1.4
Realization . . . . . . . . . . . . . . . . . . . . . . . . . . .
75
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
5.2.2.1
Small Signal Measurements . . . . . . . . . . . . . . . . . .
76
5.2.2.2
Large Signal Performance and Linearity . . . . . . . . . . .
77
5.2.2.3
Harmonic Suppression Measurements . . . . . . . . . . . .
78
5.2.2.4
Two-Tone Measurements . . . . . . . . . . . . . . . . . . .
78
5.2.2.5
Influence of Vdd on Efficiency and Output Power . . . . . . .
79
5.2.2.6
PA Reliability . . . . . . . . . . . . . . . . . . . . . . . . .
80
UHF Broadband Class-E PA . . . . . . . . . . . . . . . . . . . . . . . . . . .
84
5.3.1
Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . .
85
5.3.2
Realization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
5.3.3
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
5.3.3.1
Large Signal Performance . . . . . . . . . . . . . . . . . . .
89
Broadband SMPA Behaviour Over the Frequency . . . . . . . . . . . . . . . .
90
5.4.1
DE-Embedding Method . . . . . . . . . . . . . . . . . . . . . . . . .
91
5.4.2
Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
5.2.2
5.3
5.4
6
L and S Band Broadband PA
97
6.1
10 W-Harmonically Tuned PA . . . . . . . . . . . . . . . . . . . . . . . . . .
97
6.1.1
Load/Source-Pull Simulation . . . . . . . . . . . . . . . . . . . . . . .
97
6.1.1.1
The Effect of the Load Impedances . . . . . . . . . . . . . .
99
6.1.1.2
Safe-Zone Impedance Margin . . . . . . . . . . . . . . . . . 102
6.1.2
Matching Network Design and Synthesis . . . . . . . . . . . . . . . . 103
6.1.2.1
6.1.3
6.2
DC-feed Design . . . . . . . . . . . . . . . . . . . . . . . . 104
Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.1.3.1
Single Tone Measurements . . . . . . . . . . . . . . . . . . 105
6.1.3.2
Linearity for UMTS Application. . . . . . . . . . . . . . . . 107
100 W L-Band Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.2.1
Power Handling Capabilities of Passive Components . . . . . . . . . . 109
6.2.1.1
Microstrip Lines PHC . . . . . . . . . . . . . . . . . . . . . 109
6.2.2
Load-Pull Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.2.3
Matching Network Design . . . . . . . . . . . . . . . . . . . . . . . . 112
6.2.4
Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.2.4.1
Optimum Bias Points . . . . . . . . . . . . . . . . . . . . . 113
xiv
CONTENTS
6.2.4.2
6.2.4.3
6.2.4.4
7
Small Signal Behaviour . . . . . . . . . . . . . . . . . . . . 114
Large Signal Behaviour . . . . . . . . . . . . . . . . . . . . 115
Linearity Measurement . . . . . . . . . . . . . . . . . . . . 116
Conclusion
119
7.1 Thesis Outcome . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
References
123
List of Publications
127
List of Figures
1.1
Spectrum allocation for the most common wireless standards. . . . . . . . . . .
2
1.2
Base-station model showing the consumed power in different blocks. . . . . . .
3
1.3
a) Cross section view of the GaN HEMT transistor, and b) band-gap structure of
the HEMT transistor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
1.4
Typical large signal GaN HEMT model. . . . . . . . . . . . . . . . . . . . . .
7
2.1
Energy conservation in power amplifier operation. . . . . . . . . . . . . . . . .
13
2.2
Two-port network with power definitions. . . . . . . . . . . . . . . . . . . . .
14
2.3
Typical performance for a power amplifier versus input power. . . . . . . . . .
16
2.4
Different types of linearity measurements. . . . . . . . . . . . . . . . . . . . .
16
2.5
Voltage gain compression as in (2.13). . . . . . . . . . . . . . . . . . . . . . .
17
2.6
Single tone output power for the fundamental, second harmonic and third harmonic. 18
2.7
Typical AM-AM/AM-PM curves for power amplifiers. . . . . . . . . . . . . .
18
2.8
Output frequency component of an amplifier excited by a two tone signal. . . .
20
2.9
Third order intercept point example. . . . . . . . . . . . . . . . . . . . . . . .
21
2.10 Typical spectrum for a UMTS signal for PA. . . . . . . . . . . . . . . . . . . .
21
2.11 Different stabilization techniques are used in this work. . . . . . . . . . . . . .
23
3.1
Simple FET model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
25
3.2
Characteristic I-V curve for ideal FET operation. . . . . . . . . . . . . . . . .
26
3.3
Class-A power amplifier waveforms . . . . . . . . . . . . . . . . . . . . . . .
26
3.4
Typical load pull simulation showing output power (filled circle), PAE (cross
symbol) and IMD3 (solid) for, a) fundamental load impedance, and b) second
harmonic load impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
3.5
Classification of power amplifier . . . . . . . . . . . . . . . . . . . . . . . . .
28
3.6
Classical PA classes waveforms, bias points, load lines and drive signals. . . . .
29
3.7
Typical schematic for classical classes. . . . . . . . . . . . . . . . . . . . . . .
29
3.8
Drain current for general conduction angle. . . . . . . . . . . . . . . . . . . .
30
xvi
LIST OF FIGURES
3.9
Drain current DC and harmonic component for the DC, fundamental and the
harmonics up to the fifth components. . . . . . . . . . . . . . . . . . . . . . .
30
3.10 Drain efficiency η and output power Pout for general conduction angle. . . . . .
31
3.11 Typical circuit of class-E PA. . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.12 Drain current isw (t), Drain Voltage vsw (t) and output capacitance current iCds (t)
of Class-E power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
33
3.13 Typical voltage mode Class-D power amplifier circuit. . . . . . . . . . . . . .
35
3.14 Ideal current and voltage waveforms for Class-D family power amplifiers. . . .
35
3.15 Schematic diagram for Current mode Class-D power amplifier. . . . . . . . . .
37
3.16 Typical circuit diagram for A Class F-Power amplifier. . . . . . . . . . . . . .
37
3.17 Typical circuit diagram for an inverse Class-F-Power amplifier. . . . . . . . . .
38
3.18 Ideal current and voltage waveforms for inverse Class-F powers amplifier, for up
to two/three controlled harmonics for even/odd components (dotted) and for up
to four/five controlled harmonics for even/odd components (solid). . . . . . . .
38
3.19 Efficiency and output power capability for maximum flat Class-F power amplifier
with different odd and even components combination . . . . . . . . . . . . . .
39
3.20 Output power and efficiency of different combinations of harmonically tuned
power amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
3.21 Typical I-V curve with knee effect . . . . . . . . . . . . . . . . . . . . . . . .
42
3.22 Circuit model for FET with major parasitic capacitances . . . . . . . . . . . .
43
3.23 Calculated gain from (3.75) over the frequency with a) Cgs of a range between
2 pF and 10 pF in 0.2 pF steps, b) Cgd of a range between 0.1 pF and 1.3 pF
in 0.3 pF steps, and c) a) Cds of a range between 1 pF and 10 pF in 2 pF steps;
gm = 0.525 S, RL = 1 Ω and LL = 2.696 nH. . . . . . . . . . . . . . . . . . . .
45
3.24 fmax for different parasitic values obtained from each diagram in Fig. 3.23
crossing the unity power gain (zero in dB). For each graph in the diagram, the
other capacitance values are kept similar to Fig. 3.23. . . . . . . . . . . . . . .
46
3.25 Calculated efficiency factor from (3.102) over the frequency with a) Cgd of a
range between 0.1 pF and 1.3 pF in 0.3 pF steps, and b) Cds of a range between
1 pF and 10 pF in 2 pF steps; gm = 0.525 S, RL = 1 Ω and LL = 2.696 nH. . . .
50
4.1
Designed Resonant Circuit utilizing the DC-feed as parallel inductor. . . . . . .
52
4.2
a) Ideal Parallel LC resonant circuit presented to ideal CMCD PA, and b) Impedance resulted from the designed resonator (red) and from the ideal parallel LC
circuit (blue). The small circles represent the the operating frequency (2.14 GHz) 52
4.3
Designed single stub output matching network for CMCD PA. . . . . . . . . .
53
4.4
Photo of the fabricated CMCD power amplifier using 30 W GaN HEMT from
Eudyna. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
53
LIST OF FIGURES
4.5
4.6
xvii
Simulation results of time domain voltage and current waveforms for the designed
CMCD PA taken without de-embedding output die parasitics. . . . . . . . . . .
54
Simulation (solid) and Measured (symbol) for the a) insertion loss and b) small
signal gain of the designed PA . . . . . . . . . . . . . . . . . . . . . . . . . .
54
4.7
Large signal measurement setup used in to measure the designed PA in this thesis. 55
4.8
Simulation (solid) and Measured (symbol) for the a) output power and power gain,
and b) efficiency (drain and PAE) of the designed PA at the designed frequency,
i.e.; 2.14 GHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
Efficiency performance versus output power showing more than 50 % PAE at
3 dB OPBO at the designed frequency, i.e.; 2.14 GHz. . . . . . . . . . . . . . .
56
4.10 Typical voltage mode Class-D power amplifier circuit. . . . . . . . . . . . . .
57
4.11 Load impedance of the output matching network integrated with resonator for
the designed Class-F−1 power amplifier shown in Fig. 4.10. . . . . . . . . . . .
57
4.12 Measured (symbol) result for the output power, power gain and efficiency versus
a) frequency and b) input power for the designed Class-F−1 PA. . . . . . . . .
58
4.13 output power, power gain and efficiency over the drain supply voltage for designed
Class-F−1 PA at 2.35 GHz operating frequency. . . . . . . . . . . . . . . . . .
59
4.14 Fundamental and harmonic spectral density for an arbitrary signal with a certain
bandwidth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
59
Circuit diagrams of broadband matching problems for a) resistive matching,
b)single matching, c) double matching. . . . . . . . . . . . . . . . . . . . . . .
62
Different load problem for Bode-Fano limit with passive lossless matching network (MN) and a) resistive load and shunt capacitor, b) resistive load and shunt
capacitor series inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
5.3
Bode-Fano limit criterion for a constant reflection coefficient. . . . . . . . . . .
63
5.4
Fractional bandwidth limit according to Bode-Fano limit with different reflection
coefficient and different quality factor assuming constant Γm . . . . . . . . . . .
63
Reflection coefficient definition for resistive load network with shunt capacitor
and series inductor including a passive lossless matching network. . . . . . . .
64
Evaluation of Bode-Fano limit for the circuit in Fig. 5.5 with XC as a parameter
and XL = 2 showing a) reflection coefficient and b) return loss from the reflection
coefficient; the dashed line shows the case where the inductor is not present. .
65
Evaluation of Bode-Fano limit for the circuit in Fig. 5.5 with XL as a parameter
and XC = 2 showing a) reflection coefficient and b) return loss from the reflection
coefficient; the dashed line shows the case where the inductor is not present. . .
65
4.9
5.1
5.2
5.5
5.6
5.7
xviii
5.8
LIST OF FIGURES
Different matching component behaviour in a matching network, the black dot is
the default load impedance and the arrow present the increasing value/length of
the component and transmission line TL. . . . . . . . . . . . . . . . . . . . . .
66
Design algorithm for the matching network to design a broadband highly efficient
PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
5.10 Load-pull contours for the output power (red) with step 0.5 dB, drain efficiency
(green) with 2 % step and DC current (blue) with 0.6 mA step for a) 225 MHz, b)
312 MHz and c) 400 MHz. the black dot is the realised load impedance. . . . .
70
5.11 Ideal optimum a) source impedances and b) load impedances over the entire band
according to the load/source-pull simulation. . . . . . . . . . . . . . . . . . . .
71
5.12 Ideal performance for the transistor with ideal load/source-pull impedances; output power (red), gain (blue), drain efficiency (green) and power added efficiency
(black). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
71
5.13 Proposed circuit diagram topology consists of output matching network (OMN)
and band-pass filter (BPF). . . . . . . . . . . . . . . . . . . . . . . . . . . . .
72
5.14 Load matching network synthesize showing a) circuit impedance network and b)
Load impedances for each element in the matching network. . . . . . . . . . .
72
5.15 Butterworth bandpass filter used in the matching network of the designed PA. .
73
5.9
5.16 Matching network design to include the first series capacitor of the band-pass filter. 74
5.17 Drain and gate DC-feed network used in the PA design including the bypass
capacitors, the dots here represent a multi section of the same DC-feed network.
74
5.18 The designed PA circuit with the stability circuits. . . . . . . . . . . . . . . . .
75
5.19 Simulation without stability network (solid) and with stability network (dashed)
for a) K-factor and b) maximum gain. . . . . . . . . . . . . . . . . . . . . . .
76
5.20 Photo of the fabricated VHF broad-band Class-E power amplifier using 45 W
GaN HEMT from Eudyna. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
77
5.21 Simulated (solid) and measured (symbol) of the measured small signal gain using
-20 dBm, the dots showing the second harmonic small signal gain. . . . . . . .
77
5.22 Simulated (solid) and measured (symbol) for a) output power (red) and Gain
(blue), and b) drain efficiency (green) and power added efficiency (black), versus
input power with Idq = 115 mA, Vgg = −1.35 V, Vdd = 50 V. . . . . . . . . . .
78
5.23 Simulated (solid) and measured (symbol) for output power (red) and Gain (blue),
drain efficiency (green) and power added efficiency (black), versus input power
with Idq = 115 mA, Vgg = −1.35 V, Vdd = 50 V. . . . . . . . . . . . . . . . . .
79
5.24 Measured fundamental output power (red), second harmonic power (blue) and
third harmonic (green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
79
5.25 Linearity measurement for the amplifier showing a) IMD3 and b) OIP3 . . . . .
80
LIST OF FIGURES
xix
5.26 Output power (red) and drain efficiency (green) with different biasing voltage
values and input power for a) 225 MHz b) 312 MHz and c) 400 MHz. . . . . .
81
5.27 Measurement set-up for the PA reliability showing the tuner (VSWR), phase
shifter (Φ) and the de-embedded reference plane. . . . . . . . . . . . . . . . .
82
5.28 Simulated (solid) and measured (dashed) for the Output power with different
VSWR and phase values for a) 225 MHz b) 312 MHz and c) 400 MHz. . . . .
83
5.29 Simulated (solid) and measured (dashed) for the drain efficiency with different
VSWR and phase values for a) 225 MHz b) 312 MHz and c) 400 MHz. . . . .
84
5.30 De-embedded impedance contour for sweeping VSWR value and phase (star
black) imposed on the ideal output power contours (red) with 0.5 dB step, drain
efficiency contours (green) with 2 % step and DC current contours (blue) with
0.6 mA step, The black line is the designed load impedances for a) 225 MHz b)
312 MHz and c) 400 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
5.31 Ideal load/source-pull a) load impedance magnitude (blue) and phase (red), and
b) ideal performances for output power (red), gain (blue), drain efficiency (green)
and power added efficiency (black). . . . . . . . . . . . . . . . . . . . . . . .
86
5.32 a) Filter topology used in output matching network showing the capacitor dashed
box that will be replaced, and b) the filter transmission loss over the targeted
band and the harmonic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
5.33 Full output matching network including the filter used in the ideal design step. .
88
5.34 Photo of the fabricated UHF broad-band Class-E power amplifier using 30 W
GaN HEMT from Eudyna. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
89
5.35 Simulation of final stage for the current (red) and voltage (blue) waveforms. The
dashed lines shows the zero level for the current, where below the dashed line
is the time for the output capacitor Cds discharging and above the line is the
charging period of the output capacitor Cds . . . . . . . . . . . . . . . . . . . .
89
5.36 Measured small signal gain across the bandwidth with -30 dBm showing the gain
for the second harmonic of the lowest frequency. . . . . . . . . . . . . . . . .
90
5.37 Measured output power (red), gain (blue) drain efficiency (green) and PAE (black)
over the stimulated input power for the centre frequency, i.e., 800 MHz, of the
designed power with Vd = 50 V, Idq = 150 mA . . . . . . . . . . . . . . . . . .
90
5.38 Measured output power (red), gain (blue) drain efficiency (green) and PAE (black)
across the bandwidth for the maximum output power (Pin = 34 dBm) frequency,
i.e., 800 MHz, of the designed power with Vd = 50 V, Idq = 150 mA. . . . . . .
91
5.39 Circuit diagram of the PA showing the de-embedded load impedance and drain
impedance reference plane. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
92
xx
LIST OF FIGURES
5.40 Simulated current (red) and voltage (blue) waveforms for a) 600 MHz, b)
800 MHz and c) 1000 MHz. The dashed lines shows the zero level for the
current, where below the dashed line is the time for the output capacitor Cds
discharging and above the line is the charging period of the output capacitor Cds .
93
5.41 Calculated load impedances from the simulation for a) 600 MHz, b) 800 MHz
and c) 1000 MHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
94
6.1
6.2
6.3
Output power and PAE contours for 10W PA design at a) 1.7 GHZ, b) 2.2 GHz,
and, c) 2.7 GHz. The input power was 29 dBm, Vdd = 28 V and Id = 20 mA. .
98
Optimum load impedances, i.e., magnitude and phase, for the fundamental
frequency, second and third harmonic. The input power was 29 dBm, Vdd = 28 V
and Id = 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
99
Optimum output power and PAE obtained from the optimum load impedances.
The input power was 29 dBm, Vdd = 28 V and Id = 20 mA. . . . . . . . . . . .
99
6.4
Output power and PAE for three different frequencies versus (a) the magnitude of
the fundamental frequency load impedance and (b) the phase of the fundamental
frequency load impedance. The input power was 29 dBm, Vdd = 28 V and Id = 20
mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.5
Output power and PAE for three different frequencies versus (a) the magnitude of
the second harmonic load impedance and (b) the phase of the second harmonic
load impedance. The input power was 29 dBm, Vdd = 28 V and Id = 20 mA. . . 101
6.6
Output power contours with 0.3 dB step (solid green) and PAE (symbol red)
with 5 % step performances versus the second harmonic load impedances for; a)
1.7 GHz, a) 2.2 GHz, and, a) 2.7 GHz. The input power was 29 dBm, Vdd = 28 V
and Id = 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.7
PAE performance with full second harmonic reflection coefficient and different
phase values for three different frequencies. The input power was 29 dBm,
Vdd = 28 V and Id = 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.8
Method for obtaining the safe-zone of load impedances by finding the intersection
of optimum impedance for a) fundamental frequency and b) second harmonic. . 103
6.9
Safe zone region definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.10 a) Ideal single section matching network for 10 W power amplifier design, b) load
impedances for the first three harmonics at three different frequencies obtained at
each section from the matching network. . . . . . . . . . . . . . . . . . . . . . 104
6.11 Realised load impedance from two section matching network for the fundamental
and second harmonic across the targeted band imposed on the safe zone region.
105
LIST OF FIGURES
xxi
6.12 comparison between realised simulated results (symbol) and optimum simulated
results (solid) for the output power and PAE. The input power was 29 dBm,
Vdd = 28 V and Id = 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
6.13 Photo of the fabricated broad-band harmonically tuned power amplifier using
10 W GaN HEMT from Cree Inc. . . . . . . . . . . . . . . . . . . . . . . . . 106
6.14 Measured output power, power gain and PAE for the designed power amplifier
across the bandwidth for the 1 dB compression point (hollow symbol) and 3 dB
compression point (filled symbol). The input power was 30−32 dBm, Vdd = 28 V
and Id = 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
6.15 Measured power amplifier performances across the input power at the centre
frequency (2.125 GHz). Vdd = 28 V and Id = 20 mA. . . . . . . . . . . . . . . 107
6.16 ACPR and average output power and drain efficiency versus the supply drain
voltage and gate bias voltage at 35 dBm. . . . . . . . . . . . . . . . . . . . . . 108
6.17 a) Typical transistor package model and b) small signal load impedances seen
from the lead reference plane of a 100W Cree transistor. The input power was
40 dBm, Vdd = 28 V and Id = 400 mA. . . . . . . . . . . . . . . . . . . . . . . 108
6.18 Output power contours with 0.5 dB step and PAE contours with 5 % step for
100 W power amplifier at the edge frequencies. . . . . . . . . . . . . . . . . . 110
6.19 Fundamental (red) second harmonic (green) and third harmonic (blue) load impedances for a) optimum case with Smith chart centred at 50 Ω, and b) optimum
(dotted), realised from ideal lumped OMN (crossed) and realised from microstrip
OMN (solid). The input power was 40 dBm, Vdd = 28 V and Id = 400 mA. . . 111
6.20 PAE performance with full second harmonic reflection coefficient and different
phase values for two different frequencies. The input power was 40 dBm, Vdd =
28 V and Id = 400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.21 Stability factor for the designed power amplifier. The input power was 40 dBm,
Vdd = 28 V and Id = 400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . 112
6.22 Ideal lumped component matching network for the designed amplifier. The input
power was 40 dBm, Vdd = 28 V and Id = 400 mA. . . . . . . . . . . . . . . . 113
6.23 Ideal (hollow symbol) and realies from ideal lumped OMN (filled symbol) for
a) output power and b) PAE. The input power was 40 dBm, Vdd = 28 V and
Id = 400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
6.24 Simulated output power and PAE performances for different case temperature
(i.e., 25◦ C, 50◦ C and 85◦ C). The input power was 40 dBm, Vdd = 28 V and
Id = 400 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.25 Photo of the fabricated broad-band harmonically tuned power amplifier using
120 W GaN HEMT from Cree Inc. . . . . . . . . . . . . . . . . . . . . . . . . 114
xxii
LIST OF FIGURES
6.26 Measured output power and PAE performances of the designed PA for different
frequency vs.(a) gate bias voltage (b) drain supply voltage. . . . . . . . . . . . 115
6.27 Simulated (solid) and measured (symbol) Small signal gain. The input power
was −20 dBm, Vdd = 28 V and Id = 650 mA. . . . . . . . . . . . . . . . . . . 115
6.28 Simulated (solid) and measured (symbol) performances at 28 V drain supply
voltage and Id = 650 mA for CW signal at frequency of 1.95 GHz. . . . . . . . 116
6.29 performance over the frequency for different input power i.e.; 22, 27, 32, 37 and
40 dBm for (a) output power (black) and power gain (blue) , (b) drain efficiency
(green) and power added efficiency (brown). The supply voltage is Vdd = 28 V
and Id = 650 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.30 Performance over the frequency for the post-tuned power amplifier with different
output power levels i.e.; Pout_sat , Pout_3dB and Pout_1dB . The supply voltage is
Vdd = 28 V and Id = 650 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.31 Measured upper (red) and lower (black) ACLR without memory DPD (hollow
symbol) and with memory DPD (filled symbol) vs. average output power at
2.15 GHz operating frequency. The supply voltage is Vdd = 28 V and Id = 650 mA.117
List of Tables
1.1
1.2
1.3
3.1
3.2
4.1
4.2
5.1
5.2
5.3
5.4
5.5
6.1
Important parameters for the most common materials used in semiconductor
devices, adapted from [5, 6]. . . . . . . . . . . . . . . . . . . . . . . . . . . .
An important parameters for the most common substrates used in semiconductor
devices, adapted from [7]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
State of the art for broadband power amplifier with more than 50 % drain efficiency published in the last five years Based on GaN HEMT technology. . . . .
Design Parameters for Class-AB, Class-C and Class-B PAs with Class-A PA
Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Optimum voltage harmonic gain and design factor for Harmonically Tuned power
amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Results of Harmonic Impedances Obtained from the Proposed Topology in
Fig.4.10. The symbols are defined in Fig. 4.11 . . . . . . . . . . . . . . . . . .
Frequency Parameters for Class-F/F−1 and Class-E PA for minimal Broadband
condition value design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal lumped element values for the output matching network used to design
broadband VHF PA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Measured IMD3 for three different frequencies with four output power levels .
Extreme output power degradation for three different frequency points with
different VSWR values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ideal lumped elements values used in the matching network shown in Fig. 5.33.
Measured PA performances across the bandwidth with 100 MHz step. . . . . .
4
6
10
32
40
58
60
72
80
82
88
91
Optimum Load Impedances for the First Three Harmonic at Three Different
Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
xxiv
LIST OF TABLES
Acronyms
2-DEG
Two-dimensional electron gas
AC
Alternating current
ACLR
Adjacent channel leakage Ratio
ACPR
Adjacent channel power ratio
AlGaN
Aluminium gallium nitride
AlN
Aluminium nitride
CMCD
Current mode Class-D
DC
Direct current
FET
Field effect transistor
GaN
Gallium nitride
GSM
Global System for Mobile Communications, originally Groupe Spécial Mobile
HD
Harmonic distortion
HTPA
Harmonically tuned PA
IIP
Input intercept point
IMD
Intermodulation distortion
LTE
Long-Term Evolution
OIP
Output intercept point
PA
Power amplifier
xxvi
Acronyms
PAE
Power added efficiency
RF
Radio frequency
SiC
Silicon carbide
SNR
Signal-to-noise ratio
SRF
Self resonant frequency
UMTS
Universal Mobile Telecommunications System
VMCD
Voltage mode Class-D
WCDMA Wideband Code Division Multiple Access
List of Symbols and units
A
Ampere
C
Capacitor
cm
Centimetre
dB
Decibel
dBc
Decibel referenced to the carrier
dBm
Decibel referenced to the mW
eV
Electron volt
G
Gain
GHz
Gigahertz
K
Stability factor
k
kelvin
L
Inductor
mA
milliampere
MHz
Megahertz
mW
milliwatt
PAE
Power added efficiency
R
Resistor
s
Second
xxviii
Symbols and Units
t
Time
V
Voltage
W
Watt
Ebr
Break down field
Eg
Band gap
f
Frequency
f0
Fundamental frequency
gm,max
Maximum transconductance
gm
Transconductance
I
Current
I0
DC-component current
I1
Fundamental-component voltage
Id
Channel drain current
IDS
Drain-source current
ids (t)
Compound (different frequency component) drain–source current
Imax
Maximum current
P
Power
P1dB
One decibel compression power
Pavg
Average power
PDC,T L
DC power for tuned load PA
PDC
DC supply power
PDCA
DC power for Class-A PA
Pdiss
dissipated power
Pin
RF input power
Pout,T L
Optimum output power for tuned load PA
Symbols and Units
Pout
Output power
PPmax, f 0
Maximum power at the center frequency
Psat
Saturated power
Q
Quality factor
RL,opt
Optimum load resistance
RL,T L
Optimum load resistance for tuned load PA
RLA
Optimum load resistor for Class-A PA
Ropt
Optimum loadline impedance
RL
Load resistance
S
Scattering parameter
S11
Input reflection coefficient
S21
Transmission coefficient
S22
Output reflection coefficient
V0
DC-component voltage
V1
Fundamental-component voltage
VDS
Drain-source voltage
vds (t)
Compound (different frequency component) drain–source voltage
Vdsi
Intrinsic drain-source voltage
VGS
Gate-source voltage
Vgsi
Intrinsic gate-source voltage
Vin
Input RF voltage
Vknee
Knee voltage for FET
Vmax
Maximum voltage
vo (t)
Compound (different frequency component) output voltage
X
Reactants
xxix
xxx
Symbols and Units
Z
Impedance
Zout
Output impedance
β
The gain of output current to the gate-source voltage
∆
scattering matrix determinant
∆f
Frequency spacing
εr
Dielectric constant
η
Drain efficiency
ηT L
Drain efficiency for tuned load PA
Γ
Reflection coefficient
γ
The gain of input current to the gate-source voltage
κ
Thermal conductivity
λ
Wavelength
µ
Input stability parameter
µ
′
Output stability parameter
µn
Electron mobility
Ω
Ohm
ω
Angular frequency
φ
Phase
ρ
Resistivity
υsat
Saturation velocity
1|
1.1
Introduction
Wireless Communication Networks
Since the early invention of wireless technology, there has been growing interest on its implementations and developments, and it has been used to serve human beings in all aspects. Radio,
television and cellular phones are some of the most influential wireless inventions of human
beings. Each of these inventions is developed by introducing new standards. GSM, UMTS and
LTE are different standards for mobile phone systems. The integration of these standards is a
major issue in the base station transceivers.
In an RF transceiver chain, a power amplifier (PA) is one of the most influential RF blocks in
the transceiver chain. It is an essential block in an RF transceiver to send a considerable amount
of information to a remote destination in clear data transmissions and with minimum consumed
power. The bold words in the last sentence describe the most important characteristics of the
power amplifier operation. A considerable amount of information means high bandwidth and
capacity. Remote destination describes the output power of the amplifier. Clear data transmission
explains the linearity characteristics of a power amplifier. Finally, minimum consumed power is a
measure of the power amplifier efficiency.
Achieving good values of these characteristics is a goal for power amplifier designers over
the years. However, linearity and efficiency can not be achieved simultaneously from simple
power amplifier architecture [1] [2]. In principle, power amplifier linearity is achieved when the
signal is not clipped because it has zero harmonic contents. Nevertheless, the efficiency is only
maximum if the signal is clipped that results in minimum current and voltage overlapping. The
following subsection gives answers to the next three statements:
• The importance of the bandwidth in PA.
• Why the efficiency is significant for a power amplifier.
• The reason of choosing GaN HEMT for the PA designs in this work.
2
1. Introduction
1.2
Motivation
The goal of this thesis is to design broadband power amplifiers in high-efficiency operations with
high-output power. Usually, high-output power is defined based on wireless standard, size and
capacity of a typical cellular cell. High-output power for a base station gives a high signal to
noise ratio (SNR), which permits the use of high modulation rate near the base station. On the
other hand, high power extends the range of the signal reception and reduces the total cost of
wireless infrastructure.
1.2.1
Broadband Power Amplifier
Increasing the capacity of wireless communication requires high data rate transmissions. As a
result, new standards are used to accommodate the need of high data rates. Fig. 1.1 represents
the most common wireless standards used for data transmission. It is shown that these standards
are allocated, mostly, around two frequencies: 0.8 GHz and 2.0 GHz. For a base station, it is
convenient to integrate these standards together in one base station. This reduces the cost of the
base station and makes it easier for upgrading new standards on one base station.
1.2.2
Efficient Power Amplifier
According to [3], information and communication technology (ICT) consumes, approximately,
3 % (600 TWh) of worldwide electrical energy. Wireless mobile base stations consume almost
half of this energy [3]. Over 4 billion subscribers of mobile phones over the entire world demand
an increasing number of base stations, which comes at the cost of consumed energy. Minimizing
the dissipated power in base stations reduces the cost of the operation. Additionally, low energy
consumptions reduce the environmental impact from CO2 emissions.
The largest power consumption in a mobile base station is from the power amplifier, which
consumes 65 % of the total energy. Digital Signal processing and baseband operations are
consuming about 10 %, and AC/DC conversion components consume more than 7.5 %. The
rest of the energy (17.5 %) is consumed by the air conditioning and cooling devices of a base
station [4]. The lost energy in the latter part is the second largest consumption in a base station.
GSM-450
GSM-1800
GSM-1900
UMTS
GSM-900
LTE
LTE
DVB-T
0.5
1.0
1.5
LTE
UMTS
DVB-T
0.1
WLAN 802.11 b/g/n
2.0
2.5
3.0
freq. [GHz]
Figure 1.1: Spectrum allocation for the most common wireless standards.
3
1.2 Motivation
120 W
RF component/PA
65%
1800 W
DSP/Baseband
10%
Power Amplifier
65%
Cooling
17.5%
AC/DC Converter
7.5%
DSP/Baseband
10%
AC/DC Converter
7.5%
Cooling
17.5%
Figure 1.2: Base-station model showing the consumed power in different
blocks.
Most of the cooling system is dedicated to the heat produced from the power amplifier. Therefore,
making an efficient power amplifier minimizes, in addition to the cost of the power amplifier
energy, the cost of the cooling energy required for the base station. Fig. 1.2 presents the power
loss distribution on different base-station's components. Typical base station requires 1800 W as
an input signal, where the radiated power is about 120 W. This makes an overall base station's
efficiency 6.7 %; in other word, base stations have a 1680 W loss in the energy.
In addition, an efficient power amplifier reduces the thermal problem of an RF transistor. It
prolongs the transistor's life and gives a better linearity performance. It prevents the reduction of
the output power over the time. Achieving a better power amplifier in terms of efficiency and
output power, in addition to the bandwidth and the linearity, requires a good choice of RF power
transistors.
1.2.3
RF Power Transistor
Since the early invention of the transistor, Silicon (Si) based BJT devices were the most preferable
RF transistors for power amplifiers. However, many researches are carried to find different
transistor technologies and different materials to increase RF performances. Semiconductor
properties have different influences on different power amplifier characteristics. Table 1.1
presents the major semiconductor properties to the most-used materials. The shown properties
have different impacts on the RF performance of power amplifier applications. In this table, the
diamond is presented to show its out-performance and will not be considered in the following
analysis.
Bandgap energy: Higher value of this parameter results in a higher operating temperature. This
allows smaller devices to be fabricated compared to smaller bandgap materials. Higher
operating temperatures permit cheaper packages to be used for the device. Smaller device
4
1. Introduction
sizes increase the output impedance and, hence, make it easier to design a broadband power
amplifier.
Thermal conductivity: It measures the ability of conducting heat to the external environment.
Reducing this parameter will degrade the performance of the device over the time. Additionally, low thermal conductivity reduces electron mobility and the saturated electron
velocity, which results in a degraded efficiency. GaN and SiC have 1.70 and 4.90 eV,
respectively, which make them the best candidates for a high-power RF amplifier, and
make them good for cheaper packaging.
Dielectric constant: The physical structure of any transistor can be modelled with different
capacitors, inductors, resistors and a current source. These capacitors'values are influenced,
mainly, from the dimension of the transistor and the dielectric constant. Decreasing this
property reduces the associated capacitance and, hence, increases the load impedance. This
leads to increasing the dimensions of the transistor to increase the output power. GaN has
a relative dielectric constant of 8.90. It is the best candidate for a high bandwidth and
efficiency operation.
Breakdown voltage: This indicates the maximum applied electric field without destroying the
device. This increases the RF power swing and boosts the device power density. High
breakdown voltage is suitable to increase the doping concentration and reduces the device
dimension. As a result, high transconductance, high gain, maximum frequency and low
parasitics are obtained in the device. Low parasitics increase the efficiency of the power
amplifier. The highest breakdown voltage shown in Table 1.1 is obtained for GaN then SiC.
This is the reason for choosing these materials for a high-performance power amplifier.
Saturation velocity: Higher saturation velocity of the electron leads to the reduction of the
required time for the electrons to be transported through a channel which, in turn, increases
the operating frequency. On the other hand, the current increases with increasing the
Table 1.1: Important parameters for the most common materials used in semiconductor devices, adapted from [5, 6].
Material
Si
4H-SiC
InP
GaAs
GaN
Diamond
Bandgap Eg [eV]
1.11
3.20
1.34
1.43
3.40
5.45
Thermal Conductivity κ [W/cm·◦ K]
1.50
4.90
0.68
0.46
1.70
20
Dielectric constant εr
11.70
9.70
14.00
12.90
8.90
5.70
Breakdown voltage Ebr [V/cm]
300
2000
500
400
5000
5000
Saturation velocity υsat [cm/s]
9 × 106
2 × 107
1.9 × 107
1.3 × 107
2.3 × 107
2.7 × 107
Electron mobility µn [cm2 /V·s]
1450
500
4000
8500
800
4500
1.2 Motivation
5
velocity of the electron. The corresponding saturated electrical field indicates how fast the
electrons can be accelerated to reach their saturated velocity. GaN and SiC are the best
materials for this parameter compared to GaAs and Si devices.
Electron mobility: Increasing electron mobility will increase the velocity of the electron and,
hence, the current density increases. Moreover, a low value of mobility requires a larger
electric field to reach the saturation velocity and, in turn, the maximum current. This
results in increasing the knee effect of the transistor. The on-resistance becomes higher
for lower mobility values, which increases the losses and reduces the efficiency. The
electron mobility of GaN and SiC is the lowest among other materials shown in Table 1.1.
However, GaN HEMT has a higher electron mobility, reaching more than 1000 cm2 /V·s.
This results from the 2DEG layer produced from the discontinuity in the energy bandgap
between AlGaN and GaN. It is worth noting that it is very difficult to manufacture p−type
transistors from wideband gap materials due to their low hole mobility. Additionally, there
is no saturated hole velocity for these materials.
1.2.3.1
GaN HEMT Technology
High electron mobility transistor (HEMT) is a heterojunction field effect transistor (HFET).
Another name for this transistor is modulation doped field effect transistor (MODFET). Fig. 1.3.a
presents the basic structure of a HEMT transistor.
One of the important layers in manufacturing GaN HEMT is the substrate used in the transistor.
The most important properties for the substrate are good thermal conductivity, high resistivity
and low lattice mismatch with GaN. Table 1.2 shows that SiC is a very good substrate material
choice. However, it is expensive and not produced in large wafer size, which makes a transistor
made from this substrate very expensive compared to other high RF power transistors. After the
substrate, a nucleation layer from GaN, AlGaN or AlN is used to increase the growth quality of
other layers by optimizing the polarity of GaN crystal [7]
A modulated doped AlGaN, which is a wideband semiconductor, is grown over undoped GaN
layer, i.e., narrow-bandgap semiconductor. Modulated doped layer refers to a layer of a certain
semiconductor material doped for a certain thickness, i.e., close to the gate side, and undoped
for smaller thickness near the undoped GaN. Fig. 1.3.b shows the energy band structure of this
configuration. Due to the big bandgap difference of these semiconductor materials, there is a
bend in the bandgap at the interface of the AlGaN/GaN which attracts the electrons from the
AlGaN material and performs a two-dimensional electron gas (2DEG) layer. The reason for
this name is that the electron confined in this layer is moving at a very high speed, nearly with
saturation velocity, in y-direction, i.e., from source to drain, and in z-direction. The concentration
of electrons in this layer is particularly very high, which increases the current density of this
transistor. Furthermore, the mobility of these electrons is very high. This layer overcomes the
6
1. Introduction
Table 1.2: An important parameters for the most common substrates used in
semiconductor devices, adapted from [7].
Material
Si
4H-SiC
Sapphire
1.50
4.90
0.42
≤ 104
105 − 108
> 106
lattice mismatch with GaN [%]
−17
+3.5
−16
Wafer size [cm]
30.5
3.7
15
Cost
low
high
low
Thermal Conductivity κ [W/cm·◦ K]
Resistivity ρ [Ω· cm]
drawback of the wideband semiconductor in their low mobility [8]. This thickness of the 2DEG
layer can be controlled by the undoped layer of AlGaN, where a thick layer of this makes the
2DEG layer far from the ionized donor, i.e., doped AlGaN layer, thus electron mobility increases.
However, electron charge density decreases if the undoped AlGaN layer thickness increases
because it becomes hard for the electron to diffuse to the 2DEG layer [9].
1.2.3.2
GaN HEMT modelling
Transistor modelling is an important aspect for a RF-designer. It is beyond the thesis scope.
However, it must be briefly mentioned here. Usually transistor modelling can be classified into
three categories. First, the physical/electromagnetic model where the physical dimensions and
boundary condition for solving the current and voltage across the device are used to describe the
transistor. Usually, this model is very accurate, but it is hard to be simulated and requires fast
computers to solve its equation. Second, the empirical model which is based on an equivalent
circuit model. The basic elements in this model are curved fitted from different measurement
parameters. Third, the table based model where the transistor is described as a two port black box
x
Source
Gate
Drain
z
Doped AlGaN
2DEG
Undoped AlGaN
x
y
Schottky
gate
n AlGaN
Undoped GaN
Undoped
AlGaN
Undoped GaN
Nucleation layer: GaN/AlGaN/AlN
2DEG
Substrate: Sapphire/SiC/Si
(a)
(b)
Figure 1.3: a) Cross section view of the GaN HEMT transistor, and b) band-gap
structure of the HEMT transistor.
7
1.2 Motivation
with its response based on the applied current/voltage for each port. Most of the GaN HEMT
models are based on an empirical model because of its extrapolation property.
A compact model describing GaN HEMT behaviour is shown in Fig. 1.4 adopted from [10].
The model consists of three parts; intrinsic, extrinsic and a thermal part. The intrinsic part contains
a current source describing the drain source channel current. It also contains two other current
sources which describe the leakage current from the gate to the drain and to the source. Moreover,
two non-linear capacitors between the gate and drain, and gate and source terminals, i.e., (Cgd )
and (Cgs ). It also contains small resistances describing the losses between these terminals.
The extrinsic part contains, mainly, models of the terminal pads. Each of these pads is
modelled as an inductance, resistance and capacitance between the pads. Additionally, a drain
source capacitance is used to model the channel capacitance (Cds ). It is worth noting that
this capacitance is constant over all the voltage terminals. It is one of the advantages of a
HEMT transistor compared to other high-power RF transistors, e.g., LDMOS. This capacitor is
considered, with (Cgd ), as main non-linear capacitance seen at the output of the transistor. Hence,
C pgd
Igd
Intrinsic
Lg
Cgd
Rg
Rgd
Rd
Ld
Gate
Drain
Cgs
+
Vgsi
+
Igs
Ids
Vdsi
−
+
Vgs C pgs
−
−
Cds
Rgs
C pds
+
Vds
−
RS
LS
Source
+
Ith
Vth
−
Figure 1.4: Typical large signal GaN HEMT model.
Rth
Cth
8
1. Introduction
a linear output capacitance behaviour will enhance the switching performances of the transistor
which makes GaN HEMT a good candidate for switch mode high efficiency power amplifier. The
reason of this linear behaviour could be the high speed of the 2DEG layer which is not affected
by the external applied field.
Finally, the thermal part contains a current source (Ith ) calculated from the dissipated power.
Thermal resistance (Rth ) describes the losses, and the thermal capacitance (Cth ) represents the
thermal delay.
The drain channel current is a voltage controlled parameter described by [10]:
Ids (Vgsi ,Vdsi ) = f1 (Vgsi ) · f2 (Vdsi ,Vgsi ) · f3 (Vdsi ) · f4 (∆T )
(1.1)
where f1 (Vgsi ) is the transfer function of the transistor and given by:
f1 (Vgsi ) =
CDvc · [1 + tanh(β(Vgsi −Vc ) + γ(Vgsi −Vc )3 )]
+ CDvsb · [1 + tanh(δ(Vgsi −Vsb ))]
(1.2)
The parameter CDvc is the drain-source current at Vc gate voltage, where the transconductance is
maximum (gm,max ). Parameter β is calculated by gm,max /CDvc . The second term parameters are
used to fine-tune the model at high gate voltages.
The f2 (Vdsi ,Vgsi ) describes the output conductance of the transistor and is given by:
f2 (Vdsi ,Vgsi ) = 1 +
λ
2
Vdsi , where Vto = Vc −
2
1 + ∆λ (Vgsi −Vto )
β
(1.3)
The parameter λ models the drain current in the saturation region. ∆λ is a parameter used to
fine-tune the drain-source current in the sub-threshold region defined by Vto .
The f3 (Vdsi ,Vgsi ) describe the triode region of the transistor and is given by:
f3 (Vdsi ) = tanh(αVdsi ), where α =
α0
1 + KVgs
(1.4)
The slope of the drain-source current in the linear transistor region is controlled by the parameter
α0 . However, K is introduced here to add the dependence of the linear region on the gate source
region.
Finally, f4 (∆) models the behaviour of the drain-source current with respect of the temperature.
It is given by:
∆T
(1.5)
f3 (Vdsi ) = 1 + κ , where ∆T = Rth Ith
T0
The thermal current is equal to the total power passed through the channel, i.e., Ith = IdsVds .
However, it is worth to note that there are different models for GaN HEMT transistors, but
more or less they have the basic principle of the already described model.
1.3 State of the Art
1.3
9
State of the Art
Broadband power amplifier with high-efficiency operation has been under the research spot for
the last decade. Most of these designed amplifiers were based on GaN HEMT technology. Table
1.3 represents the state of the art of highly efficient power amplifiers designed recently based on
GaN HEMT.
The designed amplifier in [11] uses Class-E PA concept. The resonator of the matching
network uses spiral inductors based on a two layer substrate. The parasitic of the designed
output resonator were used for the matching network. Without second harmonic trapping at the
input matching network, the relative bandwidth was 22.22 %. The authors had shown that using
the second harmonic trapping at the input side increases the relative bandwidth. However, this
reduces the peak efficiency.
In [12], the author used the Class-J concept for designing linear high-efficiency PA. The output
impedances, which gave optimum waveforms for the class, were acquired from the load-pull
measurement system. The amplifier delivered a constant 10 W output power with drain efficiency
ranges from 55 % to 65 %.
In [13], An octave bandwidth PA was designed using low pass matching network techniques,
based on ideal lumped elements. From a source/load-pull simulation, optimum source/load
impedances were extracted. The ideal matching network was converted step-by-step to be
realised using microstrip lines. The achieved output power was from 10 W to 15 W with drain
efficiency over the range of 57 − 72 %.
The amplifiers presented on [14], [18] and [19] were implemented based on a push-pull
operation where they first delivered 100 W output power using 4-cell PA each of which has 30 W
minimum output power. The latter two amplifiers used 2-cell of a power amplifier based on 45 W
PA in two different bands and two different relative bandwidths.
In [15], the authors presented 1 GHz power amplifier based on simplified real frequency
technique (SRFT). The amplifier operated with nearly 42 % bandwidth. The output power is
45 W, and the average drain efficiency is 63 %.
The concept of realizing the amplifier in [16] is by implementing distributed second harmonic
impedance. The output matching network is composed of two blocks; the first was the fundamental matching network, and the second was the second harmonic termination. About 25 %
relative bandwidth was achieved with an average output power 45 W, and average drain efficiency
of 66 % was achieved.
In [17], the authors implemented the novel concept of a continuous mode of operation for
the power amplifier. This concept introduces a new dimension for a range of impedances, which
are in favour of broadband operations. It used an output termination for the first three harmonic
impedances. The average drain efficiency achieved was 74 % with output power of 10 W. The
achieved operating bandwidth was more than 66 %.
10
1. Introduction
Table 1.3: State of the art for broadband power amplifier with more than
50 % drain efficiency published in the last five years Based on GaN HEMT
technology.
Year/Ref.
Bandwidth [GHz] BW [%]
Pout [W]
Gain [dB]
η [%]
2009 [11]
2.00 − 2.50
2.10 − 2.70
22.22
25.00
7.10 − 12.80
9.30 − 12.70
10.73 − 13.29
10.90 − 13.26
74.00 − 77.00
55.00 − 66.00
2009 [12]
1.40 − 2.60
60.00
10.00
10.20 − 12.20
55.00 − 65.00
2009 [Paper A]
0.60 − 1.00
50.00
36.00 − 52.00
10.20 − 12.20
66.00 − 87.00
2010 [13]
1.90 − 4.30
77.42
10.00 − 15.00
9.00 − 11.00
57.00 − 72.00
2010 [14]
0.10 − 1.00
163.64
104.00 − 121.00 15.50 − 18.60
61.40 − 76.60
2010 [15]
1.90 − 2.90
41.67
45.00 − 47.00
10.00 − 11.80
2010 [16]
1.80 − 2.30
24.39
45.00 − 48.00
11.50 − 14.00 60.00 − 76.00
2010 [Paper B]
1.55 − 2.75
50.00
9.80 − 15.50
10.20 − 12.20 71.00 − 87.00
2011 [17]
0.55 − 1.10
66.67
8.50 − 13.20
9.50 − 12.00
65.00 − 80.00
2011 [18]
0.9 − 2.20
83.87
10.00 − 20.00
10.00 − 13.00
63.00 − 89.00
2011 [19]
0.10 − 1.00
163.64
82.20 − 107.50
15.20 − 16.30
51.90 − 73.80
2011 [20]
2.15 − 2.65
20.83
11.40 − 15.00
11.00 − 12.50 65.00 − 76.00
2011 [Paper C]
1.55 − 2.53
41.10
89.00 − 110.00
8.90 − 11.00
60.00 − 65.00
61.00 − 79.00
Finally, in [20], the broadband concept of continuous mode of PA operation was used to find
the load impedances up to third harmonic load impedance. SRFT was used to synthesize the
output matching network. The achieved operating bandwidth was 21 % with more than 10 W
output power and more than 65 % drain efficiency.
Comparing these results to the already published work by the authors, it is easily seen that
the designed amplifiers in this work are among the top listed broadband state of the art power
amplifiers. Additionally, the designed broadband power amplifiers cover all the wireless standards
from VHF to S-Bands and have different ranges of output power, i.e., from 10 W passing through
50 W to 100 W.
1.4
Thesis Outline
To achieve the thesis goals, this work is divided into two parts: theory and implementation.
The second chapter presents the most important figure of merit's definitions for power
amplifier. Most of the definitions are used in this work and the rest are mentioned to give a better
overview of the concept. The last section of this chapter talks about the stability criteria of power
amplifier designs. Finally, some techniques that suppress the oscillation problem are presented.
Chapter three gives basic and theoretical concepts of power amplifier designs. It starts with
1.4 Thesis Outline
11
the load-pull technique and the load line theory. Followed by the power amplifier classes, which
are divided into classical classes and the highly efficient classes. This is supported with design
equations. The last section analyses the efficiency, gain and power limitations of the power
amplifier from a typical parasitic of simple FET model. This chapter ends the discussion in the
theory section of this dissertation.
Chapter four presents first step of designing broadband efficient power amplifiers. It discusses
two published papers of the authors, [Paper D] and [Paper E]. It describes the design of single
band power amplifiers using the two modes of operation; CMCD PA and Class-F−1 PA. Their
design approach and their measurements are shown for each of them.
Chapter five is the core of the thesis. The theory of the broadband matching technique is
analysed. The implementation of a matching network, which is used throughout the thesis, is
presented. Design procedure of a broadband power amplifier is also shown. This is followed by a
design of two broadband power amplifiers for VHF and UHF applications. Extensive study and
analysis of measured data is given. It also discusses the behaviour of the broadband amplifier
over an entire band and gives a description to the power amplifier class of operation for every
single frequency over the band, which gives a continous mode of operation. This section is based
on [Paper A], [Paper F] and [Paper G].
In Chapter six, full broadband design concepts for L-band power amplifiers with two different
output powers are presented. This is based on the continuity behaviour found in the previous
chapter. A load pull simulation is shown to implement what is called the "safe-zone" on the
Smith chart is analysed. Design and consideration of a high-output power amplifier is given.
Evaluation from simulation as well as measurement results are presented. These two amplifiers
were published in [Paper B] and [Paper C].
Chapter 7 concludes the overall work and gives key results of the broad band highly efficient
power amplifier based on this contribution.
12
1. Introduction
2|
2.1
Power Amplifier Characteristics
Power Amplifier Definitions
A RF power amplifier is an electronic device which converts DC-power to an RF power with the
same RF input behaviour. From this definition, there are different characteristics for RF power
amplifiers. The output power, from Fig. 2.1, can be defined as:
Pout = PDC − Pdiss
(2.1)
where: Pout is the output power, PDC is the input DC power and Pdiss is the dissipated power. The
dissipated power includes ohmic losses, switching losses and losses in matching networks.
2.1.1
Basic Definitions
RF output power is the converted power to the load, mostly 50 Ω, from the DC-power within a
finite bandwidth. This power is represented as a thermal power in the load, which is expressed as:
1
∗
Pout = Re{Vout · Iout
}
2
(2.2)
RF input power is the available input power that contains the signal information in the finite
PDC
Pin
PA
Pout
Pdiss
Figure 2.1: Energy conservation in power amplifier operation.
14
2. Power Amplifier Characteristics
bandwidth, which is expressed as:
1
∗
Pin = Re{Vin · Iin
}
2
(2.3)
DC input power is the injected power at DC, which is the main source of the power amplification:
PDC = VDC · IDC
(2.4)
In an ideal FET operation the DC voltage and current in Eq. (2.4) are replaced with their
respective drain components.
2.1.2
Gain Definitions
Gain definition depend on the reference plane and matching network. Fig. 2.2 shows four basic
definitions for the power which will help for defining the gain.
• Pin is the input power stimulating the transistor.
• Pav,S is the power available from the source. It is equal to the Pin if the input matching
network is conjugate match at the source side, otherwise it is larger than Pin .
• PL is the delivered power to the load.
• Pav,L is the device output power which is equal to the PL if the output matching network is
a conjugate match, otherwise it is larger than PL .
Power gain is the ratio of an output power to an input power, i.e.;
GP =
PL
Pin
(2.5)
It depends on the output impedance seen from the DUT but never on the source impedance.
Pin
Zs
PL
⎡
Z11
⎢
⎢
⎣
Z21
+
Vs
−
Pav,S
Z12
⎤
⎥
⎥
⎦
ZL
Z22
Pav,L
Figure 2.2: Two-port network with power definitions.
15
2.1 Power Amplifier Definitions
Available gain is the ratio of the power available from the DUT to the power available to the
DUT. It depends on the source impedance.
GA =
Pav,L
Pav,S
(2.6)
Transducer gain is the ratio of the power delivered to the load to the available power from
source. In this definition, both source and load impedance influencing this gain:
GT =
PL
Pav,S
(2.7)
It is worth noting that GP ≥ GT ≤ GA . These gain definitions are used with different applications
and with different circuits. However, the transducer gain is the measured gain which will be used
in this work unless it is specified.
One of the important figures of merit of the RFPA is the 1-dB compression point. This point
is found when the gain is one dB less than the small signal gain. This phenomena is a natural
behaviour for the nonlinear operation of the active devices. The corresponding output power and
input power is represented by; Pout,1−dB and Pin,1−dB , respectively. Fig. 2.3 clarifies the 1-dB
compression point concept.
2.1.3
Efficiency Definitions
For any power conversion, a measure for this conversion is usually named as efficiency. In
FET-RFPA, it is called as drain efficiency and its mathematical definition is:
η=
Pout
PDC
(2.8)
The drain efficiency increases exponentially with the input power (in Logarithmic). However,
for higher input power, near 1-dB point occurs, the efficiency reaches its maximum and the gain
reduces further. Additionally, the output power is directly proportional to the input power. Hence,
the influence of the input power must be included leading to the power added efficiency (PAE)
definition:
Pout − Pin Pout · (1 − G1 )
=
(2.9)
PAE =
PDC
PDC
Another reason for this new definition is that drain efficiency increases as the operating conduction
angle decreases, where the required input power increases beyond this point and reaches the 1-dB
compression point, Fig 2.3.
Additionally, there are further different definitions for the efficiency. However, these are the
most common used in RFPA.
16
2. Power Amplifier Characteristics
80
30
Pout,1dB
60
η
Pout
PAE
20
40
Gain
10
η, PAE [%]
Pout [dBm], Gain [dB]
40
20
0
0
5
10
Pin
15 Pin,1dB 20
0
25
[dBm]
Figure 2.3: Typical performance for a power amplifier versus input power.
2.2
Linearity and Distortion
Linearity, as a term, is a measure of the output current and voltage waveforms’ clarity compared
to the input waveforms. The distortion reduces, further, the signal quality and, consequently,
the receiver can not recover the transmitted information completely. Modern communication
standards such as WCDMA signals, demand strict requirements regarding the linearity. The
nonlinear effects in power amplifiers are usually expressed in the form of a third-order power
series expansion:
vo = α1 vi + α2 v2i + α3 v33
(2.10)
where vo is the output voltage, vi is the input voltage and αi are the voltage coefficients. This
equation is the simplest expression that represents the nonlinear effect. However, more efficient
expression (Volterra series) which includes time as a dependent variable, is used for advanced
linearity analysis. Fig. 2.4 represents the most common linearity measurements categorized
based on the input signal. The next few subsections discuss these phenomena.
Linearity
Multi Tone
Single Tone
1-dB Compression point
AM-AM/AM-PM
Harmonic distorsion
Intermodulation distortion
Intercept point
Dynamic Signal
ACPR/ACLR
Figure 2.4: Different types of linearity measurements.
17
2.2 Linearity and Distortion
2.2.1
Single Tone
Single-tone measurements are the basic method of the RF power amplifier to quantify linearity
performance. If the input signal for a PA is expressed as:
vi = γ cos(ωt)
(2.11)
where γ is the amplitude of the input signal and ω is the radial operating frequency. The output
power can be obtained from (2.10) as:
vo =
α2 γ 2
3
α2 γ2
α3 γ3
+ (α1 γ + α3 γ3 ) cos(ωt) +
cos(2ωt) +
cos(3ωt)
2
4
2
4
(2.12)
As it can be observed from (2.12), the output voltage contains harmonic components in addition
to the fundamental and DC components. The voltage gain for the fundamental component is
expressed as:
vo
3
= (α1 + α3 γ3 )
(2.13)
vi
4
It is evident from (2.13) that the gain is proportional to the cubic input voltage amplitude (γ). This
gain compresses if and only if the α3 is negative; otherwise it will expand, which is not a nature
of the nonlinear devices. This gain shows the compression discussed before, which is usually
referred to as the maximum input that can be applied to a RFPA without distorting the signal,
in Fig. 2.5. For the other harmonic component in (2.12), it can be easily seen that the output
v2
harmonic power (P =
) increases twice as fast as in the fundamental power for the second
2R
harmonic and three times as fast as in the fundamental power for the third harmonic, Fig. 2.6.
2.2.1.1
AM-AM/AM-PM
AM-AM is a measure of the compression between the output and the input waveforms and can
simply be expressed by the gain expression. AM-PM is a measure of the change in the output
Voltage Gain [dB]
15
Gv,1dB
10
5
0
0
5
Vi,1dB 10
15
vi [dB]
Figure 2.5: Voltage gain compression as in (2.13).
18
2. Power Amplifier Characteristics
40
Pout [dBm]
30
Pout, f und
20
Pout,sec
1
10
Pout,third
0
2
3
-10
0
5
10
15
20
25
Pin [dBm]
Figure 2.6: Single tone output power for the fundamental, second harmonic
and third harmonic.
phase that depends on the input amplitude, expressed as:
AM − PM = ϕo (vi )
(2.14)
where ϕo and vi are the output phase and the input amplitude components, respectively. Usually,
these parameters are plotted versus the input power, Fig. 2.7.
2.2.1.2
Total harmonic distortion
The harmonic distortion due to n-order of harmonic is defined by:
HDn =
Pout,n
Pout, f und
(2.15)
AM-AM [dBm], AM-PM [deg.]
An ideal operation for a PA requires zero harmonic distortion (HDn ). Higher value of this
parameter reduces the efficiency of the power amplifier and increases the nonlinearity.
30
20
10
AM-PM
0
AM-AM
-10
0
5
10
15
20
25
Pin [dBm]
Figure 2.7: Typical AM-AM/AM-PM curves for power amplifiers.
19
2.2 Linearity and Distortion
In a straightforward manner, the total harmonic distortion is defined by:
T HD =
Pout,nth
∑ Pout, f und
(2.16)
n≥2
The above expressions are usually expressed on a logarithmic scale with reference to the fundamental (dBc). This describes how far the harmonic powers are from the fundamental power.
2.2.2
Multi Tone
Single tone measurements and analysis give limited information regarding the linearity performance. In reality, the input signal for a PA is not a single tone signal. Hence, a multi tone test gives
a better picture of the distortion that might appear on the output signal of a PA. In this section,
analysis for a two-tone signal is presented and discussed. Nevertheless, the same analysis applies
for higher-order tones.
2.2.2.1
Intermodulation distortion
In reality, the input signal of a PA consists of two closely spaced frequencies f1 and f2 ( f1 < f2 ).
For simplicity, in this analysis both signals will be assumed to have an equal amplitude:
vi = γ cos(ω1t) + γ cos(ω2t)
(2.17)
Applying (2.17) in (2.10) and making some mathematical simplifications, the output signal is
given by:
α2 γ 2
vo =
9
+ [α1 γ + α3 γ3 ][cos(ω1t) + cos(ω2t)]
4
+
α2 γ 2
[cos(2ω1t) + cos(2ω2t)]
2
+
α3 γ3
[cos(3ω1t) + cos(3ω2t)]
4
(2.18)
+ α2 γ2 [cos(ω1t + ω2t) + cos(ω1t − ω2t)]
+
3α3 γ3
[cos(ω1t + 2ω2t) + cos(ω1t − 2ω2t) + cos(2ω1t + ω2t) + cos(2ω1t − ω2t)]
4
The output voltage from the two-tone input signal contains an infinite number of a combination
20
2. Power Amplifier Characteristics
from these tones in the form of:
n f1 ± m f2
(2.19)
where n and m are integers ≥ 0. The sum of these products gives the order of distortion. The
second-order intermodulation products of two signals at f1 and f2 would occur at f1 + f2 , f1 − f2 ,
2 f1 and 2 f2 , as shown in Fig. 2.8. From this figure, it can be concluded that the even products
are out of band and, hence, they are less important than the odd product. Furthermore, the most
influential odd product on the fundamental component is the third-order intermodulation product
(IMD3 ). It is because of being the closest product to the fundamental component and highest
amplitude component compared to the other odd products.
2.2.2.2
Intercept point
If the third intermodulation power is plotted with the fundamental tone versus the input power,
new parameters can be extracted from this plot called the third order intercept point, as shown
in Fig. 2.9. This point can be referred as the third order input intercept point IIP3 and third
order output intercept point OIP3 . They are usually known to be 10 dB higher than the 1-dB
compression power for the one tone power [21]. From Fig. 2.9, it can be seen that the IMD3 has
a 3-dB slope versus the input power on the logarithmic scale. Usually, for the measurement, this
is valid for the low power drive. However, when the power increases, the fifth order becomes
more effective, and the translated IMD3 from this order become more visible. Hence, for higher
input power, the IMD component will have higher slope than 3-dB relative to the input power.
If the phases of the third- and fifth-degree coefficients are equal, the total IMD3 responses will
expand. However, if the phases are opposite, the IMD3 distortion will be locally reduced. This
explains why notches (sweet-spots) in the IMD3 (and high-order) have been reported at certain
amplitudes of output power.
f1 f2
PSD
f2 − f1
IMD3
2 f1 − f2
2 f2 − 2 f1
3 f2 − 3 f1
3 f1 − 2 f2
4 f1 − 3 f2
2 f2 − f1
3 f2 − 2 f1
f2 + f1
2 f1
2 f2
4 f2 − 3 f1
f
Figure 2.8: Output frequency component of an amplifier excited by a two tone
signal.
21
2.2 Linearity and Distortion
60
Pout [dBm]
OIP3
40
20
1 Pout, f und
0
PIMD3
-20
3
-40
-60
0
10
IIP3 30
20
40
Pin [dBm]
Figure 2.9: Third order intercept point example.
2.2.3
Dynamic Signal
The previous two sections discussed the linearity with respect of discrete frequency input signals.
However, modern communication standards have many frequency components that need a more
precise measure for the linearity. An important measure of the linearity for a dynamic input
signal is the adjacent channel power ratio (ACPR) or adjacent leakage power ratio (ACLR). Fig.
2.10 shows the typical spectrum for a UMTS signal for a PA. From this figure the ACPR can be
defined as the ratio of the power in the main band (carrier band) to the power in the adjacent band
(adjacent channel), mathematically:
∫
Pout ( f )d f
BA1 Pout ( f )d f
B
ACPRu = ∫ c
(2.20)
∫
Pout ( f )d f
BA2 Pout ( f )d f
B
ACPRl = ∫ c
(2.21)
Spectrum [dBm]
where Bc , BA1 , BA2 , ACPRu and ACPRl are the signal bandwidth, the upper adjacent bandwidth,
the lower adjacent bandwidth, the upper ACPR and the lower ACPR, respectively. Generally
speaking, the power amplifier must meet certain ACPR depending on the applied input power.
For example, for a WCDMA signal, both bandwidths for the carrier and the adjacent channel are
5 MHz without any spacing between them. The ACPR must be more than -45 dBc [22].
Carrier Signal
Adjacent Signal
BC
BA2
Adjacent Signal
BA1
Freq. [Hz]
Figure 2.10: Typical spectrum for a UMTS signal for PA.
22
2. Power Amplifier Characteristics
ACLR has the same definition as the ACPR but the output power is filtered through the system
filter and (2.20) and (2.21) can be applied directly.
2.3
Bandwidth
All the characteristics defined previously and others can be the targeted goal for any designed RF
power amplifier. However, the specifications for a power amplifier must be achieved in a range of
frequencies, or in one or more frequencies with a finite range. This is what is called a frequency
bandwidth.
2.4
Stability problem with PA
In principle, any active device can oscillate without applying any RF input power due to high
gain. Specifically, RF power amplifiers can oscillate if impedance, load mismatch, input power,
temperature and/or supply voltage change. Over the years, there has been extensive studies on
RF power amplifier stability and how it could be solved. The most common oscillation problem
in RF PA will be discussed in addition to other oscillation problems. More details can be found
in literature such as: [21, 23–25]
Usually, RF power amplifier stability is tested using small signal S-parameters. The reason for
this is that stability issues for large signal behaviour is non-linear and depends on the transistor
terminal voltages [24,25]. The most common method to determine the stability is by using rollet's
factor K [26]:
1 − |S11 |2 − |S22 |2 + ∆
2 |S21 S12 |
(2.22)
∆ = |S11 | |S22 | − |S12 | |S21 |
(2.23)
K=
where
For unconditional stable operation, the power amplifier must satisfy (2.24) [27]:
K > 1
∆ < 1
(2.24)
These two conditions are verified using the equivalent circuit model in the simulation from very
low frequencies to very high frequencies usually until the maximum available gain reaches 0 dB.
On the other hand, there are two other conditions which can replace (2.24) [28]:
1 − |S11 |2
⏐
µ = ⏐⏐
> 1
∗ ∆⏐ + |S S |
S22 − S11
21 12
1 − |S22 |2
′
⏐
> 1
µ = ⏐⏐
∗ ∆⏐ + |S S |
S11 − S22
21 12
(2.25)
23
2.4 Stability problem with PA
The advantage of these parameters is that they can identify where the un-stability occurs, i.e., µ
′
for the input side and µ for the output side. Additionally, they tell how far the stability is from
the presented impedance at the input and output terminals [24].
2.4.1
Oscillation suppression techniques
Stabilization network technique prevents the amplifier from going into the unstable region and it
lowers the amplifier gain. The most common stabilization networks are shown in Fig. 2.11. For
very-high gain transistors, a series resistor can be used in series with the gate, as in Fig. 2.11.a,
to reduce the negative resistance and force the unstable region to be outside of the Smith chart.
However, this circuit may reduce the gain drastically. Usually, this resistance value is very small
to allow reasonable gain.
Another stabilization technique is a parallel RC circuit connected in series to the gate, Fig.
2.11.a. This circuit is similar to the previous; however, the capacitor is used to bypass the RF
component in the targeted design. Thus, a capacitor with self-resonant frequency (SRF) centred
on the targeted band is used to pass the wanted signal to the transistor. It is worth noting that the
resistor can be high value without reducing the gain in the targeted band because it will be passed
through the capacitor.
Fig.2.11.c is another technique, which suppresses the RF component which has a high gain
and may cause an oscillation. This circuit is a narrow band circuit because it is used to short out
the unwanted RF component. The SRF of this capacitor is chosen for the unwanted RF signal
where the series resistance is very high to block the operated band to be shortened out.
The last stabilization circuit, Fig. 2.11.d, is simply the same technique as the first one in that
it reduces the negative resistance. However, this resistance can be used to suppress the oscillation
Rs
R1
Q1
Q1
Cs
(a)
(b)
Q1
Q1
Rp
R p2
Cp
Lp
(c)
(d)
Figure 2.11: Different stabilization techniques are used in this work.
24
2. Power Amplifier Characteristics
from the DC-source. This technique is better than the one used in Fig. 2.11.a in that it does not
reduce the total performance of the designed PA.
These circuits and many others can be used alone or combined to reduce the oscillation of the
PA. The oscillation can be measured simply using the spectrum analyser with full sweep. Any
pulses seen on the spectrum, without applying an RF signal, means an oscillation and must be
suppressed using one of the four circuits shown in Fig. 2.11.
3|
3.1
Power Amplifier Operation
Load line and PA matching
As it was shown in Chapter 1, FET transistors are usually modelled as a voltage controlled
current source. This source has upper and lower limits, which can be used for calculating the
optimum load for PA. Considering a simple FET model as shown in Fig. 3.1, it can be seen that
the minimum and maximum voltages are between 0 and Vmax and the minimum and maximum
currents are between 0 and Imax . If the maximum power is required from this source in highly
linear operation, the voltage and current waveforms should be allowed to swing between these
extreme limits symmetrically around the DC drain voltage and current. As a result, the time
domain behaviour of the current waveform versus the time domain behaviour of the voltage
waveform can be imposed into the I-V curve. The resulted line is called a load line and it has a
1
slope of RL,opt
, Fig 3.2. This load impedance (RL,opt ) can be calculated using the known slope
equation:
Vmax − 0 2VDC Vmax VDC
RL,opt =
=
=
=
(3.1)
Imax − 0
Imax
2IDC
IDC
If the load impedance is lower than the optimum load impedance,RL < RL,opt , the drain
current swings between zero and Imax and the drain voltage swings in the range of ±Imax RL /2
symmetrically around VDC . This operation is called as current clipping. On the other hand, if the
load impedance is higher than the optimum load impedance, RL > RL,opt , the drain voltage varies
between 0 and Vmax where the drain current changes in the range of ±Vmax /2RL symmetrically
around IDC . This operation condition is known as voltage clipping.
As a conclusion, if RL = RL,opt , the transistor works with the maximum rating condition
+
+
Vin
−
Vgs
−
+
Id = gmVgs
Figure 3.1: Simple FET model.
Vds
−
26
3. Power Amplifier Operation
Ids
Imax
RL < RL,opt
IDC
Vmax RL
2
1/RL,opt
Q − Point
RL > RL,opt
Vmax RL
2
Imax RL /2
Imax RL /2
VDC
Vmax Vds
Figure 3.2: Characteristic I-V curve for ideal FET operation.
where the delivered power is at maximum. The output power of this case is given as:
1
1
Pout = VDC IDC = Vmax Imax
2
8
(3.2)
The DC power delivered to the transistor is:
1
PDC = VDC IDC = Vmax Imax
4
(3.3)
As a result the drain efficiency is given by:
η=
Pout
1
=
PDC 2
(3.4)
This is the maximum theoretical efficiency of a Class-A power amplifier. In this class, the
transistor works as a current source, conducting all the time (2π), by choosing the quiescent point
to be exactly in the middle of the device current and voltage, as in Fig 3.2. It is the ideal choice
for the applications that require high linearity amplifications because the drain voltage and current
remain unclipped for all the input values below the 1-dB compression. However, this class has
the poorest efficiency given that all the time there is overlapping between the drain voltage and
current, see Fig 3.3.
Vd
Vd [V], Id [A]
Id
0
π/2
π
3π/4
2π
ϑ [rad]
Figure 3.3: Class-A power amplifier waveforms
27
3.2 Power Amplifier Classes
3.1.1
Source/Load Pull
To this point, all the discussions are made for an optimum load impedance which produces
maximum power. However, for each performance, e.g., power, PAE, intermodulation, etc.,
there is a different optimum load impedance. This impedance can be called absolute maximum
impedance for a specific performance. If a certain performance tolerance is accepted for the
design, a range of load impedances can be applied to the transistor to give a broadband behaviour.
Fig. 3.4.a and Fig. 3.4.b show a typical load pull simulation for three different performances,
i.e., output power contours, PAE contours and IMD3 contours. It also shows the impedance for
fundamental and second harmonic impedance, respectively. As it can be seen from Fig. 3.4.a,
the optimum impedance for maximum output power and PAE are different. Consequently, the
power amplifier can be designed either for high efficiency or high output power. The same can
be applied for IMD3 . Another observation made from Fig. 3.4.b is that the performances never
tend to have full contours in the Smith Chart area for second harmonic load-pull. Source/load
pull measurement setup is beyond this thesis' scope. More details can be found in the text
books [21, 25, 29].
3.2
Power Amplifier Classes
In the previous section, a short introduction for a Class-A power amplifier was presented. This
class is the basic operating class of PA. It works on full conduction operation, allowing maximum
linear operation and minimum efficiency. Reducing the conduction angle gives a broad range of
operating classes. These classes can be classified in three different categories based on their drive
and their output harmonic impedance. Fig 3.5 shows these classes.
Classical classes can be designed by terminating the harmonic impedances with short circuit
(a)
(b)
Figure 3.4: Typical load pull simulation showing output power (filled circle),
PAE (cross symbol) and IMD3 (solid) for, a) fundamental load impedance, and
b) second harmonic load impedance.
28
3. Power Amplifier Operation
RF Power Amplifier
Classes
Switched-Mode
Classes
Class-D
Class-E
Class-S
Classical Classes
Class-A
Class-AB
Class-B
Class-C
Harmonically
tuned PA
Class-F
Class-2nd /Class-J
Class-E/Fn
Figure 3.5: Classification of power amplifier
and changing the bias to make the conduction angles as required by each class. Switched mode
power amplifiers require high drive signals and a different harmonic termination than the classical
classes. Finally, the harmonic tuned power amplifier (HTPA) is a state between the classical
classes and the switched-mode power amplifier. In the following sections, a brief introduction of
some of these classes will be presented with their figure of merits.
3.2.1
Classical classes
Fig 3.6 shows the load line of these classes, their drain waveforms, their input drive signal and
their operating points. The drain voltage waveform is the same for all classes and swings between
0 and 2VDC . On the other hand, the current waveform changes according to the bias point, where
it reaches to half rectified signal for a Class-B operation and can be zero for a Class-C operation
if the conduction angle is zero. As the conduction angle reduces the overlapping reduces, and
the clipping increases. This increases efficiency and none-linearity. Usually, a Class-AB (with
conduction angle between 180◦ and 360◦ ) is the most designed class because of its fair linearity
and efficiency. A typical schematic for these classes is shown in Fig 3.7, where all the higher
harmonics are terminated as short circuits. This termination ensures a half-sinusoidal current
waveforms, that has a duration specified by the input conduction angle, and full sinusoidal voltage.
Starting from the drain current waveforms with conduction angle ϕ, as shown in Fig 3.8, the
drain current can be written as:
{
I0 + I1 cos(ωt) if |ωt| < ϕ/2
ids (ωt) =
(3.5)
0
otherwise
where ω = 2π f is the radian frequency, I0 and I1 are the DC and the fundamental drain current,
respectively.
29
3.2 Power Amplifier Classes
Id [A]
Id [A]
A
A
AB
AB
CB
Vg [V ]
B
VddC
t[s]
Vd [V ]
t[s]
t[s]
Figure 3.6: Classical PA classes waveforms, bias points, load lines and drive
signals.
If ωt = 0, a maximum current is achieved if:
Ids = Imax = I0 + I1
(3.6)
The current becomes zero for ωt = ϕ/2, hence:
I0 = −I1 cos
ϕ
2
(3.7)
Substituting (3.6) and (3.7) in (3.5), the drain current can be written as:
⎧
Imax
ϕ
⎨
ϕ [cos(ωt) − cos 2 ] if |ωt| < ϕ/2
1 − cos 2
ids (ωt) =
⎩
0
otherwise
(3.8)
Vdd
I0
Cb
Pin
ids (t)
+
Q1 v (t)
ds
−
+ io (t)
@ f0
C0
L0
vo (t)
Figure 3.7: Typical schematic for classical classes.
−
RL
30
3. Power Amplifier Operation
Id [A]
IMAX
ϕ
ωt[rad/s]
Figure 3.8: Drain current for general conduction angle.
from (3.8) the drain current can be written in Fourier series expression:
Id (ωt) = I0 + I1 cos(ωt) + I2 cos(2ωt) + I3 cos(3ωt) + ...
with the following coefficients [24]:
⎧
Imax
ϕ
ϕ
⎪
⎪
ϕ 2 sin 2 − ϕ cos 2
⎪
⎪
2π[1 − cos 2 ]
⎪
⎪
⎨
Imax
ϕ − sin ϕ
In =
2π[1 − cos ϕ2 ]
⎪
⎪
⎪
⎪
4 sin n ϕ2 cos ϕ2 − 4n sin ϕ2 cos n ϕ2
Imax
⎪
⎪
⎩
n(n2 − 1)
2π[1 − cos ϕ2 ]
(3.9)
if n=0
if n=1
(3.10)
n≥2
These harmonic components are drawn in Fig 3.9. The current components decrease with higher
harmonics. For Class-B PA, there are no odd harmonic components. On the other hand, in
Class-B PA operation, the even components have different polarity compared to the neighbour
even current component.
The drain voltage, from Fig 3.6, is:
vd (ωt) = V0 −V1 cos(ωt)
(3.11)
0.6
I1
In /IMAX
0.4
I0
I2
0.2
0
I7
Class-B
Class-A
Class-AB
Class-C
-0.2
0
π/2
π
3π/2
2π
ϕ [rad]
Figure 3.9: Drain current DC and harmonic component for the DC, fundamental
and the harmonics up to the fifth components.
31
3.2 Power Amplifier Classes
where Vdd is the drain DC voltage, and V0 is the peak output voltage which is equal to Vdd . The
optimum load impedance for the general conduction angle is given by:
ϕ
Vdd 1 − cos 2
RL (ϕ) =
2π
Imax ϕ − sin ϕ
(3.12)
For the full conduction angle (i.e., 2π) operation, the load impedance is:
RL (2π) = 2
Vdd
= RLA
Imax
(3.13)
Substituting (3.13) in (3.12), the load resistance is equal to:
RL (ϕ) = πRLA
1 − cos ϕ2
ϕ − sin ϕ
(3.14)
The output power, DC power and drain efficiency can be derived in the same way:
PDC (ϕ) = Idd Vdd
(3.15)
I1V1 PoA ϕ − sin ϕ
=
2
π 1 − cos ϕ2
(3.16)
Po
ϕ − sin ϕ
= ηA
PDC
2 sin ϕ2 − ϕ cos ϕ2
(3.17)
Po (ϕ) =
η(ϕ) =
ϕ
ϕ
PDCA 2 sin 2 − ϕ cos 2
=
π
1 − cos ϕ2
The above equations are in reference with Class-A PA design parameters mentioned previously
in (3.1)-(3.4). The output power and the drain efficiency are drawn in Fig 3.10. From this figure,
the output power is the same for Class-A and Class-B PA conditions, while the drain efficiency
is 50 % for Class-A PA and 78.5 % for Class-B PA. However, Class-AB PA has the maximum
4
output power (7.3 % more than Class-A) with π conduction angle where the efficiency is 65 %.
3
A Class-C power amplifier, the most non-linear PA class, could achieve a higher drain efficiency
(100 %) but as output power approaches zero, the conduction angle decreases. Table 3.1 shows
Pout [dBm], η [%]
1.2
η
1
0.8
0.6
Pout
0.4
Class-B
0.2
Class-A
Class-C
Class-AB
0
0
π/2
π
3π/2
2π
ϕ [rad]
Figure 3.10: Drain efficiency η and output power Pout for general conduction
angle.
32
3. Power Amplifier Operation
Table 3.1: Design Parameters for Class-AB, Class-C and Class-B PAs with
Class-A PA Parameters.
250o
π
RL
0.93RLA
RLA
π
2
1.612RLA
PDC
0.82PDCA
0.64PDCA
0.33PDCA
Pout
1.073PoA
PoA
0.6PoA
65%
78.5%
94%
Conduction Angle
η
typical Design parameters for Class-AB and other PA for different conduction angles.
3.2.2
High efficiency classes
Most of highly efficient power amplifiers are based on harmonic impedance termination and bias
points. The analysis for these classes are in frequency domains except for Class-E PA, as will be
shown.
3.2.2.1
Switched-mode Classes
I− Class-E power amplifier
Class-E PA was introduced, first, by N.Sokal [30] then was analysed in detail by Raab [31]. Fig
3.11 presents typical circuit diagram for Class-E PA.
The load network consists of series L0C0 elements, to pass the fundamental components to the
rest of the network, followed by an inductive load impedance to tune out the internal capacitance
(Cds ) switching loss. A Class-E power amplifier satisfies very important conditions for optimum
high efficiency. These conditions are the zero voltage switching and zero derivative switching,
given by
vsw (ωt)|ωt=2π = 0
(3.18)
Vdd
IDC
ZL
C0
id (t)
@ f0
isw (t) iCds (t) +
Cds
vsw (t)
−
L0
jXL
+ io (t)
vo (t)
−
Figure 3.11: Typical circuit of class-E PA.
RL
33
3.2 Power Amplifier Classes
⏐
dvsw (ωt) ⏐⏐
=0
dωt ⏐ωt=2π
(3.19)
From [31] and [32], the output current is:
io (ωt) = Io,max sin(ωt + ϕ)
(3.20)
where Io,max is the amplitude of the output current, and ϕ is the phase shift. Using a 50 %
conduction angle, the normalized voltage and current waveforms are:
{
0
, 0 < ωt < π
vsw (ωt)
[
]
=
(3.21)
3π
π
VDC
π ωt − 2 − 2 cos(ωt) − sin(ωt) , π < ωt < 2π
isw (ωt)
=
IDC
{
π
2 sin(ωt) − cos(ωt) + 1
0
, 0 < ωt < π
, π < ωt < 2π
(3.22)
and the phase angle ϕ is equal to
2
ϕ = arctan(− ) = −32.482◦
π
(3.23)
The normalized voltage and current described in (3.21) and (3.22), respectively, are drawn in
Fig 3.12. In this figure, the drain current id (t) in the cut off-region is shown. This represents the
current passing through the output capacitance Cds .
By differentiating the waveform equations given in (3.21) and (3.22) and setting the results equal
to zero, the maximum voltage and current can be found as:
Vsw max = 3.562VDC
(3.24)
Isw max = 2.8621IDC
(3.25)
and
4
Vsw (t) [V]
vsw (t)
isw (t)
3
3
2
2
1
1
iCds (t)
0
0
-1
isw (t), ICds (t) [A]
4
-1
0
0.5
1
1.5
2
Time [s]
Figure 3.12: Drain current isw (t), Drain Voltage vsw (t) and output capacitance
current iCds (t) of Class-E power amplifier.
34
3. Power Amplifier Operation
The optimum load impedance is
ZL = RL + jXL = RL (1 + j tan 49.052◦ )
(3.26)
XL = RL tan 49.052◦
(3.27)
2
VDC
RL = 0.5768
Pout
(3.28)
which result in
where
A Class-E power amplifier has a limiting operating frequency due to the transistor output capacitance, (Cds ). The maximum operating frequency for Class-E is given by:
fmax =
Isw max
56.5CdsVDC
(3.29)
Another condition for designing a Class-E PA is that the output capacitance of the transistor Cds
must satisfy the relation below:
RL
(3.30)
XCds =
0.1836
Usually, for high output capacitance, an extra shunt capacitance in parallel is needed to satisfy
(3.30). This reduces the maximum operating frequency of a Class-E PA as in (3.29), where Cds
replaced with the total capacitance C. From (3.26) and (3.30) using total capacitance, the load
phase seen by the switch can be derived as follows [32]:
RL
XL
XC
− arctan(
φL = arctan
) = 49.052◦ − 13.109◦ = 35.945◦
X
R
L
L
RL
1− R X
L
(3.31)
C
From (3.31), if the operating frequency is low and the output capacitance C is small, the load
phase seen by the switch is the same as the load impedance in (3.26). Class-E PA equations will
be used later in this thesis for designing a broadband Class-E power amplifier.
II−Class-D power amplifier
Class-D power amplifiers is a family of power amplifier classes that uses two transistors each of
which work in 180◦ out of phase. Usually, Class-D power amplifier refers to the voltage mode
Class-D (VMCD) PA, where the switch (drain) voltage is tuned (by presenting an open circuit
for higher harmonic) to be square waveforms with a sharp rise up and fall down as shown in
Fig. 3.13 and Fig. 3.14.
There is a complementary mode of operations is defined as current mode Class-D (CMCD) PA. It
is mostly referred as Class-D−1 . In this class the current waveform of the transistor is shaped to
form a square shape by presenting a short circuit for even order harmonics. Its circuit is shown
in Fig. 3.15 and its waveforms are exactly as in Fig. 3.14 with reversing the current to voltage
35
3.2 Power Amplifier Classes
Vdd
IDC
Pin
Id2
∠0
Q2
Cds2
+
Vd2
−
C0
Id1
∠ jπ
Q1
Cds1
L0
@ f0
+
Vd1
−
+ Io (t)
Vo RL
−
Figure 3.13: Typical voltage mode Class-D power amplifier circuit.
and vice versa. For several reasons, CMCD PA is widely used in RF applications. It is easier to
eliminate the losses from the output capacitance of the transistors by employing them in the shunt
resonant circuit. The package lead losses, which can be modelled as an inductive loss, become
the major losses. However, it can be negligible if the inductance can be used in the circuit as
part of the matching impedance. Another reason to for choosing of this PA in high frequency
operation is the high output power in this class, which is higher than the output power in Class-E
power amplifiers.
The analysis will be carried for CMCD PA. However, VMCD can be obtained by replacing the
voltage with current and vice versa. Usually, CMCD uses an output BALUN which is not shown
in Fig. 3.15 for simplicity. Furthermore, the single ended impedance is half of the balanced
impedance if the optimum power from each transistor is required in single mode operation. Using
Fourier analysis on the waveforms on Fig. 3.14, we get the half wave rectified sinusoidal signal
4
2
id (t)
1.5
vd (t)
2
1
1
Id [V]
Vd [V]
3
0.5
0
0
0
0.5
1
1.5
2
Time [s]
Figure 3.14: Ideal current and voltage waveforms for Class-D family power
amplifiers.
36
3. Power Amplifier Operation
given by:
∞
2
π
cos(nωt)
vd1 (ωt) = Vdd + Vdd sin(ωt) +Vdd ∑ 2
2
n=2,4... n − 1
(3.32)
∞
π
2
vd2 (ωt) = Vdd − Vdd sin(ωt) −Vdd ∑ 2
cos(nωt)
2
n=2,4... n − 1
(3.33)
It is evident from (3.32) and (3.33), that the voltage contains only even harmonics. These
components have the same magnitude and phase. This means that the push-pull operation
provides an open circuit for even harmonics. The output voltage is the difference between the
voltage on the (3.32) and (3.33), excluding the harmonics components which will be shortened
by the resonant circuits, given by:
Vo = Vd1 −Vd2 = πVDC sin(ωt)
(3.34)
Now the current waveforms can be calculated using the same method previously
∞
4
4
(−1)n
sin(nωt)
Id1 (ωt) = Idd + Idd sin(ωt) − Idd ∑
π
π n=3,5... (n)
(3.35)
∞
4
4
(−1)n
Id2 (ωt) = Idd − Idd sin(ωt) + Idd ∑
sin(nωt)
π
π n=3,5... (n)
(3.36)
It is clear from (3.35) and (3.36) that the harmonic components of the drain currents of both
transistors have the same magnitude and 180◦ . That is, the push-pull operation needs a parallel
LC network tuned at the fundamental to terminate the odd harmonics of the current. The output
current passing through the load resistor is given by:
4
Io = Idd sin(ωt)
π
(3.37)
The following parameters can be derived easily from previous equations
RL =
Po = 2Vdd Idd
π2 Vdd
4 Idd
2
8 2
π2 Vdd
= 2 Idd
RL
=
2 RL
π
PDC = 2Idd Vdd =
2
π2 Vdd
8 2
RL = Po
= 2 Idd
2 RL
π
η=
Po
=1
PDC
(3.38)
(3.39)
(3.40)
(3.41)
Usually a Class-D−1 power amplifier is known to be an ideal case of Class-F−1 power amplifier
operation. This is because the push-pull operation represents the optimum impedance termination
37
3.2 Power Amplifier Classes
Vdd
Vdd
IDC
IDC
Io (t) RL
+ Vo (t) −
@ f0 C0
L0
Pin
Id1 (t)
∠0
Id2 (t)
Q1
Cds1 Cds2
Q2
∠ jπ
Figure 3.15: Schematic diagram for Current mode Class-D power amplifier.
for the harmonics.
3.2.2.2
Harmonically tuned PA
As it was shown previously, a switch mode power amplifier needs a special termination impedance
for the fundamental and harmonic components. This criterion challenges the designs to meet
only one set of impedances, which can never be achieved precisely. This criterion, also, limits the
power amplifier bandwidth. Hence, more relaxed criteria should be introduced to overcome these
limitations. Harmonically tuned power amplifiers give the key solution in these cases.
I−Class-F power amplifier
Figure 3.16 and Fig. 3.17 show typical circuit diagrams for Class-F and Class-F−1 , respectively.
Similar to Class-D PA families, Class-F PA is a complementary class for Class-F−1 PA. This
type of family classes, ideally, requires control of all the harmonics to achieve highly efficient
operation. The optimum impedance for this class is similar to Class-D PA families following
Vdd
IDC
ZL
C3
Pin
id (t)
+ @ f3
Q1 vd (t)
−
L3
@ f0
C0
io (t)
+
L0vo (t) RL
−
Figure 3.16: Typical circuit diagram for A Class F-Power amplifier.
38
3. Power Amplifier Operation
Vdd
IDC
ZL
C2
id (t)
+ @ f2
Q1 vd (t)
−
Pin
L2
@ f0
C0
+ io (t)
RL
v
(t)
L0 o
−
Figure 3.17: Typical circuit diagram for an inverse Class-F-Power amplifier.
(3.42):
ZL_Class−F −1
⎧
⎪
⎨ ZLopt , ωt =Fundamental
=
∞
, ωt =Even Harmonics
⎪
⎩
0
, ωt =Odd Harmonics
(3.42)
However, Class-F and inverse Class-F PA can achieve high efficiency operations by controlling
the limited number of harmonics [33]. Fig. 3.18 [33] presents inverse Class-F PA with controlling
one or two harmonics for even and odd components under Class-B power amplifier bias point.
The theoretical efficiency and output power are shown in Fig. 3.19 for a combination of these
harmonic cases together with ideal an case (infinity controlled harmonics). It can be clearly
observed from this figure that controlling an infinite number of even harmonic components
without any odd harmonic yields to Class-B PA operation efficiency (78.5 %). On the other
hand, controlling infinite odd harmonic components without any even harmonics leads to a state
between a Class-A and Class-B power amplifier with an efficiency of 63.7 %; i.e., Class-AB PA
with a 252◦ conduction angle. Thus, Class-F PA can reproduce classical classes’ efficiency by
mixing the controlled harmonics in even and odd mode.
In [34], the author shows the possibilities to increase the efficiency and the output power capability
3
3
2
1
1
0
0
-1
id (t) [A]
vd (t) [V]
vsw (t)
isw (t)
2
-1
0
0,5
1
1,5
2
Time [s]
Figure 3.18: Ideal current and voltage waveforms for inverse Class-F powers
amplifier, for up to two/three controlled harmonics for even/odd components
(dotted) and for up to four/five controlled harmonics for even/odd components
(solid).
39
3.2 Power Amplifier Classes
120
η [%]
100
0.15
Pout, c
m=∞
80
0.1
60
0.05
η
Pout Capability
0.2
m=1
40
0
0
2
4
∞
Odd Harmonics
Figure 3.19: Efficiency and output power capability for maximum flat Class-F
power amplifier with different odd and even components combination
in Class-F PA using different harmonics’ components. It is shown that by changing the third
harmonic value, the resultant efficiency and output power capability increase 6-8 % of the those of
maximally flat Class-F PA. In [35], it was shown that inverse Class-F PA has superior performance
over Class-F PA for higher conduction angle operations. This is because the fundamental current
increases faster than the DC-component increment in this region [35].
II−Mixed mode classes
Mixed-mode power amplifiers refer to a family of classes that combine two or more of power
amplifier classes discussed earlier. In [36], [25] and [37], a detailed discussion of these kinds of
mixed mode/harmonically tuned power amplifiers is presented. Combination of Class-F PA and
Class-E PA with different controlled harmonics is presented theoretically in [36]. It is shown that
controlling the harmonics, by very low/high impedance, as in Class-F PA with presenting the
fundamental optimum impedance for Class-E PA leads to high efficiency operation. This results
from the optimum ZVS (Zero Voltage Switching).
In [25], the author presents the optimum fundamental load impedance and the voltage components
for second/third and both harmonics in an analytical approach. Giving the drain voltage as:
Vd (ωt) = Vdd −V1,HT cos(ωt) −V2,HT cos(2ωt) −V3,HT cos(3ωt)
(3.43)
The voltage gain (δHT ) is the ratio of the fundamental voltage component in the harmonic tuned
case to the voltage of the classical classes. On the other hand, the voltage gain (αHT ) factor is the
ratio of the harmonic voltage component to the fundamental voltage component in harmonically
tuned case. Both can be defined as:
V1,HT
δHT =
(3.44)
V1,T L
and
αn,HT =
Vn,HT
V1,HT
(3.45)
where Vn,HT is the nth voltage component for the harmonic tuned PA and V1,T L is the fundamental
40
3. Power Amplifier Operation
voltage component for classical classes (tuned load) in (3.11).
As a result, the design parameters in relation with the tuned load case in (3.14)-(3.17) is given by:
1 − cos ϕ2
ϕ − sin ϕ
(3.46)
I1V1 PoA ϕ − sin ϕ
=
2
π 1 − cos ϕ2
(3.47)
Po
ϕ − sin ϕ
= ηA
PDC
2 sin ϕ2 − ϕ cos ϕ2
(3.48)
RL,HT (ϕ) = δHT RL,T L (ϕ) = πRLA
Pout,HT (ϕ) = δHT Pout,T L (ϕ) = δHT
ηHT (ϕ) = δHT ηT L (ϕ) = δHT
PDC,HT (ϕ) = PDC,T L (ϕ) = Idd Vdd
ϕ
ϕ
PDCA 2 sin 2 − ϕ cos 2
=
π
1 − cos ϕ2
(3.49)
It is clearly observed that all the design equations for HTPA, except the DC-power equation, are
based on the voltage harmonic tuning's (HT) gain , δHT .
Optimum harmonic components for these classes are shown in Table 3.2. The maximum output
power and drain efficiency is shown in Fig. 3.20. In this figure, the maximum efficiency exceeds
the 100 % limit, which is not feasible. The vertical lines in Fig 3.20 represents the starting limits
of the conduction angle for HTPA cases to achieve a feasible efficiency value. However, in [25],
there is another region for the optimum conduction angle resulted from the current limitation to
achieve perfect voltage waveforms, which reduces the limits on Fig. 3.20.
In [21] and [37], waveform engineering techniques and continuous mode is introduced to increase
the limit of high efficiency power amplifiers and to give a broader perspective on designing a new
family of PA classes. In [21], based on waveform engineering, a Class-J PA was introduced. This
class is a transition between Class-AB and Class-E PA. It presumes no third harmonic produced
by the transistor. It terminates the third harmonic impedance (and higher harmonic components)
with low impedance. The required impedances for Class-J PA are given by [21]:
Z1,opt =
√
2RL,opt ∠45◦
(3.50)
Table 3.2: Optimum voltage harmonic gain and design factor for Harmonically
Tuned power amplifiers
Power Amplifier Class α2,HT
α3,HT
δHT
Classical Class PA
0
0
1
HT,3rd (Class-F PA)
0
-0.17
1.15
HT,2nd
-0.35
0
1.41
HT,2nd ,3rd
-0.55
0.17
1.62
41
3.3 Efficiency and power limitations in power amplifiers
2.0
HT,2nd ,3rd
Pout [dBm], η[%]
η
HT,2nd ,3rd
1.5
HT,2nd
HT,2nd
HT,3rd
TL
HT,3rd
TL
1.0
Pout
0.5
0
0
π/2
π
3π/2
π
ϕ [rad/s]
Figure 3.20: Output power and efficiency of different combinations of harmonically tuned power amplifier.
3π
RL,opt ∠−90◦
(3.51)
8
where RL,opt is given by (3.13). From [38], Class-J PA is expressed by half-sinusoidal waveforms
with specified phase shifts:
Z2,opt =
1 1
2
Vd (ωt) = πVdd ( − sin(ωt + ψ) − cos(2(ωt + ψ)))
π 2
3π
(3.52)
1 1
2
Id (ωt) = Imax ( + sin(ωt) − cos(2ωt))
(3.53)
π 2
3π
where ψ is the phase angle between the voltage and the current waveforms. It is equal to 45◦
in (3.50) and (3.51). A detailed analysis for this class is presented in [38] and [21]. In [37],
an extension for Class-F and Class-J power amplifiers is presented based on the waveforms
engineering concept by reformulating the voltage equation as:
Vd = (1 − cos(ωt))(1 − ζn sin(nωt)), (−1 < ζ < 1, n = 2, 3, 4, . . . )
(3.54)
Where n represent the harmonic resolution factor. This clever reformulation and the extended
work in [39] give a broader view and explanation of what the PA designers did for the last decades.
Other mixed mode power amplifiers are already in research with more or less dealing with same
concepts discussed here. In this work, there is an extensive study on using and implementing
these concepts of design and PA. However, more practical issues must be discussed before going
to the work of this thesis.
3.3
3.3.1
Efficiency and power limitations in power amplifiers
The knee Effect
In Fig. 3.21, a more realistic I-V curve for FET model is presented. It is shown that the
minimum drain voltage is not zero but a finite voltage, which causes limiting voltage swing on
42
3. Power Amplifier Operation
Id [A]
Imax
A
Idd
Vknee
Vdd
Vd [V ]
Figure 3.21: Typical I-V curve with knee effect
load impedance line. As a result, the power and, consequently, the efficiency reduces to a lower
value. The optimum load line for Class-A PA, shown in Fig. 3.21, can be calculated as shown
previously:
Vdd −Vknee
(3.55)
RL,opt,knee =
2Idd
where Idd , Vdd and Vknee are the drain DC current, drain DC voltage and drain knee voltage. The
output power is:
1
Pout,knee = (Vdd −Vknee )Idd
(3.56)
2
and the DC power delivered to the transistor is:
PDC = Vdd Idd
(3.57)
The drain efficiency is
Pout
1
Vknee
= (1 −
)
(3.58)
PDC 2
Vdd
It is clearly seen from (3.58) that the efficiency reduces linearly with the ratio of knee voltage
to the DC supply voltage. Hence, if the knee voltage is 20 % from the DC-supply voltage, the
resulted drain efficiency is 20 % less than the ideal case. On the other way, the efficiency will
reduce from 50 % to 40 %. From (3.17), the efficiency for the classical classes with the knee
effect can be calculated as:
ηknee =
η(ϕ) =
Pout
1
Vknee
ϕ − sin ϕ
= (1 −
)
PDC 2
Vdd 2 sin ϕ2 − ϕ cos ϕ2
(3.59)
Finding the influences of the parasitic capacitance on the efficiency need a different concept
to be applied because the DC component is difficult to be calculated from the lumped model. The
efficiency can be solved using the dissipated power and the DC power:
η=
Pout
PDC − Pdiss
Pdiss
=
= 1−
PDC
PDC
PDC
(3.60)
43
3.3 Efficiency and power limitations in power amplifiers
In a Class-A power amplifier, the dissipated power for an ideal model and zero knee voltage is:
1
Pdiss,ideal = PDC − Pout = Vdd Idd − Vdd Idd
2
1
1
Vdd Idd = PDC
2
2
=
(3.61)
This power is dissipated in the current source generator in the FET model. It is the minimum
dissipated power in a Class-A power amplifier, and it does not account for the losses from the
parasitics and knee voltage. The dissipated power in a Class-A power amplifier with the knee
voltage effect is:
Pdiss = Pdiss,ideal + Pout,opt − Pout,knee
=
1
1
1
PDC + Vknee Idd = Idd (Vdd +Vknee )
2
2
2
(3.62)
Hence, the efficiency can be calculated by substituting (3.62) in (3.60) resulting in (3.58). In the
same way, the efficiency using the parasitic FET model can be calculated and will be presented in
the next part.
3.3.2
Parasitic effects on gain and power
A basic FET-model is shown in Fig. 3.22. The transistor is modelled as a voltage controlled
current source with a value of gmVgs (t), where gm is the input transconductance and Vgs (t) is the
voltage at the input terminal of the transistor. The parasitics from the semiconductor layers are
represented between the three terminals as capacitance. In Fig 3.22, a signal generator with input
impedance Zin is stimulating the transistor. The output power is terminated in load impedance ZL .
In this circuit, the input power is:
1
Pin = |Iin |2 R{Zin }
2
(3.63)
ZL
Cgd
Iin
Zs
+
Vs (t)
−
ICgd
Id1
Iout
+
Cgs
Vgs (t)
-
+
gmVgs (t)
Cds
Vds
-
Figure 3.22: Circuit model for FET with major parasitic capacitances
ZL
44
3. Power Amplifier Operation
Where the input current can be written as:
Iin = ICgs − ICgd
(3.64)
with
Vgs
XCgs
(3.65)
Vout −Vgs
XCgd
(3.66)
Vds = Vout = Iout ZL
(3.67)
ICgs = j
and
ICgd = j
The output voltage is then:
Substituting (3.66), (3.67) and (3.65) in (3.64), the resulted input current is calculated as:
(
)
XCgs + XCgd
ZL
Iin = j
Vgs − j
Iout
(3.68)
XCgd XCgs
XCgd
From (3.68) it can be seen that the input current is a function of the output voltage (ZL Iout ). The
reason for this is the feedback capacitor Cgd . The output power is calculated using:
1
Pout = |Iout |2 R{Zout }
2
(3.69)
where the output current is:
Iout = −Id − ICgd − ICds = −gmVgs +
Vout −Vgs
Vout
+
jXCgd
jXCds
substituting (3.67) in (3.70) and rearranging the equation, the output current is:
(
)
(−gm XCgd + j)XCds
Vgs = βVgs
Iout =
XCgd XCds + jZL (XCgd + XCds )
Finally, by substituting (3.71) in (3.69) the output power can be rewritten as:
⏐
⏐2
⏐
(−gm XCgd + j)XCds
1 ⏐⏐
⏐ |Vgs |2 R{Zout }
Pout =
2 ⏐ XCgd XCds + jZL (XCgd + XCds ) ⏐
1 2
|β| |Vgs |2 R{Zout }
=
2
From (3.71) and (3.68), the input current can be calculated as:
(
)
XCgs + XCgd − ZL XCgs β
Iin = j
Vgs = jγVgs
XCgd XCgs
(3.70)
(3.71)
(3.72)
(3.73)
45
3.3 Efficiency and power limitations in power amplifiers
Hence, the input power is:
Pin
⏐
⏐
1 ⏐⏐ XCgs + XCgd − ZL XCgs β ⏐⏐2
2
=
⏐ |Vgs | R{Zin }
2⏐
XCgd XCgs
1 2
|γ| |Vgs |2 R{Zout }
=
2
(3.74)
Simply the power gain can be calculated as:
⏐ ⏐
Pout ⏐⏐ β ⏐⏐2 R{Zout }
Gp =
=⏐ ⏐
Pin
γ R{Zin }
(3.75)
In (3.72) and (3.75), a full capacitance parasitic influence on the output power and gain is shown
respectively. The gain equation in (3.75) is shown over the frequency with different values of
parasitics in Fig. 3.23. The dashed line in these figures represents the unity gain where the
corresponding frequency is the maximum oscillating frequency fmax . The gain in Fig. 3.23.a for
all Cgs have the same value at 2.8 GHz. This is because the load impedance, which is composed
of RL = 1 Ω and LL = 2.696 nH, is equivalent to XCds //XCgd . Sweeping the gate-drain capacitor
have big influence on fmax , Fig. 3.23.b. This figure shows that the gain at small frequencies is
almost identical with all swept values of Cgd . This is logically because the impedance of Cgd at
60
60
Cds = 1.0 pF
Cgd = 0.2 pF
40
Gain [dB]
20
Decreasing Cgs
0
20
Decreasing Cgd
0
-20
-20
0
2
4
6
0
8
2
Freq [GHz]
(a)
4
Freq [GHz]
(b)
60
Cgs = 2.0 pF
Cgd = 0.2 pF
40
Gain [dB]
Gain [dB]
40
Cgs = 2.0 pF
Cds = 1.0 pF
20
Decreasing Cds
0
-20
0
2
4
6
8
Freq [GHz]
(c)
Figure 3.23: Calculated gain from (3.75) over the frequency with a) Cgs of a
range between 2 pF and 10 pF in 0.2 pF steps, b) Cgd of a range between 0.1 pF
and 1.3 pF in 0.3 pF steps, and c) a) Cds of a range between 1 pF and 10 pF in
2 pF steps; gm = 0.525 S, RL = 1 Ω and LL = 2.696 nH.
6
8
46
3. Power Amplifier Operation
fmax [GHz]
8
6
Cgs
4
Cds
2
Cgd
0
0
5
10
15
Cxy [pF]
Figure 3.24: fmax for different parasitic values obtained from each diagram
in Fig. 3.23 crossing the unity power gain (zero in dB). For each graph in the
diagram, the other capacitance values are kept similar to Fig. 3.23.
these frequencies has a large value which eliminates the feedback effect. This is also valid for
sweeping Cds , Fig. 3.23.c.
The maximum frequency ( fmax ) is shown in Fig. 3.24, which are calculated from Fig. 3.23. It
is shown that the Cgd has a major influence on fmax because it presents the effects of the output
capacitance (Cds ) on fmax .
The output power and gain equations require a tedious calculation and simplification to
represent a useful meaning. In the following sections, an individual influence from Cgs and Cds
will be presented and discussed in terms of power, gain and efficiency.
3.3.2.1 Cgs influence on power, gain and efficiency
Solving the limit of β and γ in (3.71) and in (3.73), for Cds and Cgd approaching zero will result
in βCgs and γCgs as:
lim
lim β = βCgs = −gm
XCds →∞ XCgd →∞
lim
lim γ = γCgs = − j
XCds →∞ XCgd →∞
1
XCgs
= ωCgs
(3.76)
(3.77)
Substituting (3.76) and (3.77) in (3.72) and in (3.75), the output power and gain are:
1
Pout = g2m |Vgs |2 R{Zout }
2
Gp =
g2m R{Zout }
2 R{Z }
ω2Cgs
in
(3.78)
(3.79)
3.3 Efficiency and power limitations in power amplifiers
47
To calculate the drain efficiency, the dissipated power must first be found. The dissipated power
can be calculated from (3.78) and (3.61):
Pdiss = Pdiss,ideal + Pout,opt − Pout,lossy
=
1
1
PDC + g2m |Vgs |2 R{Zout,opt }
2
2
−
1 2
g |Vgs |2 R{Zout,lossy }
2 m
(3.80)
In (3.80) Zout,opt and Zout,lossy are the optimum load impedance without knee voltage and parasitic
effect and the load impedance with knee voltage and parasitic effect, respectively. Zout,opt is given
by (3.1). On the other hand, Zout,lossy with the presence of Cgs and knee voltage is given in (3.55).
Thus, (3.80) reduces to:
Pdiss =
=
1
1
1 VDC Vknee
PDC + g2m |Vgs |2
[
]
2
2
2 IDC VDC
Vknee
1
PDC + Pout,opt [
]
2
VDC
(3.81)
The efficiency is then:
1
Vknee
η = (1 −
)
(3.82)
2
VDC
This result is expected because (Cgs has no effect on the efficiency and power as discussed
before. This result concludes that Cgs does not have influence on the output power and efficiency.
However, Cgs is important to give a finite gain. On the contrary, for very low frequencies the
gain is very high, which is a major reason to make the transistor oscillate on these frequencies.
Usually, the stability circuit is designed at the gate side to reduce this gain. In the next section
Cgs will always be present in the analysis.
3.3.2.2 Cds influence on power, gain and efficiency
Assuming Cgd is zero and solving β and γ yielding βCds and γCds :
lim β = βCds =
XCgd →∞
lim γ = γCds = − j
XCgd →∞
−gm XCds
XCds + jZL
1
XCgs
= − jωCgs
As a result, the output power and the gain can be obtained as:
⏐
⏐
1 ⏐⏐ gm XCds ⏐⏐2
Pout = ⏐
|Vgs |2 R{Zout }
⏐
2 XCds + jZL
(3.83)
(3.84)
(3.85)
48
3. Power Amplifier Operation
⏐
⏐
⏐ gm XCds XCgs ⏐2 R{Zout }
⏐
⏐
Gp = ⏐
(3.86)
XCds + jZL ⏐ R{Zin }
It can be easily seen that the maximum power will be reached, in an ideal case, when Cds is zero,
which will give the same result as in (3.56). Another possible maximum is when the imaginary
impedance part in the load is equal to the conjugate of the impedance in Cds . The latter case is
called a conjugate match, where the output power and, hence, the gain are:
Pout =
1
1
g2m
|Vgs |2
2
2 R{Zout } ω2Cds
g2m
1
Gp =
2 C2
R{Zout }R{Zin } ω4Cds
gs
(3.87)
(3.88)
In this case, the output power and gain are reduced from the optimum case in (3.78) by a factor
of (XCds /R{Zout })2 . This factor is equal to the square of quality factor Q, which represents the
switching loss of the Cds . Due to the large output capacitance in the FET transistor (Cds ), the
accounted loss, in addition to the operating frequency, are the major limiting factors on efficiency
and power.
The dissipated power for a Class-A power amplifier with all parasitics, including Cds , and
knee voltage is equal to:
1
Vknee
Pdiss = PDC + Pout,opt [1 − ξ(1 −
)]
2
VDC
(3.89)
2
XCds
ξCds = |βCds | =
|ZL − jXCds |2
(3.90)
where
2
The efficiency is then:
1
Vknee
)
η = ξCds (1 −
2
VDC
There are two cases for the efficiency presented in (3.91)
(3.91)
Cds = 0⇒ ξ = 1 and hence the efficiency reduces to (3.58)
Cds ̸= 0: In this case, usually the load impedance is designed to get the maximum output power
from the transistor. According to (3.85), the output impedance should absorb the output capacitance, i.e.; Im{ZL } = XCds . Hence,
ξCds_opt =
1
2 Re{Z }2
ω2Cds
L
(3.92)
and the efficiency is:
η=
1
1
Vknee
(1 −
)
2
2
2
2 ω Cds Re{ZL }
VDC
(3.93)
3.3 Efficiency and power limitations in power amplifiers
49
where
1 VDC −Vknee
Re{ZL } = RLopt,lossy = (
)
(3.94)
2
IDC
As it was shown before, the switching loss due to Cds limits the efficiency of the power amplifier.
In addition, the efficiency decreases as the frequency increases, which makes highly efficient
power amplifier designs at high frequencies a real challenge.
3.3.2.3 Cgd influence on power, gain and efficiency
Similarly, β and γ with presence of Cgd and Cgs only is given by βCgd and γCgd :
−gm XCgd + j
XCgd + jZL
(3.95)
XCgs + XCgd − ZL XCgs βCgd
XCgd XCgs
(3.96)
lim β = βCgd =
XCds →∞
lim γ = γCgd =
XCds →∞
Pout
⏐
⏐
1 ⏐⏐ gm XCgd − j ⏐⏐2
= ⏐
|Vgs |2 R{Zout }
2 XCgd + jZL ⏐
⏐
⏐
⏐ βCgd ⏐2 R{Zout }
⏐
G p = ⏐⏐
γCgd ⏐ R{Zin }
(3.97)
(3.98)
The efficiency is similar to (3.91) with:
ξCgd
⏐
⏐
⏐ XCgd − j ⏐2
⏐
g
m ⏐
= |βCgd |2 = ⏐
⏐
⏐ ZL − jXCgd ⏐
(3.99)
There are two cases to be considered for the efficiency:
Cgd =0⇒ ξ = 1 and hence the efficiency reduces to (3.58)
Cgd ̸= 0: In this case, obtaining the maximum power from the transistor requires the load impedance to absorb the output capacitance (3.97), i.e.; Im{ZL } = XCds . Hence,
ξCgd_opt =
2
g2m + ω2Cgd
2 Re{Z }2
g2m ω2Cgd
L
(3.100)
Where Re{ZL } is given similar to (3.94) in addition to the switching loss due to Cgd and the
operating frequency, the input transconductance limits the efficiency of the power amplifier as
concluded in (3.100).
50
3. Power Amplifier Operation
3.3.2.4 Cds and Cgd influence on the efficiency
If all major analysis and knee voltages affect the dissipated power (3.62), the efficiency will be
given as in (3.91). However, ξ will change to take both capacitances in effect as:
⏐2
⏐
⏐
⏐
(XCgd − gjm )XCds
⏐
⏐
ξ=⏐
⏐
⏐ XCgd XCds + jZL (XCgd + XCds ) ⏐
(3.101)
Ideally, the load impedance should absorb the output parasitics of the transistor to get high output
power and efficiency. In this case XL is equal to |XCds //XCgd |. Hence, (3.101) will be:
ξopt
⏐
⏐
2 )
(g2m − ω2Cgd
1 ⏐⏐ (gm XCgd − j)XCds ⏐⏐2
1
= 2 ⏐
=
⏐
2 C2 Re{Z }2
gm
Re{ZL }
g2m ω4Cds
L
gd
(3.102)
From (3.102), efficiency of power amplifier changes with transconductance of the FET due to the
feedback capacitance between the output and the input terminals of the FET (Cgd ). On the other
hand, the efficiency here decreases rapidly with frequency due to the two frequency dependent
impedances |XCds //XCgd |.
The drain efficiency factor is shown over the frequency with sweeping Cgd and Cds in
Fig. 3.25.a and Fig. 3.25.b, respectively. From these figures, it is worth noting that the efficiency
factor is only valid if it is below one. However, the graph in Fig. 3.25 gives an overview of
parasitic influence on the drain efficiency.
All these analysis are made by assuming a linear capacitance model. However, very complicated equations can be obtained if the dependent voltage relation of the parasitics (gm , Cgs , Cds
and Cgd ) is substituted in the previous analysis.
1
1
Cds = 1.0 pF
0.8
Cgd = 0.2 pF
0.8
ξ
0.6
ξ
0.6
Decreasing Cgd
Decreasing Cds
0.4
0.4
0.2
0.2
0
0
0
2
4
Freq [GHz]
(a)
6
8
0
2
4
Freq [GHz]
(b)
Figure 3.25: Calculated efficiency factor from (3.102) over the frequency with
a) Cgd of a range between 0.1 pF and 1.3 pF in 0.3 pF steps, and b) Cds of
a range between 1 pF and 10 pF in 2 pF steps; gm = 0.525 S, RL = 1 Ω and
LL = 2.696 nH.
6
8
4|
Single Band Power Amplifiers
To investigate highly efficient broadband power amplifiers, narrow band amplifiers with very high
efficiency are designed and analysed. In this chapter, these amplifiers are discussed in terms of
design, efficiency, power capability and broadband operation. The power amplifiers are based
on [Paper D] and [Paper E].
The first section will present an inverse Class-D power amplifier. The design technique and
its result are shown. In the second section, an inverse Class-F power amplifier is presented
with a novel matching network integrated with the required resonator. Finally, the last section
will discuss power amplifier classes capabilities for broadband applications based on theoretical
analysis.
4.1
Inverse Class-D PA
The various Class-D power amplifiers, as discussed previously, have different advantages. For
instance, VMCD PA operate on lower peak voltage (Vd,max = 2Vdd ). On the other hand, CMCDPA have very high peak drain voltage (Vd,max = πVdd ). This might make the transistor exceed the
breakdown region and, hence, cause transistor damage. However, for current transistor technology
e.g., GaN HEMT, peak drain voltage has minimal concerns in PA design.
Inverse Class-D PA might include the output capacitance of the transistor in the main resonator.
As a result, low switching loss is achieved. This makes inverse Class-D more preferable for high
frequency power amplifiers.
4.1.1
Design of CMCD PA
The goal of this PA is to get the maximum possible efficiency from two 30 W GaN-HEMT
transistors provided from Eudyna (currently SUMITOMO) EGNB030MK [40]. The PA should
work for the UMTS band (i.e.; 2.14 GHz). The operating bandwidth is not an important issue
at this stage as said before. The design bias point of this amplifier is 800 mA at 50 V operating
voltage.
52
4. Single Band Power Amplifiers
Matching
Network
Matching
Network
Large
Capacitor
Q1
Q2
Gap
Capacitor
Narrow DC-feed
Vdd
Vdd
Figure 4.1: Designed Resonant Circuit utilizing the DC-feed as parallel inductor.
CMCD PA operating at high frequency and high output power requires a careful design for
the resonator and the balun. The circulating current in the resonator is usually higher than the
output current (i.e.; from the simulation ICres = 3.5 A while the output current is 1.3 A). At high
frequencies and high output power, small values for the capacitor and the inductor with high
quality factors are required to design good CMCD PA. Moreover, the resonator should be very
close to the capacitor die to reduce the losses by minimizing any extra parasitic connections.
Furthermore, it will make the output capacitance of the transistor (i.e.; Cds ) easier to be tuned out
in the design.
The designed resonator uses the inductance of the microstrip DC-feed as part of the resonator,
which reduces the loss compared to a conventional inductor. Fig. 4.1 shows the schematic of the
designed circuit. The narrow DC-feeds produce small inductance parallel to the resonator; hence,
a large capacitance is used to achieve a resonance at the fundamental frequency. Moreover, the
capacitance value for the high frequency is sensitive. Hence, a microstrip gap is added in parallel
Ideal
Designed
Freq.
Fund. Freq.
Impedance
+
Port 1
+
L
−
Port 2
C
−
(a)
(b)
Figure 4.2: a) Ideal Parallel LC resonant circuit presented to ideal CMCD
PA, and b) Impedance resulted from the designed resonator (red) and from the
ideal parallel LC circuit (blue). The small circles represent the the operating
frequency (2.14 GHz)
53
BALUN Side
Transistor Side
4.1 Inverse Class-D PA
Figure 4.3: Designed single stub output matching network for CMCD PA.
to increase the total capacitance that is required for the resonator.
To verify that the resonator presents an open circuit impedance at fundamental frequency and
a short circuit impedance for all other harmonics, a large signal simulation is done on the die
model to extract and model the output capacitance (i. e.; Cds ). The modelled capacitance was
used with the package parasitics and the designed resonator as shown in Fig. 4.1. The result is
compared with the ideal resonator shown in Fig. 4.2.a.
The reflection coefficient for the simulation is shown in Fig. 4.2.b. The proposed resonator
topology has zero impedances for the harmonics which indicates that it will work well for the
odd harmonics as required for CMCD PA. However, a matching network for the fundamental
frequency is required to transform the 50 Ω load impedance to the optimum fundamental PA load
impedance. As a conclusion, the designed resonator is comparable with the ideal LC parallel
circuit.
It is worth noting that the even harmonic impedances required for CMCD PA is obtained
by the nature of the push-pull operation as described earlier in Chapter 3. The output matching
network required to transform the optimum load impedance to a 50 Ω was designed using a single
stub matching network for each transistor and then fed to the balun as shown in Fig. 4.3. The
input and output baluns are constructed using low loss λ/4 transmission lines together with 90◦
hybrids from Anaren (XC2100A-03S) [41] at the input and output side of the complete power
amplifier. Fig. 4.4 shows the fabricated PA using a Rogers substrate with εr =3.38 and thickness
of 0.51 mm.
Vdd1
Input
Output
Vdd2
Figure 4.4: Photo of the fabricated CMCD power amplifier using 30 W GaN
HEMT from Eudyna.
54
4. Single Band Power Amplifiers
200
1.5
1.0
Vd
Id
100
0.5
50
0.0
Id [A]
Vd [V]
150
Discharging output
capacitance
0
-.5
0
0.2
0.4
0.6
0.8
1.0
Time [nS]
Figure 4.5: Simulation results of time domain voltage and current waveforms
for the designed CMCD PA taken without de-embedding output die parasitics.
4.1.2
Results of the Designed CMCD PA
Fig 4.5 presents the simulated current and voltage waveforms for the designed CMCD PA. It
is clear from this figure that the current and the voltage waveform resembles a square and half
sinusoid shape, respectively. This ensures that the operation of this class satisfies the condition of
CMCD PA. The reason of the voltage and current waveforms overlapping in Fig. 4.5 is that the
reference level of this result was taken on the die model in ADS simulation. This means that the
external parasitics of the die model (e.g.; Cds , die pad model, etc. . . ) is not de-embedded in this
result. In the off-region, the drain current is negative and the slop is also negative, which means
that the output capacitance is discharging into the load.
4.1.2.1
Small Signal Measurements
The small signal (SS) parameters for this amplifier are measured with a vector network analyser.
The simulated (solid) and measured (symbol) results are shown in Fig. 4.6. It is vividly observed
that a close fit between simulated and measurement results are achieved for the small signal
10
0
40
40
S21 meas
S21 sim
-10
S11−sim
S11−meas
S22−sim
S22−meas
0
-20
-5
-10
0
1
2
f[GHz]
(a)
3
4
5
S22 [dB]
S21 [dB]
S11 [dB]
5
20
20
0
0
-30
-20
-40
-40
-20
-40
0
1
2
3
f[GHz]
(b)
Figure 4.6: Simulation (solid) and Measured (symbol) for the a) insertion loss
and b) small signal gain of the designed PA
4
55
4.1 Inverse Class-D PA
PS
Ref. 1: of input power
Ref. 2: of output power
Pdc
DUT
SG
50Ω
PM/SA
50Ω
PM/SA
Figure 4.7: Large signal measurement setup used in to measure the designed
PA in this thesis.
performance. However, the measured output reflection coefficient (S22 ) has a smaller matchbandwidth compared to the simulation. The input and output reflection coefficients (S11 and S22 )
in Fig. 4.6.a are lower than 10 dB for the operating frequency (i.e; 2.14 GHz). The measured
small signal gain is 15.4 dB at the operating frequency, which is lower than the simulated data
(i.e.; 16.9 dB).
4.1.2.2
Large Signal Measurements
To measure the power amplifier performances (e.g.; output power, gain and efficiency) accurately,
a very good automated measurement system is developed at the department. The measurement
system, shown in Fig. 4.7, consists of a signal generator (SG) stimulating the driver amplifier
with a sufficient signal. The driver signal is fed into a directional coupler with a known coupling
parameter. The rest of the signal, which is the largest amount of the incident power (i.e., for
20 dB coupling and negligible directivity, the output power is 99 % of the incident power), is
injected into the isolator then to the DUT-PA. The resulted output power is fed again into another
directional coupler and then to a load.
50
Pout
40
40
Pout−meas
Pout−meas
Gainmeas
Gainsim
30
GP
20
30
20
10
10
0
0
10
20
30
Pin [dBm]
(a)
40
PA Efficiency [%]
Pout [dBm], Gain [dB]
50
80
80
60
60
40
40
ηsim
PAEsim
ηsim
PAEmeas
20
0
20
0
10
20
30
Pin [dBm]
(b)
Figure 4.8: Simulation (solid) and Measured (symbol) for the a) output power
and power gain, and b) efficiency (drain and PAE) of the designed PA at the
designed frequency, i.e.; 2.14 GHz
40
56
PA Efficiency [%]
4. Single Band Power Amplifiers
60
PAE @3 dB OPBO
40
ηsim
PAEsim
ηsim
PAEmeas
20
0
25
30
35
40
45
50
Pout [dBm]
Figure 4.9: Efficiency performance versus output power showing more than
50 % PAE at 3 dB OPBO at the designed frequency, i.e.; 2.14 GHz.
The input power is measured at the coupling port of the first coupler and multiplied with a
factor to correct the losses from the coupling and the main path until the DUT-PA. The output
power is measured in the same manner. The DC power is measured from the power supply to
calculate the efficiency.
The simulated and measured output power and the power gain over the input power are shown
in Fig. 4.8.a. The output power achieves a maximum of 50 W at 33 dBm input power, while the
1 dB compression point is 14.3 dB.
On the other hand, the drain efficiency and power added efficiency is shown in Fig. 4.8.b.
The peak drain efficiency is 62.7 % (simulated; 66.8 %) and the peak power added efficiency is
60.3 % (simulated; 64.0 %). both simulation and measurement show good agreement.
It is worth noting here that the amplifier (i.e., SMPA) is working as normal Class-AB PA for
low drive power, which produces low efficiency. For high drive power, the output non-linear
parasitics reach to a value that resonate with the external circuit. In this stage, the PA is working
as SMPA, if designed correctly, and produce high efficiency near the compression point i.e.,
usually ±3 dB. from the compression point.
The efficiency is shown versus the output power in Fig. 4.9. It is shown that in 3 dB back-off
from the output power (OPBO),i.e., 44 dBm at Pin = 30 dBm, the drain efficiency is kept more
than 55.0 % while the power added efficiency is more than 52.5 %. This is a good value for a
GSM system that has a power control.
4.2
Inverse Class-F PA
A typical circuit diagram for Class-F and Class-F−1 PA is shown and discussed in Section 3.2.2.
Class-F−1 has a remarkable advantage over other classes because the high peak voltage can give
higher output power [35]. This is the reason of choosing this class in this stage.
57
4.2 Inverse Class-F PA
ZL
TL1 = 0.10λ2
TL3 = 0.20λ4
TL5 = 0.30λ2
Q1
Out
TL2 = 0.25λ3
TL6 = λ2
TL4 = 0.40λ4
Figure 4.10: Typical voltage mode Class-D power amplifier circuit.
4.2.1
Design of Inverse Class-F PA
The main goal of this design is to achieve the maximum efficiency delivering a 45 W output power
with operating frequency of 2.45 GHz, i.e., ISM band. Using the transistor large signal model for
EGNB045MK provided by Eudyna (currently SUMITOMO), source/load pull simulation (i.e.;
for the fundamental) is used to extract the optimum source and load impedances for maximum
output power and power added efficiency (PAE). During the simulation, the harmonic impedances
were terminated with proper impedance for Class-F−1 PA. The simulation is based on Advanced
Design System (ADS) from Agilent.
The output matching network was designed using open stubs and transmission lines, which
also tune the required harmonic termination up to the fourth harmonic. The output matching
network and harmonics’ termination circuit topology are shown in Fig. 4.10. In this circuit, TL2
provides a short circuit for the third harmonic (i.e.; TL2 =0.25 λ3 f0 ). The section composed of
TL4 (TL4 =0.40 λ4 f0 ) and TL3 (TL3 = 0.20 λ4 f0 ) provides an open circuit for the fourth harmonic.
Additionally, the section composed of TL6 (TL6 = λ2 ), TL5 (TL5 = 0.30 λ2 ) and TL3 (TL3 = 0.10
λ2 ) provides an open circuit for the second harmonic. Finally, all transmission line lengths and
widths can be optimized to get an optimum harmonics’ termination and optimum fundamental
load impedance (i. e., for this design the required impedance was 6.80 + j15.00 Ω). From the
Fund.
H3
H2
H4
Figure 4.11: Load impedance of the output matching network integrated with
resonator for the designed Class-F−1 power amplifier shown in Fig. 4.10.
58
4. Single Band Power Amplifiers
Table 4.1: Results of Harmonic Impedances Obtained from the Proposed Topology in Fig.4.10. The symbols are defined in Fig. 4.11
Marker
Frequency [GHz]
Impedance [Ω]
2.45
4.90
7.35
9.80
6.10 + j15.30
397.20 + j430.80
2.60 + j7.80
132.30 − j10.10
Fund
H2
H3
H4
previous design consideration and circuit, Fig. 4.11 shows the optimum load impedance and
harmonic terminations. Table. 4.1. depicts the corresponding markers in Fig. 4.11.
4.2.2
Large Signal Performance
The PA was designed using the same Rogers substrate used for CMCD PA design. CW large
signal measurements are performed using the frequency (Fig. 4.12.a). The stimulating signal was
swept with ±100 MHz from the designed centre frequency. From Fig. 4.12.a, it is observed that
the designed power amplifier has better performances with an offset of 100 MHz. Hence, the
measurements were performed at 2.35 GHz instead of 2.45 GHz.
An output power of 40 W (46 dBm) was achieved at the 1 dB power compression point,
with a power gain of 10 dB. Furthermore, a peak drain efficiency of 60.8 % (PAE =55.7 %) is
measured at the same drive point, as shown in Fig. 4.12.b. These measurements were taken at the
same design point, i.e., Vd = 50 V and Id = 1.2 A.
Further measurements were taken with supply voltage, i.e., Vd , sweep from 34 V to 48 V,
Fig. 4.13. In this measurement, the efficiency is kept within 4 % of the maximum drain efficiency
(i.e.; 59.0 % < η < 62.8 %). Moreover, The output power is found to be within 2.3 dB of the
40
80
Gain
η
PAE
Pout
30
60
20
40
10
20
0
0
2.360
2.380
2.400
2.420
2.440
2.460
50
100
80
@ f = 2.35 GHz
40
60
30
40
Gain
η
PAE
Pout
20
10
15
20
25
30
Freq [GHz]
Pin [dBm]
(a)
(b)
Figure 4.12: Measured (symbol) result for the output power, power gain and
efficiency versus a) frequency and b) input power for the designed Class-F−1
PA.
35
20
0
40
Efficiency [%]
@Pin = 36 dBm
Efficiency [%]
Pout [dBm], Gain [dB]
Pout [dBm], Gain [dB]
50
59
50
100
40
80
30
60
Gain
η
PAE
Pout
20
10
40
Efficiency [%]
Po ut [dBm], Gain [dB]
4.3 Power Amplifier Classes for Broadband Operation
20
@ f = 2.35 GHz
0
30
35
40
Vdd [V]
0
50
45
Figure 4.13: output power, power gain and efficiency over the drain supply
voltage for designed Class-F−1 PA at 2.35 GHz operating frequency.
1dB compression point (i.e.; 43.7 dBm < Pout < 46.0 dBm). The power gain over this voltage
sweep is more than 9 dB. This type of measurement shows that this device is suitable for envelope
elimination and restoration (EER)/envelope tracking (ET) techniques [42–45] applications.
4.3
Power Amplifier Classes for Broadband Operation
In this chapter, two narrow band SMPAs were designed and measured. However, broadband
highly efficient PA is the major goal for this research. A very general condition of SMPA is to
make non-overlapped signal’s harmonics as shown in Fig. 4.14. If the power amplifier design
tunes up to the n−th maximum harmonic, then (4.1) must be satisfied:
n f1 > (n − 1) f2
(4.1)
where f1 and f2 are the lower and the upper edge of the targeted band.
PSD [dBm]
Hence, for ideal case, i.e., infinitely controlled harmonic, f1 must be equal to f2 . This is
the case for single band power amplifiers. As described in Section 3.2.2, Class-F/F−1 requires
different termination for odd and even harmonics. To design Class-F/F−1 with three harmonic
terminations (4.1) becomes:
2
f1 > f2
(4.2)
3
BW
2BW
3BW
f1
f2
2 f1
2 f2
3 f1
3 f2
Freq.
Figure 4.14: Fundamental and harmonic spectral density for an arbitrary signal
with a certain bandwidth.
60
4. Single Band Power Amplifiers
On the other hand, a Class-E PA has a more relaxed condition since it requires one termination
for all harmonics. This makes the harmonics overlapping of the frequencies inside the targeted
band not of any importance. Hence, designing broadband Class-E PA requires that:
f1 >
1
f2
2
(4.3)
The Bandwidth and centre frequency are defined as:
BW = f2 − f1
(4.4)
f2 + f1
(4.5)
2
Another factor which gives a better meaning for the bandwidth and centre frequency is the
bandwidth factor (defined as geometrical bandwidth in filter design). The higher the value of this
factor, the more complex filter design is needed. The bandwidth factor is given by:
f0 =
BW f =
BW
f2 − f1
=2
f0
f2 + f1
(4.6)
Table 4.2 presents the calculated parameters, using the minimum value of the condition (4.1),
for Class-F/F−1 and Class-E PA. It is clearly seen that a Class-E power amplifier has a higher
bandwidth than Class-F/F−1 . This is because the condition (4.1) requires higher value to ensure
the non-overlapping between the second and third harmonic signal.
Table 4.2: Frequency Parameters for Class-F/F−1 and Class-E PA for minimal
Broadband condition value design.
PA Classes
Class-E
Class-F/F−1
Condition (4.1)
BW
f0
BW f
1
f2
2
2
f1 >
3
1
f2
2
1
f2
3
3
f2
4
5
f2
6
2
3
2
5
f1 >
5|
VHF and UHF Broadband PA
The design of highly efficient broadband power amplifiers is discussed in this chapter and the
next. A low frequency broadband power amplifier will be introduced in this chapter. Broadband
matching is defined as designing a lossless reciprocal two port network that can transfer the power
from one side to another (namely from source to load) with minimum loss in a predefined range
of frequencies [46].
The broadband matching problem is classified into three categories [46]:
Resistive Matching: The goal in this problem is to design a matching network that can transfer
the power from a resistive source to a resistive load, Fig 5.1.a. This kind of problem can be
solved using filter matching technique (insertion loss method). The achievable insertion
loss in this method can be zero if an infinite number of reactive elements are used.
Single Matching: In this problem, the source impedance is resistive and the load impedance is
complex, i.e., frequency dependent, Fig. 5.1.b. The achievable insertion loss is not zero
due to the complex impedance which preserves some power.
Double Matching: In this problem, both impedances are complex impedances, Fig. 5.1.c. The
insertion loss is smaller than the one in single matching techniques due to the two complex
impedances of both sides of the network. It usually represents the interstage matching
problem of a cascaded power amplifier.
Most of the power amplifier matching problems encounter the single matching technique. This is
clear because the transistor output impedance can be modelled, in most cases, as an RC network,
where the other side is terminated with 50 Ω. The double matching technique is implemented for
interstage matching network in power amplifiers as both sides have complex impedances.
5.1
Gain-Bandwidth Limit
Bode [47] and later Fano [48] have shown the minimum return loss that can be achieved from a
matching network over a wide frequency range. If the output impedance of the transistor can be
62
5. VHF and UHF Broadband PA
RS
RS
+
+
VS
−
VS
−
RL
MN
ZL
MN
(a)
(b)
ZS
+
VS
−
ZL
MN
(c)
Figure 5.1: Circuit diagrams of broadband matching problems for a) resistive
matching, b)single matching, c) double matching.
modelled as a parallel RC network, Fig. 5.2.a., the reflection coefficient is constructed by solving
the following equation:
⏐
∫ ∞ ⏐⏐
⏐
1
⏐ dω ≤ π
(5.1)
ln ⏐⏐
Γ(ω) ⏐
RC
0
Assuming constant reflection coefficient over the frequency as in Fig. 5.3, equation (5.1)
shows that the minimum return loss, Γm , is limited to the equivalent circuit value within a certain
bandwidth given as (5.2). Outside this bandwidth, the matching network has to give a full
reflection (Γ = 1)
π
πω0
1
≤
=
(5.2)
ln
Γm RC(ω2 − ω1 ) Qc (ω2 − ω1 )
where Qc represents the quality factor of the parallel RC circuit, i.e., Qc = 2π f0 RC
From (5.2) very important facts can be concluded. First, the bandwidth increases at the
expense of a higher reflection coefficient. However, the minimum reflection coefficient can not
be zero unless the bandwidth (ω2 − ω1 ) is zero. Finally, (5.2) can be rewritten as (5.3), which
clearly states that reducing the quality factor of the device output circuit increases the bandwidth
L
Γ
MN
C
R
Γ
(a)
MN
C
(b)
Figure 5.2: Different load problem for Bode-Fano limit with passive lossless
matching network (MN) and a) resistive load and shunt capacitor, b) resistive
load and shunt capacitor series inductor.
R
63
5.1 Gain-Bandwidth Limit
|Γ|
1
Γm
ω1
Freq.
ω2
BW
Figure 5.3: Bode-Fano limit criterion for a constant reflection coefficient.
and hence the reflection coefficient increases.
△f
π
≤
f0
Qc ln( Γ1m )
(5.3)
The bandwidth limit for different reflection coefficients and quality factors is shown in Fig. 5.4.
A more general case, which is very common in PA design, is shown in Fig. 5.2.b. Fano [48]
extended the Bode theorem, including a more general low-pass load equivalent circuit. Usually, a
low-pass to band-pass transformation, i.e., ω → ωx (ω/ωx − ωx /ω) is used [23]. However, this
transformation can not be implemented in the circuit of Fig. 5.2.b because the capacitor can not
be accessed directly from the equivalent circuit terminals. The modified procedure of Fano is
applied for this circuit in [49] using a load resistance equal to 1 Ω. The circuit in Fig. 5.2.b has
two zeros at s = ∞, which produces two equations [48]:
⏐
∫ ∞ ⏐⏐
1 ⏐⏐
π
⏐
ln ⏐ ⏐ dω = (A1 − 2 ∑ λri )
(5.4)
Γm
2
0
⏐ ⏐
⏐ 1 ⏐
π
2
(5.5)
ω2 ln ⏐⏐ ⏐⏐ dω = − (A3 − ∑ λ3ri )
Γm
2
3
0
⏐ ⏐
⏐ ⏐
where A1 and A3 are the Taylor coefficients of ln ⏐ Γ1m ⏐ and equal to C2 and 23 L−3C
, respectively.
LC3
λri = σri + jωri are the zeros of the reflection coefficient of the equivalent circuit and the matching
∫ ∞
1
c
=
0.6
Qc
=5
0
Q
0.4
0
15
=
Q c 200
=
Qc
00
=4
c
Q
=
10
0
△ f / f0
20
Q
c
=
10
0.8
Q
c
0.2
0
0
0.2
0.4
0.6
0.8
1
Γm
Figure 5.4: Fractional bandwidth limit according to Bode-Fano limit with
different reflection coefficient and different quality factor assuming constant
Γm .
64
5. VHF and UHF Broadband PA
L
RS
Γ2
MN
C Γ1
RL
Figure 5.5: Reflection coefficient definition for resistive load network with
shunt capacitor and series inductor including a passive lossless matching network.
network in Fig. 5.5. These zeros lie on the right half plane of the s-plane.
To minimize the reflection coefficient Γm , the matching network must have zeros which
maximize the term Σλ3ri and minimize the term Σλri . This can only be achieved by using single
real zero, i.e., σr [48]. Substituting in (5.4) and eliminating σr will result:
1
ϒ(ω32 − ω31 ) + 3A3 − [(A1 ) − ϒ(ω2 − ω1 )]3 = 0
4
where ϒ =
⏐
⏐
(5.6)
⏐
⏐
2 ⏐ 1 ⏐
π ln ⏐ Γ ⏐.
m
With some mathematical manipulation and substituting A2 and A3 with their values, (5.6)
becomes:
BW f2
24XC2
XC2 12
6XC 2
3
ϒ −
[
+
12
+
]ϒ
−
ϒ +
=0
(5.7)
BW f
BW f2 XC2
XC2
BW f3 XL
where BW f =△ f / f0 is the fractional bandwidth defined as the ratio of the bandwidth to the
centre frequency.
Equation (5.7) is a general case for any matching network, which is called a non-degenerated
case. For the degenerated case, where the matching network is a mirrored of the equivalent load
circuit in which it starts with series L and then shunt C, only (5.4) is then required. (5.4) becomes
identical to (5.2):
2XC
(5.8)
ϒ=
BW f
Equation (5.7) can be solved easily in MATLAB for ϒ and the reflection coefficient |Γm | with the
corresponding loss, 1/(1 − |Γm |2 ). These results are shown with different XC and XL in Fig 5.6
and Fig. 5.7, respectively. In Fig. 5.6, the reflection coefficient is calculated with fixed XL value,
i.e., equal to 2, and different XC values as shown in the figure. Fig. 5.7 shows the same parameters
with XL as variables and XC equal to 2. The dotted line on both figures is a solution for (5.8) with
XC equal to 2. Finally, it is worth to note that these figures are valid for inductance values greater
than a certain level [48]. On the other hand, (5.7) and (5.8) are shown in the figures with unity
resistance RL , but they can be implemented with any value using impedance scaling provided
from (5.9) and (5.10):
ω0 L
XL =
(5.9)
R
65
5.1 Gain-Bandwidth Limit
1
25
16
0.8
20
16
1/[1 − |Γ|2 ]
8
4
0.6
|Γ|
2
1
0.5
0.4
4
10
2
5
0.2
0
0.01
8
15
0.1
1
BW f
(a)
0
0.01
10
1
0.5
0.1
BW f
(b)
1
10
Figure 5.6: Evaluation of Bode-Fano limit for the circuit in Fig. 5.5 with XC as
a parameter and XL = 2 showing a) reflection coefficient and b) return loss from
the reflection coefficient; the dashed line shows the case where the inductor is
not present.
1
ω0CR
where ω0 is the centre radian frequency for the targeted band.
XC =
5.1.1
(5.10)
The Real Frequency Technique
To this point, the discussed matching network technique is implemented via circuit approximation,
which works well for simple load impedance. However, Carlin’s technique [50, 51], which called
as real frequency technique (RFT), utilizes measured data for the required impedances over the
targeted band. Further, it requires rational polynomial function with numerical optimization
to synthesis the a matching network impedance. Finally, extraction of the matching network
elements is the last step in this technique.
1
20
0.8
16
1/[1 − |Γ|2 ]
8
4
0.6
|Γ|
2
1
0.4
0.5
16
8
10
4
2
5
0.2
0
0.01
15
0.1
BW f
(a)
1
10
0
0,01
1
0.5
0,1
BW f
(b)
Figure 5.7: Evaluation of Bode-Fano limit for the circuit in Fig. 5.5 with XL as
a parameter and XC = 2 showing a) reflection coefficient and b) return loss from
the reflection coefficient; the dashed line shows the case where the inductor is
not present.
1
10
66
5.1.2
5. VHF and UHF Broadband PA
Implemented Matching Technique and Design Steps
Several other approaches for broadband matching design and synthesis are presented in [52]. All
of these approaches require numerical technique to give a proper matching network. It includes
optimization needs to be applied that produce final solutions for the required impedance matching
network.
In this work, real frequency techniques are implemented from the extracted optimum load and
source impedances. These impedances are taken from a load/source pull simulation. Inspecting
the required impedance on the Smith chart and applying curve fitting for impedances with
polynomial equations are very important steps. The goal of applying curve fitting is to include
the impedances for those frequencies which are not included in the source/load-pull simulation.
Synthesizing matching networks, using ideal lumped elements, is the major step toward
finalizing the matching network. This step requires deep understanding of the influence of the
lumped elements on the impedance and how they rotate in the Smith chart, Fig. 5.8. The arrows
in this figure represent the increment of the lumped element value, short-stub(SC)/open-stub(OS)
length, transmission lines (TL) and transformer ratio (Tra). It is clearly seen from this figure that
the parallel lumped elements and the stub’s moves along an admittance circle. The transmission
line length rotates the impedance over a constant VSWR as shown.
L
ies shu
ser
nt
SC
se
seri
rie
es T
sR
L
nt
u
sh
ser
ies
C
Matching network topology is constrained by three factors; first, the operating bandwidth that
determines the number of lumped elements. As the bandwidth increases the required number of
lumped elements for matching increases. The second factor is the distance between the stop-band,
i.e., second harmonic, and the pass-band, i.e., fundamental frequencies. This factor mainly
determines the matching topology between low-pass and band-pass. The last factor is the power
amplifier type, which determines the kind of zero transmission in the stop-band. Usually, an
inductor has a zero transmission at infinity. This zero could be an open circuit zero, if connected
rie
par
R
Tra<1 Tra>1
alle
lL
C
O
ser
ies
sC
se
Figure 5.8: Different matching component behaviour in a matching network,
the black dot is the default load impedance and the arrow present the increasing
value/length of the component and transmission line TL.
67
5.2 VHF Broadband Class-E PA
in series, and short circuit zero if connected in parallel. Series LC network gives a pole, if
connected in series, at its resonance given by:
1
ω0 = √
LC
(5.11)
For frequencies below the resonance frequency, Series LC network gives a capacitive impedance. On the other hand, it gives inductive impedance above its resonance. This network can give
zero at its resonance if connected in parallel. Parallel LC network is the complementary network
to the series LC network.
PA design steps are summarized in Fig. 5.9. The first step is defining the goals of the desired
PA. The operating frequency, bandwidth, efficiency, linearity, gain and output power is defined in
this step. Followed by choosing the transistor that simplifies the design to meet the defined goals,
As it is said before, GaN HEMT is the chosen transistor in this work. The third step is to acquire
the initial design values such as input power, bias point and number of frequencies that will be
used in the load/source pull simulation.
The next step is applying load/source-pull simulation for the frequencies defined previously.
Assuming these impedances are uniform over every single frequency, hence, a polynomial
equation that describes the real and the imaginary part of the impedances over the frequency
is produced and used for the next steps. These functions are applied, and the output matching
network is designed using ideal lumped elements as in Fig. 5.8. Then, if the goals are met, a
broadband DC-feed is designed and the output matching network (OMN) is re-optimized. A
stability circuit is included in the last step. After converting the ideal lumped elements (LE) to a
real LE and TL and designing the input matching network (IMN), the total system is re-optimized
to meet the goals of the design.
The final step in simulation is to convert the matching network into the layout, and an electromagnetic (EM) simulation is used to get an accurate result. Manufacturing and measurements are
the final step in the PA design. In most of the cases, a post-tuning is required for the matching
network to get the desired power amplifier performance.
5.2
VHF Broadband Class-E PA
The goal of this amplifier is to have a broadband power amplifier with high efficiency over the
frequency from 225 MHz- 400 MHz. The gain should be at least 15 dB with output power being
50 W, i.e., 47 dBm. It is been said before that Class-E PA is the easiest power amplifier class
that can be implemented in broadband applications. Since the linearity is not a goal for this
design, hence, Class-E PA is chosen in this design. Another reason for choosing Class-E PA is
the fractional BW which is largely to be implemented for other Classes, Table 4.2.
A 45 W GaN HEMT from Eudyna was used for this design. From the data sheet, the
68
5. VHF and UHF Broadband PA
Define goals
Choosing transistor
Start-up values
Applying load/source
pull simulation and
finding ZL ( f ) and ZS ( f )
Designing ideal OMN
no
Goals
met?
yes
Designing broadband DC-feed
Optimizing OMN
and designing
stability circuit
Converting LE
to TL or real LE
and optimization
Designing IMN and
final optimization
no
Goals
met?
yes
Layout and
EM simulation
Goals
met?
no
yes
Manufacturing, measurement and post-tuning
Figure 5.9: Design algorithm for the matching network to design a broadband
highly efficient PA.
69
5.2 VHF Broadband Class-E PA
maximum output power is more than 50 W [53], and the linear gain is 13 dB. However, for low
frequency applications, such as this design, the gain is much higher, see section 3.3. Hence, the
input power is 32 dBm. The chosen bias point for this design is close to the transistor pinch-off
voltage (-2∼-1 V). The reason for this is that the low bias point value produces higher harmonic
components, which result in a high efficiency operation.
5.2.1
Matching Network Design
Load/source-pull simulation is implemented to get the optimum load and source impedances for
the targeted band. This simulation is implemented for each single frequency between 225 MHz
and 400 MHz with 50 MHz step. The load harmonic impedances were terminated with high
impedances, i.e., > 1000 Ω. The harmonic source impedances were ignored during the simulation
as they have a minor effect on the efficiency.
Fig. 5.10 represents the load pull simulation for three frequencies in the target band. This
figure shows the PAE, output power and DC-current contours with 2 %, 0.5 dB and 600 mA
steps, respectively. It is shown in this figure that the optimum impedance contours decrease
with frequency for the PAE and output power. A very interesting result is the current contours
which are never closed its contours. The black dots shown in Fig. 5.10 are the optimum load
impedances used in the design. Those impedances are chosen so that they are near to each other
and can give smooth behaviour over the frequency.
Fig. 5.11 shows the optimum load and source impedances for PA in the targeted band. As it
can be seen from this figure, the optimum load impedance has a constant phase, i.e., ≈ 52◦ , and
its magnitude reduces with the frequency with a constant slope, which follows (5.12):
{
RLopt (1 + j1.28) , @ f = f0
ZLopt =
(5.12)
∞
, @ f = n f0 , n is an integer > 1
where RLopt is the optimum real load impedance. The best function that fits the figure shown in
Fig. 5.11 is a linear function in (5.13):
RLopt = −0.0378 f + 41.1538
(5.13)
The variable f in (5.13) represents the frequency in MHz, in the targeted band.
Those equations are implemented ideally in ADS as a linear impedance function. The result
from the load/source-pull performance is shown in Fig. 5.12, where the PAE exceeds 87 % and
the output power is 47 dBm (50 W) with 14 dB Gain.
Designing the broadband Class-E SMPAs requires a matching network integrated with
the filter that terminates the harmonic with an open impedance. Making a filter that has this
termination is a straight forward procedure, see [23]. However, the source and load impedances
for the filter are 50 Ω. Hence, a matching network that must match the optimum load impedances
70
5. VHF and UHF Broadband PA
PAE
Id0
Id0
PAE
Zopt
Zopt
Pout
Pout
(a)
(b)
PAE
Zopt
Id0
Pout
(c)
Figure 5.10: Load-pull contours for the output power (red) with step 0.5 dB,
drain efficiency (green) with 2 % step and DC current (blue) with 0.6 mA step
for a) 225 MHz, b) 312 MHz and c) 400 MHz. the black dot is the realised load
impedance.
of the transistor to a 50 Ω is required prior to the filter. This matching network should not produce
a short circuit for the harmonics, i.e., without shunt capacitor or shunt series LC network. Fig.
5.13 shows the proposed concept of the circuit topology. From the figure, a bandpass filter is
chosen because it can give better termination, i.e., high impedance, compared to a low pass filter.
The first element in this bandpass filter should be a series LC network connected in series
to give high impedance termination for the harmonics. The matching network can be designed
using a one section ladder network and adding a series inductor as shown in Fig. 5.14.a. This
network avoids the shunt capacitor that can give low impedance for the high frequency (i.e.;
harmonics). The matching network is a high pass network, which passes the high frequency
starting from the fundamental. Also, its first element (i.e.; the inductor) gives high impedance for
the high frequency and its second element (i.e.; the capacitor) gives low impedance for the high
frequency. Fig. 5.14.b shows the synthesis of the matching network after each element in the
matching network. A parallel inductor LM1 moves the output impedance along the admittance
circle toward the upper half of the Smith chart. The series capacitance CM1 moves the resulted
71
5.2 VHF Broadband Class-E PA
20
60
|ZL | [Ω], ∠ZL [◦ ]
|ZS | [Ω], ∠ZS [◦ ]
0
-20
|ZS |
∠ZS
-40
50
|ZL |
∠ZL
40
-60
-80
200
250
300
350
400
450
30
200
250
300
Freq. [MHz]
350
400
450
Freq. [MHz]
(a)
(b)
Figure 5.11: Ideal optimum a) source impedances and b) load impedances over
the entire band according to the load/source-pull simulation.
impedance along the impedance circle toward the lower half of the Smith chart. The last elements
in this matching network moves along the impedance circle to the upper half of the Smith chart,
the brown line in Fig. 5.14.b. With an appropriate filter, the load impedance can be matched over
the frequency completely as with using the bandpass filter. Table 5.1 shows the lumped element
values used in Fig. 5.14.
The filter type is an important issue in this design. As stated previously, a broad-band Class-E
PA requires a constant phase and magnitude of a constant slope (5.12). Hence, a Butterworth filter
was chosen. It is well known that a Butterworth filter has a flat gain and relatively constant phase
compared to other filter types. However, a Class-E PA requires high rejection at the harmonics.
In the targeted band, the first harmonic (i.e.; 450 MHz= 2 × 225 MHz) is very close to the band
edge frequency (i.e.; 400 MHz). A roll-off of 80 dB/decade (i.e.; 4-poles) is implemented. This
should give a better rejection at the second harmonic.
Furthermore, to minimize the insertion loss of the filter, it is designed with 3 dB bandwidth
for the band between 212 MHz and 441 MHz. The circuit topology for the bandpass filter could
be a T or a π network, where T networks behave as an open impedance for the stop-band (i.e.;
100
PAE
η
Pout
Gain
40
95
30
90
20
85
10
200
250
300
350
400
Efficiency [%]
Pout [dBm], Gain [dB]
50
80
450
Freq. [MHz]
Figure 5.12: Ideal performance for the transistor with ideal load/source-pull
impedances; output power (red), gain (blue), drain efficiency (green) and power
added efficiency (black).
72
5. VHF and UHF Broadband PA
Vdd
IDC
Id
+ Io (t)
Vo RL
BPF
OMN
Q
Pin
−
Figure 5.13: Proposed circuit diagram topology consists of output matching
network (OMN) and band-pass filter (BPF).
harmonics) and π networks behave like a short for the stop-band. Therefore, the T network was
chosen to fulfil the design requirements of Class-E PA. The filter can be designed normally using
any CAD tool or by following filter design books as in [23] (5.14)-(5.17).
Lsn =
Vdd
IDC
ZL
Pin
Id
Q
50gn
BW f ω0
(5.14)
ZL
Z1
Z2
Z3
Z f inal
f1
Z1
CM1
Z2
LM2
Z3
BPF
LM1
Z f inal
+ Io (t)
Vo 50Ω
−
(a)
f1
f1 f1
(b)
Figure 5.14: Load matching network synthesize showing a) circuit impedance
network and b) Load impedances for each element in the matching network.
Table 5.1: Ideal lumped element values for the output matching network used
to design broadband VHF PA.
Lumped element
Value
LM1
CM1
LM2
33 nH
3.9 pF
36 nH
73
5.2 VHF Broadband Class-E PA
1
Lsn ω20
(5.15)
gn
50BW f ω0
(5.16)
1
C pn ω20
(5.17)
Csn =
C pn =
L pn =
where Lsn and L pn represent the series and the parallel inductor in the filter, respectively. The
BW f and ω0 are the fractional bandwidth and the geometric centre frequency, they are equal
√
to (ω2 − ω1 )/ω0 and ω1 ω2 , respectively. gn are the element values of the filter for 1 Ω and
1 rad/sec, and n is the number of filter element (i.e.; poles).
Fig. 5.15 shows the filter circuit diagram. It is clearly seen from (5.14)-(5.17) that the lumped
elements in the filter are designed with respect to the geometric centre frequency which is equal to
305.8 MHz for the designed filter. As a result, the optimum output impedances can be translated
into a 50 − jXCF1 ( f0 ) at the geometric centre frequency, Fig. 5.16. The first capacitor element in
the filter, i.e., CF1 , is equal to 10 pF which results into 52 Ω. The result of Fig. 5.16 is shown
in Fig. 5.14.b with Z3 symbol. The final result of the output matching network is shown in
Fig. 5.14.b, represented with the Z f symbol.
5.2.1.1
DC-Feed Design
To this point, the output matching network was designed using ideal lumped elements, and the
input source impedance is implemented using a function that describes it over the bandwidth.
The input and output DC-feed was implemented using ideal high inductance with an ideal shunt
capacitor. The main goal of the DC-feed is to isolate the RF component from the DC source,
which can damage the source. However, DC sources produce low frequencies that might cause a
severe oscillation for the PA. Hence, a broadband DC feed that blocks the RF components, i.e.,
fundamental and harmonics, must give a short circuit for all other frequencies. To make this,
multiple series inductors, having a resonance occurring on the fundamental band, are implemented.
Parallel capacitors with different values are introduced after each inductor, as shown in Fig. 5.17.
In this figure, the doted line is shown here to represent the repetition of the series L parallel Ci .
In most cases, these lumped elements have the same values. In Fig. 5.17, transmission lines are
used at the start and at the end of the inductors. Those transmission lines used as pads for the
CF1 LF1
CF3 LF3
CF5 LF5
+
Port 1
−
CF2 LF2
CF4 LF4
+ Io (t)
Vo 50Ω
−
Figure 5.15: Butterworth bandpass filter used in the matching network of the
designed PA.
74
5. VHF and UHF Broadband PA
Vdd
IDC
CM1
Id
Q
Pin
LM2
Z@ f0 = 50 − jXCF1
LM1
Figure 5.16: Matching network design to include the first series capacitor of
the band-pass filter.
transistor, in addition, can be optimized to shift the resonance frequency to the targeted band.
The first element in the output matching network, shown in Fig. 5.16, is a shunt inductor. This
shunt inductor can be used as part of the DC-feed, i.e., for high frequency. Hence, the ground
path of this inductor LM1 can be presented with a group of shunt capacitors, as in the DC-feed, to
block the DC current from the ground and to give a low impedance for the targeted frequency.
After those parallel capacitors, the DC feed circuit shown in Fig. 5.17, starts from the first pad of
the inductor.
5.2.1.2
Input Matching Network
The total performance is optimized in the targeted band. The input matching network is designed
in two steps. The first step is the stability circuit with the DC-feed network. The final step is to
C3
C2
C1
L
+
+
−
−
Port 1
Port 2
Figure 5.17: Drain and gate DC-feed network used in the PA design including
the bypass capacitors, the dots here represent a multi section of the same DCfeed network.
75
5.2 VHF Broadband Class-E PA
match the source equation to 50 Ω, the generator resistance.
5.2.1.3
Stability Circuit
As discussed before, oscillation suppression techniques are implemented on the input side to
decrease the gain at low frequencies. A series resistance with DC-feed (R1 ) and another series
resistance (R2 ) in series with transistor gate is implemented to reduce the low frequency and high
frequency oscillation, respectively. Another two parallel RC networks are implemented at the
gate side. Usually, the capacitance in this kind of circuit is implemented here in order to pass the
desired signal over the targeted band. This can be implemented using capacitors that have series
resonance on the pass band. In other frequencies, the parallel resistance will be seen by the signal
and, hence, will be attenuated. Finally, a series RC network is implemented parallel to the signal
path which suppresses the extreme low frequency oscillation. Fig. 5.18 represents the stability
matching network used in this design. The values of the stability elements are chosen so that the
transistor is unconditionally stable, and the maximum gain is maximized over the targeted band.
This insures stability of the PA regardless of the external networks and maximum possible gain
from the transistor, see Fig. 5.19.
The input matching network is implemented using a three segment ladder network using L
and C elements. These elements give a flexible control on the input matching network to fit the
desired source impedance shown in Fig. 5.11.b.
5.2.1.4
Realization
An equivalent matching network consisting of a real lumped element, transmission lines and
a short stub is implemented for the final realization. Air Core inductors from coilcraft and
SMD multi layer capacitor from ATC ceramics were used in the final realization. These lumped
Vgg
Igg
R4
+
C2
IMN
R5
Vin
R3
C1
R2
R1
Vdd
IDC
Id
OMN
+
Q1 V
d
−
−
C3
Figure 5.18: The designed PA circuit with the stability circuits.
+ Io (t)
Vo RL
−
76
5. VHF and UHF Broadband PA
80
4
60
Gmax [dB]
5
K
3
2
Kno stab. ckt
Kwith stab. ckt
1
Gmax no stab. ckt
Gmax with stab. ckt
40
20
0
-20
0
0
2
4
6
8
10
0
Freq. [GHz]
(a)
2
4
6
8
10
Freq. [GHz]
(b)
Figure 5.19: Simulation without stability network (solid) and with stability
network (dashed) for a) K-factor and b) maximum gain.
elements must be chosen so they meet the following criteria:
High quality factor: It is also in relation to low series DC resistance. This ensures lower losses
in the operating band.
High resonance frequency: Making the lumped elements to work as they should behave for
high frequencies. This is important to terminate the harmonic as the ideal design.
High power handling capabilities: For an inductor, it is the maximum RMS current value. For
a capacitor, it is usually the maximum voltage difference between the parallel plate.
Transmission lines are introduced here in order to fine-tune the impedances for the input and
output matching network. Usually, the values of the inductors with high quality factors are not
given in the market with high selection flexibility as by the capacitor. Hence, one more pole is
added to the designed filter in the output matching network. One more shunt inductor, between
series CM1 and series LM2 , is also added in the output matching network to give a better flexibility
of fine-tuning the matching network. A further step of optimization was necessary in the final
design to meet the required specifications. Rogers substrate with εr = 3.38 and a thickness of
0.51 mm is used as an implemented PCB for this PA. Fig. 5.20 shows the manufactured PA.
5.2.2
Measurements
The used measurement set-up is the same as in Fig. 4.7. Different measurement classes are
presented in the following sections that verify the design performances.
5.2.2.1
Small Signal Measurements
Small signal gain performance is measured using a signal generator with a very low signal, i.e.,
-20 dBm, over the targeted band. The PA output power was measured using the FSP spectrum
77
5.2 VHF Broadband Class-E PA
Output
Input
Figure 5.20: Photo of the fabricated VHF broad-band Class-E power amplifier
using 45 W GaN HEMT from Eudyna.
analyzer. Fig. 5.21 shows the small signal performance of the PA. The simulated small signal gain
of 20 dB was achieved across the targeted band. The measured small signal gain was 19.4 dB
with 0.63 dB flatness.
The bandpass filter behaviour in the roll-off region is clearly seen in Fig. 5.21. The maximum
simulated small-signal harmonic suppression, i.e., GainSS−max−in−band −GainSS−max−harmonic , is
10.2 dB where the maximum measured harmonic suppression is 6.5 dBc. This difference between
simulation and measurements comes from the difference between the model used for the lumped
elements in the design and real behaviour for these elements. Overall, the simulated gain fits
well with the measured gain. It is worth noting that this harmonic suppression is due to the filter
attenuation in the stop band region.
5.2.2.2
Large Signal Performance and Linearity
The measurements were done over the entire band from 225 MHz to 400 MHz with every 25 MHz
step. A CW signal was used to stimulate the amplifier. Fig. 5.22 shows the measured (symbol) and
the simulated (solid lines) PA performance over the input power sweep for the centre frequency
312 MHz. The measured output power reaches 50 W (47 dBm) at a 2 dB compression point
30
20
GainSS [dB]
13.2 dB
10
9.8 dB
0
-10
-20
-30
100
200
300
400
500
Freq. [MHz]
Figure 5.21: Simulated (solid) and measured (symbol) of the measured small
signal gain using -20 dBm, the dots showing the second harmonic small signal
gain.
78
5. VHF and UHF Broadband PA
(Gain=17.8 dB). The maximum measured drain efficiency is 78.7 %, and maximum measured
PAE 77 %, occurring at 3.5 dB compression point. The maximum measured output power is
60.6 W at this point. The simulated performance of this PA, as shown in Fig. 5.22, is identical to
the measured performance with less than 1 % difference in the efficiency and less than 0.5 dB
difference in Output power and gain.
The power performance versus the frequency is shown in Fig. 5.23. The measurement was
done at 30 dBm (at 2 dB compression power) input power over a wide range of frequency bands,
and it showed that the output power fulfills the requirement (50 W) with ±1 dB flatness over the
entire band. However, in the last 25 MHz band, the output power reduces until it reaches 40 W
at 400 MHz, Fig. 5.23. The measured efficiency is in close approximation with the simulated
results. However, for high frequency the efficiency is higher than the simulation.
5.2.2.3
Harmonic Suppression Measurements
The harmonic powers were measured for the entire band with a 25 MHz step. The minimum
harmonic suppression was 20 dBc at 225 MHz, while it reaches 56 dBc for the second harmonic
at 400 MHz. The third harmonic suppression is between 49 dBc and less than 62 dBc over the
entire band, Fig. 5.24. Using (2.17) the maximum total harmonic distortion was found to be
1.10 % at 225 MHz.
5.2.2.4
Two-Tone Measurements
The linearity was measured for the same frequencies and output power levels used in the previous
measurement. The drive signal has a frequency spacing of 1 MHz. The best IMD3 was -28 dBc
and was measured on 4 dB back off from the 1 dB compression point at 312 MHz operating
frequency, Fig. 5.25.a and Table 5.2.
The output intercept point OIP3 was measured over these frequencies. The best linearity is at
100
40
Efficiency [%]
Pout [dB], Gain [dB]
50
Pout_sim
Pout_meas
G_sim
G_meas
30
20
10
0
80
60
40
η_sim
η_meas
PAE_sim
PAE_meas
20
0
0
10
20
Pin [dBm]
(a)
30
40
0
10
20
Pin [dBm]
(b)
Figure 5.22: Simulated (solid) and measured (symbol) for a) output power (red)
and Gain (blue), and b) drain efficiency (green) and power added efficiency
(black), versus input power with Idq = 115 mA, Vgg = −1.35 V, Vdd = 50 V.
30
40
Pout [dBm], Gain [dB]
50
100
40
80
30
60
20
40
10
Pout_sim
Gainsim
ηsim
Pout_meas
Gainmeas
ηmeas
PAEsim
PAEmeas
Efficiency [%]
79
5.2 VHF Broadband Class-E PA
20
0
0
200
300
400
500
Freq [MHz]
Figure 5.23: Simulated (solid) and measured (symbol) for output power (red)
and Gain (blue), drain efficiency (green) and power added efficiency (black),
versus input power with Idq = 115 mA, Vgg = −1.35 V, Vdd = 50 V.
the centre frequency with OIP3 = 49.5 dBm, Fig. 5.24.b. However, this is not a perfect linear
mode of operation, i.e., 2 dB from the 1 dB compression point, because the amplifier is working
at a low bias point, and it is completely saturated for the sake of the high efficiency requirement.
5.2.2.5
Influence of Vdd on Efficiency and Output Power
Pout [dBm], Harmonic power [dBm]
The output power was measured with different supply voltages and different drive signal levels
for three different frequencies, i.e., 225 MHz, 312 MHz and 400 MHz. If 3 dB degradation from
the maximum output power was chosen as limiting criteria, the optimum usable supply voltage
should be between 42 V and 36 V for the entire band, see Fig 5.25. However, for the lower end
of the band, i.e., 225 MHz, a supply voltage with 28 V still can be used without exceeding the
60
60
40
40
P f und
Pnd
2
Prd
3
20
0
20
0
-20
250
300
350
-20
400
Freq [MHz]
Figure 5.24: Measured fundamental output power (red), second harmonic
power (blue) and third harmonic (green).
80
5. VHF and UHF Broadband PA
-15
50
49
OIP3 [dBm]
IMD3 [dBc]
f =225 MHz
f =312 MHz
f =400 MHz
-20
-25
48
47
46
-30
P1dB-8dB
P1dB-4dB
P1dB
Psat
45
225
312
400
Freq. [MHz]
(b)
Output power [dBm]
(a)
Figure 5.25: Linearity measurement for the amplifier showing a) IMD3 and b)
OIP3 .
limiting criteria.
In addition, drain efficiency is measured similar to the output power described before, see
Fig. 5.25. For 225 MHz, changing the supply voltage has a big influence on the efficiency. For
example, at 30 dBm input power, the efficiency increases with decreasing the supply voltage.
It changes from 79 % to 93 % of drain efficiency, see Fig. 5.26.a. On higher frequency, it is
clearly seen from Fig. 5.26.b and 5.25.c that varying the supply voltage does not have a significant
influence on the drain efficiency especially with high input power.
As a general conclusion, the designed PA can work optimally with 42 V supply voltage
without degrading the performances.
5.2.2.6
PA Reliability
Since the antenna is the next RF component after PA in the transmitter chain, it is very important
to measure the amplifier performances with different load impedances. The measurement set-up
is shown in Fig. 5.27. It consists of VSWR manual tuner from Maury [54] connected to a 50 Ω
coaxial phase shifter (Φ). The other end of the tuner is connected with the output port of the
PA, i.e., 50 Ω plane. The phase shifter is connected to a power meter (PM) for power level
measurements.
Table 5.2: Measured IMD3 for three different frequencies with four output
power levels
IMD3 [dBc]
Ref. back-off
P1dB-8dB
P1dB-4dB
P1dB
Psat
225 MHz
312 MHz
400 MHz
-24.31
-25.23
-26.56
-23.52
-25.81
-28.61
-23.15
-18.96
-22.61
-20.38
-15.68
-16.02
120
50
120
40
100
40
100
80
@ f =225 MHz
20
60
Vdd
Vdd
Vdd
Vdd
10
40
24
26
28
30
80
20
60
Vdd
Vdd
Vdd
Vdd
10
20
22
0
20
32
24
26
Pin [dBm]
(a)
(b)
50
120
40
100
30
80
20
60
Vdd
Vdd
Vdd
Vdd
10
@ f =400 MHz
0
20
= 50V
= 42V
= 36V
= 28V
40
20
22
Pin [dBm]
Pout [dBm]
0
20
= 50V
= 42V
= 36V
= 28V
@ f =312 MHz
30
= 50V
= 42V
= 36V
= 28V
28
30
32
η [%]
30
η [%]
Pout [dBm]
Pout [dBm]
50
η [%]
81
5.2 VHF Broadband Class-E PA
40
20
22
24
26
28
30
32
Pin [dBm]
(c)
Figure 5.26: Output power (red) and drain efficiency (green) with different
biasing voltage values and input power for a) 225 MHz b) 312 MHz and c)
400 MHz.
The measurements were performed at the maximum output power for three different frequencies, i.e., 225 MHz, 312 MHz and 400 MHz. The measurements are shown with dashed line for
the output power and drain efficiency in Fig. 5.28 and Fig. 5.29, respectively.
The maximum output power for the maximum, middle and high frequency was 47.6 dBm,
48.0 dBm and 46.0 dBm, respectively. Table 5.3 shows the maximum degradation for each
frequency from these nominal values. The output power at 225 MHz decreases, in general,
as the VSWR value decreases. Particularly, the output power is at maximum at phase of 180◦ ,
where the minimum has no general rule. For 312 MHz, the output power, with each individual
VSWR value, is maximum at the 180◦ VSWR phase also. The minimum value, for 312 MHz,
occurs at the 0◦ phase. On the other hand, for 400 MHz, the output power has a maximum value
around 90◦ ˜120◦ VSWR phase. The minimum output power for this frequency occurs on 0◦ and
180◦ phase.
For the drain efficiency, the maximum, middle and high frequency was 64.1 %, 77.1 % and
79.5 %, respectively. The degradations from these nominal values are not shown here because the
82
5. VHF and UHF Broadband PA
Table 5.3: Extreme output power degradation for three different frequency
points with different VSWR values.
Pout [dBm]
VSWR
225 MHz
312 MHz
400 MHz
1.5
±0.3
+1.1/ − 0.2
+2.0/ − 0.6
2.0
+0.7/ − 1.1
+1.2/ − 1.7
+2.8
2.5
−2.3
+0.6/ − 1.7
+3.0/ − 1.5
3.0
−2.6
+2.1
+3.0/ − 1.2
big fluctuations over the measurements which is in range of 17˜30 %. The efficiency at 225 MHz
is maximum at 0◦ VSWR phase and its minimum at phase of 180◦ . The same behaviour occurs
for the frequency 312 MHz. Finally, for high frequency (400 MHz), the efficiency has an almost
constant value with all phase values at each individual VSWR value.
It is clear from Fig. 5.28, Fig. 5.29 and Table 5.3 that the output power and the efficiency
differ with each mismatch and each frequency point. The simulation was used to verify this
behaviour. In ADS, the complete power amplifier with VSWR and phase sweep is used. The
simulated output power and drain efficiency is shown as a solid line in Fig. 5.28 and Fig. 5.29,
respectively. It is clearly seen from these figures that the simulated and measured values are
comparable with each other with minor differences.
Impedance at the transistor die plane, Fig. 5.27, is shown in Fig. 5.30 as black stars on
circle paths. The simulation was performed for each measured frequency and VSWR magnitude,
phase values imposed on the ideal load-pull contours are shown in Fig. 5.10. In this figure, the
load impedances with VSWR= 1 (the load resulted from designed matching network with 50 Ω
impedance) are shown.
Those figures show that the VSWR contours are going away from the optimum solution of
the load-pull contours. In Fig. 5.30.a, the black circle moves from the output power contours to
Vgg
+
Vin
IMN
R2
Vdd
Igg
IDC
Zde-embedded 50Ω
R1
Id
+
Q1 Vd
−
OMN
VSWR
Φ
PM
−
Figure 5.27: Measurement set-up for the PA reliability showing the tuner
(VSWR), phase shifter (Φ) and the de-embedded reference plane.
83
5.2 VHF Broadband Class-E PA
50
50
@ f =225 MHz
@ f =312 MHz
48
Pout [dBm]
Pout [dBm]
48
46
44
VSWR=1.5
VSWR=2.0
VSWR=2.5
VSWR=3.0
42
46
44
VSWR=1.5
VSWR=2.0
VSWR=2.5
VSWR=3.0
42
40
40
0
30
60
90
120
150
180
0
30
60
VSWR Phase [deg.]
(a)
90
120
150
180
VSWR Phase [deg.]
(b)
50
@ f =400 MHz
Pout [dBm]
48
46
44
VSWR=1.5
VSWR=2.0
VSWR=2.5
VSWR=3.0
42
40
0
30
60
90
120
150
180
VSWR Phase [deg.]
(c)
Figure 5.28: Simulated (solid) and measured (dashed) for the Output power
with different VSWR and phase values for a) 225 MHz b) 312 MHz and c)
400 MHz.
high power contour with increasing the VSWR phase. These simulated contours (black contours)
move from high efficiency contours to low efficiency contours. From Fig. 5.30.b, de-embedded
load impedances are moving from low output power to high output power contours where it
moves from high efficiency to low efficiency contours. Finally, in Fig 5.29.c, the VSWR is rotated
symmetrically around the optimum load-pull contours. This is the reason that the power has the
same value at 0◦ and 180◦ for different VSWR values operating at f = 400 MHz. This clarifies
the discussed result from the measurement of the PA shown in Fig. 5.28 and Fig. 5.29.
However, it is worth noting that the amplifier behaves well for the high frequency range. This
is because the second harmonic of low frequency range has a lower rejection value compared to
the rejection in a higher-frequency range which is clearly seen from Fig. 5.21 and 5.23. This can
be solved by using a higher number of poles in the bandpass filter.
84
5. VHF and UHF Broadband PA
100
100
@ f =312 MHz
80
80
60
60
η [%]
η [%]
@ f =225 MHz
40
VSWR=1.5
VSWR=2.0
VSWR=2.5
VSWR=3.0
20
40
VSWR=1.5
VSWR=2.0
VSWR=2.5
VSWR=3.0
20
0
0
0
30
60
90
120
150
180
0
30
VSWR Phase [deg.]
(a)
60
90
120
150
180
VSWR Phase [deg.]
(b)
100
@ f =400 MHz
η [%]
80
60
40
VSWR=1.5
VSWR=2.0
VSWR=2.5
VSWR=3.0
20
0
0
30
60
90
120
150
180
VSWR Phase [deg.]
(c)
Figure 5.29: Simulated (solid) and measured (dashed) for the drain efficiency
with different VSWR and phase values for a) 225 MHz b) 312 MHz and c)
400 MHz.
5.3
UHF Broadband Class-E PA
In this section, a Class-E power amplifier designed for applications working between 600 MHz
and 1000 MHz is presented. This band covers the GSM band and higher band of digital video
broadcasting-terrestrial (DVB-T). The minimum output power for this amplifier is 30 W with a
very high efficiency over all the band. This amplifier is similar to the designed PA in 5.2, hence,
Class-E PA is used in this design for the same reasons specified early.
In this design, a 30 W GaN HEMT from Eudyna [40] is used. From the data sheet supplied
from the manufacturer, this device can produce more than 45 W in normal operation with 13 dB
linear gain. This allows one to choose a 31∼33 dBm power input. The chosen drain bias current
is 150 mA at Vgs = −1.3 V and Vds = 50 V. However, during the last optimization stage, it is
necessary to try changing these parameters to get the best performance over the targeted band.
High supply voltage for the transistor increases the optimum load resistance. This makes the
matching network easier to be synthesized and implemented.
The fractional bandwidth of this design is 50 % at 800 MHz. It is less than the fractional
85
5.3 UHF Broadband Class-E PA
Id0
PAE
Id0
PAE
Z designe
Z
des
ign
e
d
d
Pout
Pout
Zopt
Zopt
(a)
(b)
PAE
Id0
Z
de
sig
ne
Pout
d
Zopt
(c)
Figure 5.30: De-embedded impedance contour for sweeping VSWR value and
phase (star black) imposed on the ideal output power contours (red) with 0.5 dB
step, drain efficiency contours (green) with 2 % step and DC current contours
(blue) with 0.6 mA step, The black line is the designed load impedances for a)
225 MHz b) 312 MHz and c) 400 MHz.
bandwidth designed in 5.2, i.e., 56 % at 312.5 MHz. This might make the impedance matching
network easier to implement with fewer numbers of poles in the output filter.
5.3.1
Matching Network Design
Load/source-pull simulation was performed using Agilent’s Advanced Design System (ADS).
The optimum load impedances over the targeted band are shown in Fig 5.31.a. This figure shows
that the magnitude of load impedance can be expressed as:
{
RLopt (1 + j1.33) , @ f = f0
ZLopt =
(5.18)
∞
, @ f = n f0 , n is an integer > 1
86
Pout [dBm], Gain [dB]
|ZL |[Ω], ∠ZL [deg.]
60
∠ZL
|ZL |
40
20
0
600
700
800
900
1000
50
90
40
85
30
80
PAE
η
Pout
Gain
20
10
600
700
Freq. [MHz]
75
800
900
Efficiency [%]
5. VHF and UHF Broadband PA
70
1000
Freq. [MHz]
(a)
(b)
Figure 5.31: Ideal load/source-pull a) load impedance magnitude (blue) and
phase (red), and b) ideal performances for output power (red), gain (blue), drain
efficiency (green) and power added efficiency (black).
While RLopt is the optimum real load impedance. The best function that fits the figure shown in
Fig. 5.31.a is a linear function as in (5.13).
RLopt = −0.0193 f + 31.3113
(5.19)
Where RLopt is the optimum real load impedance. The best function that fits the figure shown
in Fig. 5.31.a is a linear function as in (5.13). As can be seen, the optimum impedance has
a constant phase equal to 53◦ , where the optimum impedance magnitude is a linear function
with negative slope over the bandwidth. This is the same behaviour obtained from the amplifier
designed previously in section 5.2, equations (5.12) and (5.13). In both designs, the optimum
impedance phase has the same value. However, the magnitude slope is lower than the optimum
impedances obtained in section 5.2. This was expected because the load impedance should be
inversely proportional to the output power and the operating frequency, follow (5.19).
ZLopt ∝
1
Pout f
(5.20)
Since the load impedances behave similar to the designed amplifier in the VHF band, The PA
network topology in Fig. 5.13 will be used in this design also. It showed good results for this
kind of power amplifier. It was also easy to implement the amplifier.
The ideal output performance is shown in Fig. 5.31.b, where the drain efficiency and power
added efficiency exceed 79 % and 76 %, respectively. The output power is 46 dBm (40 W)
with 14.4 dB over the entire band. The design of broadband Class-E PA requires at the output
a wideband band-pass filter instead of a series resonator. This filter must pass the fundamental
frequencies and reject all higher order harmonics as an open circuit termination.
The filter type is an important issue in this design. As stated previously, a broadband Class-E
PA requires a constant phase and magnitude of constant slope. Hence, a Butterworth filter was
chosen. It is well known that a Butterworth filter has a flat gain and constant phase. However, a
87
5.3 UHF Broadband Class-E PA
Class-E PA requires high rejection at the harmonics.
For the targeted band, the first harmonic (i.e.; 1200 MHz = 2 × 600 MHz) is very close to the
band edge frequency (i.e.; 1000 MHz). A roll-off of 60 dB/decade (i.e.; 3-poles) is implemented.
Moreover, to minimize the insertion loss of the filter, the 3 dB bandwidth is designed for the band
between 470 MHz and 1.160 GHz.
The circuit topology for the used bandpass filter is a T network, where the T network behaves
as an open impedance for the stop-band (i.e.; harmonics). Fig. 5.32.a shows the filter topology
used in this design. The transmission loss of the filter is shown in Fig. 5.32.b. It is seen from
this figure that the loss in the pass-band is less than 0.3 dB. The minimum harmonic suppression,
occurs at 1.2 GHz, is equal to 4.3 dB and increases as the frequency increases. This is a good
suppression value for the harmonic.
The standard filter topology as discussed in the literature is designed using a 50 Ω termination
at both sides. For the presented work, usually the transistor output impedance is not 50 Ω. On the
other hand, the values of the elements in the filter circuit depend only on the geometric mean
centre frequency (the square root of the product of the two ends of the bandwidth), as stated
previously. Hence, a matching network to 50 Ω impedance over the entire band plus capacitive
impedance that is equal to − jXCF1 in Fig. 5.32.a was designed. The output circuit network,
which combines the filter and the matching network, is shown in Fig. 5.33. Table 5.4 presents
element values of the final version of the matching network and the filter. In the output matching
network, an extra element is added in the design compared to the network in Fig. 5.16.
The input matching network topology, DC-feed network and stability circuit is designed
here similar to the amplifier in section 5.2. However, the stability circuit uses only one parallel
network in series with the input matching network and the transistor.
5.3.2
Realization
The designed amplifier was realized using Air Core inductors from coilcraft and multilayer
capacitors from ATC. The parallel network LF2CF2 shown in the filter in Fig. 5.32.a is replaced
0
CF3
LF1
+
Port 1
CF2
−
LF2
LF3
S21 =-0.04 dB @ 0.6 GHz
S21 =-0.30 dB @ 1.0 GHz
-10
+ Io (t)
Vo 50Ω
−
S21 [dB]
CF1
-20
-30
2nd Harmonic
suppression for
1.2 GHz=4.3 dB
-40
-50
(a)
0
0.5
1
1.5
Freq. [GHz]
(b)
Figure 5.32: a) Filter topology used in output matching network showing the
capacitor dashed box that will be replaced, and b) the filter transmission loss
over the targeted band and the harmonic.
2
2.5
3
88
5. VHF and UHF Broadband PA
with a short stub λ/4. From [23], the inductor, capacitor and total parasitic loss values of an LC
network can be replaced using:
4Z0
L=
(5.21)
ω0 π
C=
π
4ω0 Z0
(5.22)
Z0
(5.23)
αl
where α is the losses of the transmission line, l is the line length equal to λ/4 at geometric centre
frequency ω0 and Z0 is the characteristic impedance of the transmission line.
R=
The DC-feed here is not connected in series to the LM1 in Fig. 5.33 as with the previous
design, it is connected in a separate path closer to the transistor. This was chosen for better control
of the final matching network and to add more harmonic control for the output impedance. It is
important to add a DC-block before adding the rest of the matching network. The final amplifier
is implemented on Roger’s substrate with εr =3.38 and a thickness of 0.51 mm, Fig. 5.34.
The drain voltage and current of the designed PA at the centre frequency are shown in
Fig. 5.35. This figure presents a high frequency operation of Class-E PA. It is clearly seen that the
drain current is below the zero level which can never occur with a FET transistor. This negative
region of the drain current is the region where the output FET capacitor discharges its current to
the load during the OFF-region.
Z = (50 + jXCF1 )Ω
Vdd
IDC
LM3
CM1
Id
Q
Pin
LM1
CF3
LF1
LM2
CF2
LF3
+ Io (t)
Vo 50Ω
−
LF2
Figure 5.33: Full output matching network including the filter used in the ideal
design step.
Table 5.4: Ideal lumped elements values used in the matching network shown
in Fig. 5.33.
Lumped element
Value
LM1
CM1
LM2
LM3
LF1
4.4 nH
3.1 pF
51.7 nH
6.4 nH
10.6 nH
CF2
LF2
9.2 pF 5.0 nH
CF3
LF3
4.0 pF
10.6 nH
89
5.3 UHF Broadband Class-E PA
Input
Output
Figure 5.34: Photo of the fabricated UHF broad-band Class-E power amplifier
using 30 W GaN HEMT from Eudyna.
5.3.3
Measurements
In this section, small-signal and large-signal performances were measured using Fig. 4.7. However, the measurements of power amplifier degradation is not a goal of verification here.
The small signal gain was measured at an input level of -30 dBm. Fig. 5.36 shows that the
maximum gain is 19 dB with 1.2 dB flatness. The minimum measured small-signal harmonic
suppression is 23.6 dB. From the figure, it is observed that the small signal gain behaves rather
similar to the filter designed in Fig. 5.31.
5.3.3.1
Large Signal Performance
The large signal performance was measured from 600 MHz to 1000 MHz with step of 100 MHz.
The measurement for 800 MHz is shown in Fig. 5.37. The maximum output power was 46.9 dBm
at 4 dB compression point, i.e., 12.2 dB gain. The drain efficiency is 75.4 % where the power
added efficiency for this operating point is 75.4 %.
The performance across the targeted band is shown in Fig. 5.38. The power over all the
bandwidth is 46.1 dBm ±0.8 dB. The measured large signal gain is 11.52 dB over the entire band.
150
5
Vd
100
3
50
1
Id [A]
Vd [V]
Id
0
0.0
0.5
1.0
1.5
2.0
-1
2.5
t [nS]
Figure 5.35: Simulation of final stage for the current (red) and voltage (blue)
waveforms. The dashed lines shows the zero level for the current, where below
the dashed line is the time for the output capacitor Cds discharging and above
the line is the charging period of the output capacitor Cds .
90
5. VHF and UHF Broadband PA
20
Gainss [dB]
10
0
-4.6
-10
-20
-30
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Freq. [GHz]
Figure 5.36: Measured small signal gain across the bandwidth with -30 dBm
showing the gain for the second harmonic of the lowest frequency.
Over this band, the measured drain efficiency and measured power added efficiency are more
than 66 % and more than 62 %. Table 5.5 summarizes the measured results in Fig. 5.38.
For the bandwidth between 600 MHz to 800 MHz, the amplifier delivers 46.3 dBm output
power with ±0.53 dB flatness with 11.4 dB gain. The drain efficiency in this band is more than
80.0 % where the power added efficiency is more than 75 %. The fractional bandwidth is 28.6 %
centred at 700 MHz.
5.4
Broadband SMPA Behaviour Over the Frequency
It was clear, as can be seen from Fig. 5.38, that there is a peak in the drain efficiency at 87 %
around 700 MHz but further up in frequency this drops to around 80 % at the centre frequency
800 MHz and then further to 66 % at 900 MHz. Clarifying and understanding what causes this
drop, the full bandwidth response can be much improved in the future.
100
Pout
Gain
η
PAE
40
80
30
60
20
40
10
20
0
0
10
20
30
Efficiency [%]
Pout [dBm], Gain [dB]
50
0
40
Pin [dBm]
Figure 5.37: Measured output power (red), gain (blue) drain efficiency (green)
and PAE (black) over the stimulated input power for the centre frequency, i.e.,
800 MHz, of the designed power with Vd = 50 V, Idq = 150 mA
91
5.4 Broadband SMPA Behaviour Over the Frequency
50
100
80
30
20
Poutmeas
Gainmeas
ηmeas
Poutsim
Gainsim
ηsim
PAEmeas
PAEsim
60
Efficiency [%]
Pout [dBm], Gain [dB]
40
40
10
0
20
0.6
0.7
0.8
0.9
1
Freq [GHz]
Figure 5.38: Measured output power (red), gain (blue) drain efficiency (green)
and PAE (black) across the bandwidth for the maximum output power (Pin =
34 dBm) frequency, i.e., 800 MHz, of the designed power with Vd = 50 V,
Idq = 150 mA.
5.4.1
DE-Embedding Method
The broadband power amplifier was designed for a Class-E PA operation. However, the ideal
optimum load impedances for this class were extracted with very high impedance approaching
ideal open termination. This makes it unpractical for the designed filter since the attenuation for
low harmonic is not high enough. Hence, the PA operation is not optimally Class-E PA for the
entire frequency band.
The PA will be considered as a black box with two reference planes at the input and the
output. PA classes can be identified, usually, by the time domain waveforms in the intrinsic
transistor plane. Knowing the matching network’s characteristics from ADS and the response
of the transistor package, some measurements on the 50 Ω can be de-embedded to the ZL plane,
die plane, as shown in Fig. 5.39. The waveforms can be de-embedded and used to analyse the
operation mode, and to extract the load impedances seen on the die reference plane.
Table 5.5: Measured PA performances across the bandwidth with 100 MHz
step.
Freq. [MHz]
Performance
Pout [dBm]
η [%]
PAE [%]
Gain [dB]
600 MHz
700 MHz
800 MHz
900 MHz
1000 MHz
46.8
82.7
76.7
11.4
45.4
87.8
80.6
10.6
46.9
80.0
75.4
12.2
46.2
66.0
61.9
12.2
45.2
67.2
62.3
11.3
92
5. VHF and UHF Broadband PA
For GaN devices, the output capacitance Ct model, which is the main effect of the waveform
shapes, is linear and has a small value. Hence the effect of this capacitance on the waveforms
for the low frequency can be neglected. Following the previous assumption and considering the
transistor as a source generator, the time domain of the drain voltage and current can be extracted
using (5.24) [23].
[ ] [
][ ]
Vd
A B Vo
=
(5.24)
Id
C D Io
Where, Vo and Io are the output voltage and current content, respectively.
These parameters can be acquired by measuring the time domain output voltage either by
using an oscilloscope or a large signal network analyser (LSNA). The transmission matrix in
(5.24) is the total transmission matrix of the matching network, filter and the package. Usually
the measurement devices can give the voltage component, and the current can be calculated based
on 50 Ω system; Io = Vo /50.
The time domain extraction method was verified in the simulation environment. It showed
a very good agreement between the simulated and calculated parameters. Fig. 5.40 shows the
calculated waveforms for the current (Id ) and the voltage (Vd ) at the die reference plane for 3
different frequencies (i.e.; 600 MHz, 800 MHz and 1000 MHz).
The extracted waveforms do not have the same shape over the frequency band which can be
concluded that the optimum Class-E PA operation is not maintained ideally over the entire band.
Fig. 5.41 shows the calculated load impedances from the extracted waveforms (ZL = Vd /Id ) for
the same frequencies calculated previously and the same reference plane. These impedances
with the extracted waveforms will guide on determining the class operation for each of these
frequencies.
5.4.2
Discussion
One very important point before starting with the analysis is that the optimum load impedances in
(5.18) excludes the effect of the intrinsic output capacitance of the die. The optimum impedance
Vdd
IDC Zd
ZL
Id
+
Pin
Q Vd
−
Package
Ct model
OMN
BPF
+ Io (t)
Vo RL
−
Figure 5.39: Circuit diagram of the PA showing the de-embedded load impedance and drain impedance reference plane.
93
5.4 Broadband SMPA Behaviour Over the Frequency
200
6
150
Id
4
2
50
0
1.0
1.5
2.0
2.5
3.0
50
1
0
0.0
-2
0.5
3
3.5
0.5
1.0
2.0
-1
2.5
t [nS]
(b)
t [nS]
(a)
200
6
Id
150
Vd [V]
1.5
Vd
4
100
2
50
0
0
0.0
Id [A]
0
0.0
100
Id [A]
100
Id [A]
Vd [V]
Vd [V]
150
5
Vd
Id
Vd
-2
0.5
1.0
1.5
2.0
t [nS]
(c)
Figure 5.40: Simulated current (red) and voltage (blue) waveforms for a)
600 MHz, b) 800 MHz and c) 1000 MHz. The dashed lines shows the zero level
for the current, where below the dashed line is the time for the output capacitor
Cds discharging and above the line is the charging period of the output capacitor
Cds .
for the entire harmonic seen at the internal current source, Zd in Fig. 5.39, is usually a capacitive
load (i.e.; Ct in Fig. 5.39) which is a frequency (or harmonic) dependent impedance. The ideal
impedances seen from the transistors current source is given by:
⎧
⎨ Rdopt (1 + jαx ) , @ f = f0
Zdopt =
(5.25)
−j
⎩
, @ f = n f0 , n is an integer > 1
2π fCt
where αx is the imaginary impedance factor equal to Xdopt /Rdopt . According to (5.25) and
previous assumptions, the following analysis will explain the behaviour of the PA over the
bandwidth.
A. Analysis at 600 MHz
It can be seen from Fig. 5.40.a, that the voltage shape is sinusoidal while the current is not
purely as in Class-E PA and not even purely a square shape. However, from Fig. 5.41.a,
the fundamental impedance is inductive and the second harmonic impedance is inductive
approaching infinity on the Smith chart. The rest of the harmonic impedances have a very
low impedance, mostly in the capacitive part of the Smith chart. It is known that the second
94
5. VHF and UHF Broadband PA
5f0
f0
2f0
f0
4f0
5f0
4f0
3f0
3f0
2f0
(a)
(b)
4f0
f0
3f0
2f0
5f0
(c)
Figure 5.41: Calculated load impedances from the simulation for a) 600 MHz,
b) 800 MHz and c) 1000 MHz.
harmonic termination for an ideal Class-F−1 is open. Hence, for this frequency operation,
the PA operation resembles a Class-E/F2 PA [36].
B. Analysis at 800 MHz
From Fig. 5.40.b, the voltage shape is sinusoidal while the current is close to the current of
a high frequency Class-E PA. Moreover, from Fig. 5.41.b, the fundamental impedance is
inductive and the harmonics are terminated with low real impedance values (approaching
zero) and capacitive imaginary value. These impedance terminations behave as in Class-E
PA (5.25).
C. Analysis at 1000 MHz
The voltage in Fig. 5.40.c resembles a sinusoidal shape while the current is close to the
current in Class-E PA. In Fig. 5.41.c, the fundamental impedance is inductively tuned. The
harmonics’ impedance is terminated with low real impedance values, but the imaginary
value is between capacitive and inductive. This kind of operation can be stated as weak
Class-E PA or as Class-E/F3 .
5.4 Broadband SMPA Behaviour Over the Frequency
95
It was stated previously that the efficiency at 1 GHz is 15 % less than the efficiency at 800 MHz.
Investigating the waveforms in Fig. 5.40 will help in the investigation of the power loss. In the
turn-ON region of the switching behaviour, there is no overlapping between the drain current and
the drain voltage for all the frequencies satisfying zero voltage switching (ZVS) condition. The
dashed line in Fig. 5.40, shows that the major part of the losses is during the OFF-state of the
operation, where the capacitor, i.e., Ct , is charging and discharging. To reduce the losses in this
region, The design needs to have a zero current switching (ZCS) operation. This ZCS requires
the switch (in this case the transistor) to be zero just prior to the turn-OFF state. Achieving this
requires that the second harmonic impedance seen at the transistor at 1000 MHz is smaller than
the second harmonic impedance seen at the transistor reference plane at 800 MHz, Fig. 5.41.
96
5. VHF and UHF Broadband PA
6|
L and S Band Broadband PA
To this point, broadband highly efficient PAs for low frequencies were presented. It was shown
that the input/output matching networks designed for those frequencies were composed of lumped
elements. The reason for this is the high quality factor, the smaller size compared to a microstrip
line and the high resonance frequency compared to the operating frequency.
This Chapter will present two PAs working on L/S-Band. The matching networks for these
amplifiers will be based on microstip lines and some lumped elements, e.g. mainly capacitors.
Different approaches of finding optimum impedances will be shown for these bands. The PAs
will work as harmonically tuned PAs (HTPA). This choice is a result from previous discussions
in section 5.4, which conclude that matching the harmonic impedance for a wide range of
frequencies to the optimal open (one point in the Smith chart) is extremely difficult for a finite
number of poles.
6.1
10 W-Harmonically Tuned PA
A 10 Watt GaN HEMT transistor from Cree Inc. [55] is used for this design. Efficiency for this
amplifier is a very important goal as well as bandwidth. The required PAE should be more than
65 %, and desired bandwidth is from 1.7 GHz to 2.7 GHz with 2.2 GHz centre frequency. This
makes a total fractional bandwidth of more than 45 %. The PA is biased with a deep Class-AB PA
(Id = 20 mA) with a supply voltage of Vdd = 28 V. If the gain is 12 to 10 dB [55]. The input power,
used in the simulation, will be 28 ∼ 30 dBm. All these parameters are used in load/source-pull
simulation to procure the optimum load and source impedances across the required bandwidth.
6.1.1
Load/Source-Pull Simulation
Source/load-pull simulations in Agilent’s Advanced Design System (ADS) is performed to extract
the optimum impedances over the targeted band. The output power and PAE contours for three
frequencies, i.e., 1.7 GHz, 2.2 GHz and 2.7 GHz, are shown in Fig. 6.1.
98
6. L and S Band Broadband PA
The load impedance for Class-E power amplifiers, as discussed previously, have constant
phase and negative magnitude slop over the frequency. This can be converted to negative real and
imaginary slope over the frequency. The behaviour of such load impedances makes the output
matching network easy to implement with shunt inductors and series capacitors.
Since the impedance of high frequency is minimum, choosing the optimum impedances that
satisfy the PA requirements will start from high to low frequency points. This will be chosen
in the lower left side of the PAE contours, represented as dot in Fig. 6.1.c. With increasing the
frequency, the optimum load impedance point will be moved on a spiral inward clockwise path,
shown in Fig. 6.1.a and b. The optimum chosen load impedances, up to three harmonics, are
shown in Fig. 6.2 and the corresponding optimum output power and PAE are shown in Fig. 6.3.
As it can be seen from Fig. 6.2, the optimum load impedances for the harmonics have large
differences in magnitude and phase. Furthermore, there is an overlapping band between the
second and the third harmonic but with different termination impedances. Hence, a design taking
into account a trade-off between these impedances, without influencing the results, must be
PAE
PAE
Zopt
Zopt
Pout
Pout
(a)
(b)
PAE
Zopt
Pout
(c)
Figure 6.1: Output power and PAE contours for 10W PA design at a) 1.7 GHZ,
b) 2.2 GHz, and, c) 2.7 GHz. The input power was 29 dBm, Vdd = 28 V and
Id = 20 mA.
99
6.1 10 W-Harmonically Tuned PA
150
100
50
100
∠ZLopt [◦ ]
⏐
⏐
⏐ZLopt ⏐ [Ω]
2nd Harmonic
0
Fund.
50
-50
3rd
Harmonic
0
-100
1
2
3
4
5
6
7
8
9
Freq. [GHz]
Figure 6.2: Optimum load impedances, i.e., magnitude and phase, for the
fundamental frequency, second and third harmonic. The input power was
29 dBm, Vdd = 28 V and Id = 20 mA.
considered.
6.1.1.1
The Effect of the Load Impedances
42
80
41
75
40
70
39
65
38
1.6
1.8
2
2.2
2.4
2.6
PAE [%]
Pout [dBm]
The optimum load impedances for the lowest, the center and the maximum frequency in the
targeted band are represented in Table 6.1. These impedances are swept in the simulation for
the presented frequencies, each of which are performed with all other parameters being fixed,
e.g. sweeping the magnitude of the fundamental impedance while fixing its phase and the other
harmonic impedances. The goal is to find a set for all the optimum impedances that can give an
output power and PAE higher than 39 dBm and 65 %, respectively. These found impedances will
be called a safe zone region for the matching network. The following discussion is accomplished
for the fundamental and the second harmonic; for the third harmonic, the same analysis is applied.
60
2.8
Freq. [GHz]
Figure 6.3: Optimum output power and PAE obtained from the optimum load
impedances. The input power was 29 dBm, Vdd = 28 V and Id = 20 mA.
100
6. L and S Band Broadband PA
Table 6.1: Optimum Load Impedances for the First Three Harmonic at Three
Different Frequencies
@ f1 = 1.7 GHz
@ f2 = 2.2 GHz
@ f3 = 2.7 GHz
Zfund. [Ω]
21.0∠40.0◦
17.0∠29.3◦
13.5∠12.0◦
Z2nd [Ω]
112.7∠74.1◦
61.5∠79.0◦
38.2∠80.6◦
Z3rd [Ω]
13.2∠ − 89.6◦
46.8∠ − 88.4◦
143.1∠ − 84.4◦
1. The Effect of the Fundamental Load Impedance:. Fig. 6.4. shows the effect of
sweeping the fundamental magnitude on the output power and the PAE for the three
different frequencies. The impedance margin, i.e., impedance range ZLg , will be chosen
for the intersection between the smallest range of the PAE (PAEmin ) and the smallest range
of the output power (Pout_min ):
ZLg = PAEmin ∩ Pout_min
(6.1)
The minimum output power range (Pout_min ), as shown in Fig. 6.4.a, is between 10 Ω and
24 Ω. This range satisfies the minimum requirement of the output power, i.e., 39 dBm. On
the other hand, the minimum PAE range (PAEmin ) is between 13.5 Ω and 30 Ω. Applying
(6.1) in these ranges, the impedance range is:
ZLg_mag f 0 = [13.5, 30] ∩ [10, 24] = [13.5, 24]
(6.2)
100
40
80
38
60
@1.7 GHz
@2.2 GHz
@2.7 GHz
36
40
34
20
0
10
20
⏐
30
⏐
⏐ZLopt_ f ⏐
0
(a)
40
50
50
100
40
80
30
60
20
40
@1.7 GHz
@2.2 GHz
@2.7 GHz
10
0
-100
-50
0
∠ZL f0
(b)
Figure 6.4: Output power and PAE for three different frequencies versus (a)
the magnitude of the fundamental frequency load impedance and (b) the phase
of the fundamental frequency load impedance. The input power was 29 dBm,
Vdd = 28 V and Id = 20 mA.
50
20
0
100
PAE [%]
42
PAE [%]
Pout [dBm]
Pout [dBm]
The phase of the fundamental load impedance controls the phase shift between the drain
voltage and drain current which affects the power and the efficiency performance. Hence, it
has a major impact (Fig. 6.4.b). Similar to (6.2), The impedance range for the fundamental
phase load will be chosen for the intersection between the smallest range of the PAE and
101
6.1 10 W-Harmonically Tuned PA
the smallest intersection range of the output power:
ZLg_phase f 0 = [5.5, 52.3] ∩ [−30.5, 26.2] = [5.6, 26.2]Ω
(6.3)
The values in (6.2) and (6.3) are the upper and lower boundaries to the safe-zone impedance
range.
2. The Effect of the Second Harmonic Load Impedance. Similar simulations are performed for the second harmonic impedances over the three frequencies. The magnitude of
the second harmonic impedance has an almost negligible effect on the output power and
the PAE for values higher than 20 Ω. Furthermore, its phase has no influence on the output
power and PAE as long as the impedance magnitude is kept high. However, it is better
to be more inductive to get an output power near 40 dBm at 2.7 GHz. Load-pull for the
second harmonic impedances gives a better overview for the power added efficiency and
output power performances, Fig. 6.5. It is clearly seen from this Figure that the efficiency
is maximum on the inductive side for all the frequencies, which follows the result made
before. Another important point in this figure is that the minimum performances occur near
short circuit point. This is clearly seen in Fig. 6.5 and Fig. 6.6.
100
40
80
38
60
@1.7 GHz
@2.2 GHz
@2.7 GHz
36
40
34
20
0
10
20
⏐
30⏐
⏐ZLopt_2 f ⏐
0
(a)
40
50
43
80
42
75
41
70
40
65
@1.7 GHz
@2.2 GHz
@2.7 GHz
39
38
-100
-50
0
∠ZL2 f0
(b)
Figure 6.5: Output power and PAE for three different frequencies versus (a)
the magnitude of the second harmonic load impedance and (b) the phase of the
second harmonic load impedance. The input power was 29 dBm, Vdd = 28 V
and Id = 20 mA.
60
50
55
100
PAE [%]
42
PAE [%]
Pout [dBm]
Pout [dBm]
It is also worth noting from Fig. 6.7 that the minimum performance occurs in different phases
of the reflection coefficient with each frequency point. To understand the reason for this, it
should be mentioned that the output model for the transistor consists of a shunt capacitor, i.e.,
Cds representing the output capacitance, and a series inductor, i.e., Lpckg representing the package
inductance. If the imaginary part in the load impedance reaches the value in (6.4), i.e., series
resonance, the voltage of the second harmonic reaches minimum value and, hence, there is no
voltage peaking. The amplifier, then, works as a classical class depending on the bias point.
102
6. L and S Band Broadband PA
D ecr
De
e
crea
si
asi
ng
ng
Pe
Pe
rf
or
rf
m
an
ce
or
m
an
ce
(a)
(b)
D ecr
e
asi
ng
Pe
rf
or
m
an
ce
(c)
Figure 6.6: Output power contours with 0.3 dB step (solid green) and PAE
(symbol red) with 5 % step performances versus the second harmonic load
impedances for; a) 1.7 GHz, a) 2.2 GHz, and, a) 2.7 GHz. The input power was
29 dBm, Vdd = 28 V and Id = 20 mA.
CL@2 f0 =
6.1.1.2
1
(2π f0 )2 Lpckg
(6.4)
Safe-Zone Impedance Margin
The third harmonic impedance has a negligible effect as long as it is maintained at the edge of
the Smith chart. It is important to have the safe-zone impedances on the Smith chart for the
matching network. With the help of (6.2) and (6.3), PAE and output power contours resulted from
load-pull simulation for the second and third harmonic is performed. Fig. 6.8.a shows the PAE
from maximum to 65 % contours and 39 dBm output power contours as a limit for the design
goals. The intersection of these contours for all three frequencies is shown as a dashed region in
Fig. 6.8.a which satisfy the conditions in (6.2) and (6.3).
Similar simulation is performed for the second harmonic load-pull, Fig. 6.8.b. The safe-zone
impedance, shown as a dashed region in this figure, is obtained only from the PAE contours
because the output power is not influenced from the second harmonic impedance. This region
clearly describes the analysis made previously. A part of the load impedances for these safe zones
103
PAE [%]
6.1 10 W-Harmonically Tuned PA
100
100
80
80
60
60
40
40
@1.7GHz
@2.2GHz
@2.7GHz
20
20
0
0
60
120
180
240
300
0
360
∠Sload@2 f0
Figure 6.7: PAE performance with full second harmonic reflection coefficient
and different phase values for three different frequencies. The input power was
29 dBm, Vdd = 28 V and Id = 20 mA.
was implemented ideally in the simulation, and it showed a good agreement as expected from
the previous analysis concerning output power and PAE. The complete safe-zone region for the
fundamental and second harmonic impedance is shown alone in Fig. 6.9.
6.1.2
Matching Network Design and Synthesis
In the first approach, the output matching network (OMN) was designed step by step from the load
to the drain side at the center frequency (i.e. 2.2 GHz). Fig. 6.10.a shows the output matching
network and Fig. 6.10.b the corresponding impedance transformation for each intermediate
section.
PAE
P out
(a)
(b)
Figure 6.8: Method for obtaining the safe-zone of load impedances by finding
the intersection of optimum impedance for a) fundamental frequency and b)
second harmonic.
104
6. L and S Band Broadband PA
Fund. safe zone
2nd Harmonic safe zone
Figure 6.9: Safe zone region definition.
6.1.2.1
DC-feed Design
The output matching network was designed using ideal lumped elements and ideal transmission
lines. The input source impedance is implemented using a function that describes it over the
bandwidth. The input and output DC-feed was implemented using ideal high inductance with
an ideal shunt capacitor. In this design, the main goal of the DC-feed, besides isolating the RF
path from the DC path, is to present high impedance for all RF signals, including fundamental
and harmonics’ components. Hence, a broadband DC feed that blocks these RF components,
and presents a short circuit for all other frequencies is necessary to accomplish the goals of this
design. To fulfill this, multiple series inductors, having a resonance occurring on the fundamental
band, are implemented. Parallel capacitors with different values are attached after each inductor,
as shown in Fig. 5.17. In most of the cases, these lumped elements have the same values, which
Z1
Z2
Z3
Vdd
IDC
ZL
ZL2
ZL1
f0
f0
Id
+
Pin
C
Q Vd
+ Io (t)
Vo RL
f0
−
−
(a)
(b)
Figure 6.10: a) Ideal single section matching network for 10 W power amplifier
design, b) load impedances for the first three harmonics at three different
frequencies obtained at each section from the matching network.
105
6.1 10 W-Harmonically Tuned PA
double the bandwidth of the DC-feed.
The first element in the output matching network, shown in Fig. 6.10.a, is a shunt stub. This
can be used as a part of the DC feed, i.e., for high frequency. Hence the ground path of this shunt
stub can be presented with a group of shunt capacitors, as in the DC-feed, to block th DC current
from the ground and to give a low impedance for the targeted frequency.
Afterwards, this circuit was simulated for the entire band with 50 MHz step. The result
was comparable with the required safe zone except for the impedances at the high frequencies
(Fig. 6.11.). Hence, more freedom of controlling the impedances for the entire band was achieved
by using two cascaded matching network of the type as shown in Fig. 6.10.a, replacing the
capacitor with a shunt open stub. The input matching network is achieved using three sections of
L network, each of which consists of transmission line and shunt capacitors.
The simulated performance of the final design (two OMN sections plus input matching
network) is shown in Fig. 6.12. The entire PA was designed using a Roger’s substrate with
εr = 3.38 and a thickness of 0.51 mm. The manufactured PA photograph is shown in Fig. 6.13.
6.1.3
Measurements
6.1.3.1
Single Tone Measurements
CW signals were used to stimulate the designed PA across the bandwidth to characterize its
performances. The input power and the signal frequency were varied from 0 dBm to 34 dBm
with 1 dB step and from 1.4 GHz to 2.8 GHz with 50.0 MHz step, respectively. A complex 3-D
matrix results from these measurements for each performance parameter. These outcomes are
analysed to show the output power, gain, drain efficiency and power added efficiency for 1-dB
and 3-dB compression points, see Fig. 6.14.
Drain efficiency and PAE between 61.0 % and 82.5 % and between 56.0 % and 75.3 %,
Z1
Z2
Z3
fHi
freq
fLo
Fund. safe zone
2nd Harmonic safe zone
Figure 6.11: Realised load impedance from two section matching network for
the fundamental and second harmonic across the targeted band imposed on the
safe zone region.
106
42
100
40
90
38
80
36
70
34
1.6
1.8
2
2.2
2.4
2.6
PAE [%]
Pout [dBm]
6. L and S Band Broadband PA
60
2.8
Freq. [GHz]
Figure 6.12: comparison between realised simulated results (symbol) and
optimum simulated results (solid) for the output power and PAE. The input
power was 29 dBm, Vdd = 28 V and Id = 20 mA.
respectively, were achieved across the bandwidth between 1.5-2.7 GHz (60 % BW at 2.125 GHz
centre frequency) at the 1 dB compression point. The output power at this point is 39 dBm ±2
dB across this band. It is worth noting that the bandwidth is increased 200 MHz in the lower
edge. The reason for this is that the safe-zone for the impedances shown in Fig. 6.9 is not only
optimal for the targeted band but also is an optimal range for the lower frequency. Additionally,
the matching network uses two sections, which make the load impedances to be in the middle of
the fundamental safe-zone of the impedances.
For the 3 dB compression point, the output power is nearly 40 dBm ±1.5 dB over the
bandwidth from 1.5 GHz to 2.75 GHz. At this power level, the measured drain efficiency
and PAE across this band are between 71.0 % and 84.0 % and between 58.5 % and 78.0 %,
respectively.
A single frequency result is shown in Fig. 6.15 for the new centre frequency (2.125 GHz).
The maximum linear output power for this amplifier at the centre frequency is 40.2 dBm (10.5 W)
Input
Output
Figure 6.13: Photo of the fabricated broad-band harmonically tuned power
amplifier using 10 W GaN HEMT from Cree Inc.
Pout [dBm], Gain [dB]
50
100
40
80
30
60
20
40
10
20
0
PAE [%]
107
6.1 10 W-Harmonically Tuned PA
0
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Freq. [GHz]
Figure 6.14: Measured output power, power gain and PAE for the designed
power amplifier across the bandwidth for the 1 dB compression point (hollow
symbol) and 3 dB compression point (filled symbol). The input power was
30 − 32 dBm, Vdd = 28 V and Id = 20 mA.
with 12.1 dB gain. The maximum drain efficiency and PAE occur around 3-dB compression point
with 71 % and 63 %, respectively.
6.1.3.2
Linearity for UMTS Application.
50
100
40
80
30
60
20
40
10
20
0
.
0
5
10
15
20
25
30
Efficiency [%]
Pout [dBm], Gain [dB]
A WCDMA signal of 5 MHz channel bandwidth and 8.51 dB peak to average power ratio (PAR)
with a centre frequency of 2.15 GHz was used as a driving signal. The measurements were
done for three different drain supply voltages (Vdd = 28, 32, and 36 V) at three varied gate bias
voltages (Vgg = -3.21, -3.11 and -3.01 V) to find the best linearity without affecting the designed
efficiency and output power. The measurement showed the optimum linearity (ACPR) of -36 dBc
with an average output power (Pout_avg) of 35 dBm. This point is 8.5 dB back from the 3-dB
compression point (43.5). The average drain efficiency (ηavg ) of 35 % occurs at Vdd =32 V and
0
35
Freq. [GHz]
Figure 6.15: Measured power amplifier performances across the input power
at the centre frequency (2.125 GHz). Vdd = 28 V and Id = 20 mA.
108
40
40
35
38
36
η[%]
Pout [dBm], ACPR [dBc]
6. L and S Band Broadband PA
34
-35
Vgg=-3.21
-40
26
V=-3.11
Vgg=-3.01
32
28
30
32
Vdd [V]
34
36
38
Figure 6.16: ACPR and average output power and drain efficiency versus the
supply drain voltage and gate bias voltage at 35 dBm.
Vgg =-3.01 V (Fig. 6.16). However, the bias voltage has a major influence on the degradation of
the ACPR. On the other hand, the output power and drain efficiency is influenced by the supply
voltage more than the bias voltage.
6.2
100 W L-Band Power Amplifier
A broadband 100 W PA is the goal for this design. The PA should have a high efficiency operation
and is intended to work for a bandwidth that covers the frequency bands of modern wireless
standard (1.65 GHz-2.25 GHz) i.e., DCS1800/LTE, PCS1900/LTE and WCDMA/LTE. The
120 W GaN HEMT from Cree Inc. is chosen for this design. It has a stable model and high linear
efficiency [56].
Q
Cds
(a)
Rpckg
LLead
8
100
6
50
4
0
2
-50
0
0
0.5
1.0
1.5
2.0
Freq. [GHz]
(b)
Figure 6.17: a) Typical transistor package model and b) small signal load
impedances seen from the lead reference plane of a 100W Cree transistor. The
input power was 40 dBm, Vdd = 28 V and Id = 400 mA.
2.5
∠Zout [deg.]
Lpckg
|Zout | [Ω]
It is well known that the output capacitance Cds of a high power transistor can limit the frequency response in case of the efficiency (depending on the PA class) and the power performance.
With increasing the frequency, the output capacitance lowers the optimum output impedance and
raises the switching losses. This makes the output impedance greatly influenced by the bondwires
-100
3.0
6.2 100 W L-Band Power Amplifier
109
of the package and results in inductive output impedance, see Fig. 6.17.
The black dots in Fig. 6.17.a show that the package model resonates out the output capacitance
of the transistor. This resonance frequency occurs at 1.3 GHz where the magnitude and the phase
are minimum and zero, respectively. It can be vividly seen that the phase at low frequency range
is capacitive where the phase at the high frequency range is inductive. Fig. 6.17.b can be modeled
exactly like the circuit in Fig. 6.17.b. Where the transistor can be ideal FET and Rpckg and LLead
are very small.
From previous analysis, the predicted optimum load impedances must be capacitive for all
the frequencies above the package resonance, which is in the targeted band.
The chosen bias point will be deep Class-AB PA. Hence, 400 mA drain current and the typical
supply voltage, i.e., 28 V, are the bias points for this design. The input power is chosen to be
40 dBm to achieve 10 dB power gain. These points will be used for acquiring the optimum load
and source impedances from ADS.
6.2.1
Power Handling Capabilities of Passive Components
Microstrips, inductors, capacitors, and resistors have a limited power handling capability (PHC)
which follows the heat distribution in a medium. The PHC of the latter three passive elements
can be obtained from their manufacturer data sheet.
6.2.1.1
Microstrip Lines PHC
The maximum average power that a microstrip line can handle is limited to; microstrip line losses,
thermal conductivity of the dielectric, skin effect area, maximum allowed operating temperature
and the ambient temperature. The maximum average power that it can handle is calculated
as [29]:
Pavg = (Tmax − Tamb )/∆T
(6.5)
where ∆T is the rise of the temperature per watt, Tmax is the maximum operating temperature and
Tamb is the temperature at of the operating environment which is usually room temperature 25◦ C.
The maximum operating temperature is the point where the physical and mechanical property
of the microstrip line changes. For Tmax = 150◦ and room temperature of 25◦ , the rise in
temperature that is needed for 120 W average output power on RO4003 LoPro is 1.042 C/W.
RO4003 LoPro is chosen because it has the lowest temperature coefficient [57]. For 125◦ C
temperature rise over the ambient temperature, the minimum microstrip line to be used for this
power, and this substrate is 0.45 mm.
To this point, average power handling capabilities APHC was the major point. However, the
peak power or DC peak power handling capabilities PPHC is an important issue for this design.
110
6. L and S Band Broadband PA
It can be calculated simply, using:
2
VDC
(6.6)
RDC
is the microstrip line which can be calculated as:
PDC =
where VDC is the drain voltage and RDC
RDC =
ρl
A
(6.7)
where ρ is the resistivity of the material which is 1.68 × 10−8 for copper material, l is the length
of the inductor, and A is the cross section area of the conductor. (6.6) can be rewritten as:
Pavg,RF =
2 ·A
η VDC
100 ρl
(6.8)
The main influential part to enhance the PPHC is the copper thickness. Hence, substrate with
35 µm is used to give a range for the design.
6.2.2
Load-Pull Simulation
Harmonic tuning is used, and it showed very good performance in efficiency and linearity. This
encourages using the same method for this design. Load-pull simulation is used to acquire the
optimum load impedances. Output power, with 1 dB step, and PAE, with 6 % step, contours
for the two edge frequencies are shown in Fig. 6.18. This figure shows how sensitive the load
impedance at this frequency is. The reason for this is the targeted band located near the resonance
frequency which makes any change in load impedances to drastically affect the optimum load
impedances seen by the transistor.
The fundamental load impedance at the package reference plane is capacitive, which is
already predicted in the previous section. As it can be seen in Fig. 6.19.a, the load impedances
for the harmonics have large differences in magnitude and phase. Hence, a design considering
the trade-off between these impedances which do not affect the result must be carried out. For
Pout @ 1.65 GHz
Pout @ 2.25 GHz
PAE @ 1.65 GHz
PAE @ 2.25 GHz
Figure 6.18: Output power contours with 0.5 dB step and PAE contours with
5 % step for 100 W power amplifier at the edge frequencies.
111
6.2 100 W L-Band Power Amplifier
(a)
(b)
Figure 6.19: Fundamental (red) second harmonic (green) and third harmonic
(blue) load impedances for a) optimum case with Smith chart centred at 50 Ω,
and b) optimum (dotted), realised from ideal lumped OMN (crossed) and
realised from microstrip OMN (solid). The input power was 40 dBm, Vdd = 28 V
and Id = 400 mA.
this reason, the load impedances are re-normalized on a Smith chart centred with the output
impedance at the centre frequency, i.e., 2.75+j1.2 Ω, Fig. 6.19.b (dotted line). The second and
the third harmonic impedances appear close to open and short termination, respectively.
The re-normalization gives a better view of the optimum load impedances and can show the
difference between realised impedances and optimum impedances.
As discussed in the previous section, safe-zone impedances are determined for the second
harmonic load impedance. Fig. 6.20 shows that the PAE has a minimum around 180◦ . The PAE
maximum occurs at the positive imaginary part (i.e., from 0◦ to 180◦ phase of S11 ). This produces
an optimum safe-zone of an inductive load for the second harmonic impedances. The safe-zone
of the fundamental impedance will not be considered here because of its negligible sensitivity,
which will result in a very small range of impedances.
80
PAE [%]
70
60
50
PAE @ 1.65 GHz
PAE @ 2.25 GHz
40
0
60
120
180
240
300
360
∠Γ2 f0
Figure 6.20: PAE performance with full second harmonic reflection coefficient
and different phase values for two different frequencies. The input power was
40 dBm, Vdd = 28 V and Id = 400 mA.
112
6.2.3
6. L and S Band Broadband PA
Matching Network Design
Making the transistor stable is an easy goal due to the large parasitic at the input and the output
of the 120 W PA. A simple parallel RC is used at the input of the transistor and a small resistance
at the gate bias network. Fig. 6.21 shows that the stability factor K is above 1.5.
The first step to realize the load impedances obtained from the load-pull simulation is to
find the optimum topology using lumped components. A low impedance microstrip line is used
for two reasons; first, to take the lead into account and second, to urge the optimum small load
impedances to move away from the edge of the Smith chart. A 3-poles ideal matching network
was used. Fig. 6.22 presents the idealized output matching network. The shunt parallel LCs
behave as poles for the pass-band and the inductors behave as zeros for the harmonics. The
resulted impedances (cross symbol) from this matching network compared with the optimum
load impedances (dotted lines) are shown in Fig. 6.19.b. It can be seen clearly, that this matching
network fits the required impedances from the load-pull simulation. The output power and PAE
obtained from the ideal lumped element matching network are shown in Fig. 6.23.a and 6.23.b,
respectively.
The ideal matching network was transformed to the equivalent microstrip line matching
network using step impedance technique, with every pole represented using wide step impedance
(resemble double stub), and every inductor represented using narrow transmission line. The
realized load impedances seen on the transistor reference plane are shown in Fig. 6.19.b,
also. It fits, clearly, with the load impedances obtained from the ideal matching network using
lumped elements, which was developed on base of load-pull data. As a final step, simulation
of the complete PA over different temperature points is performed. With 85◦ C operation, the
output power reduces to below 100 W, where the PAE decreases, approximately, 5 % from the
performances at room temperature operation, Fig. 6.24. The size of the manufactured amplifier
PCB is 65 x 60 cm2 , Fig. 6.25. A λ/4 transmission line and a high current inductor was used as
an RF choke for the drain terminal.
5
4
4
3
3
2
2
1
1
K
5
0
0
2
4
6
8
0
10
Freq. [GHz]
Figure 6.21: Stability factor for the designed power amplifier. The input power
was 40 dBm, Vdd = 28 V and Id = 400 mA.
113
6.2 100 W L-Band Power Amplifier
LZ1
+
Port 1
−
CP1
LZ3
LZ2
LP1
CP2
LP2
+ Io (t)
LP3
CP3
Vo
50Ω
−
Figure 6.22: Ideal lumped component matching network for the designed
amplifier. The input power was 40 dBm, Vdd = 28 V and Id = 400 mA.
6.2.4
Experimental Results
Due to the sensitivity of the optimum load impedance for this transistor, An optimum bias point
must be met during the measurement phase. This is considered to be a part of the pre-tuning. The
optimum point will be later used for all the measurements for this amplifier.
6.2.4.1
Optimum Bias Points
Fig. 6.26.a and Fig. 6.26.b show the measured output power and PAE of the manufactured 100 W
PA as a function of gate and drain bias voltage for three different frequencies (the two edge
frequencies and the centre frequency) and for 40 dBm input power (saturation level), respectively.
The drain voltage was 28 V, as recommended in [56], during the gate bias voltage sweeping.
From Fig. 6.26.a, it is evident that the performances do not degrade by varying the gate voltage
Vgg . For the targeted band, the output power has a maximum variation of less than 0.5 dB. The
variation for PAE is around 3 %. Looking at the PAE vs. the gate voltage, the best bias point that
gives a tradeoff between the PAE and the output power over the bandwidth is −2.9 V (Idq = 650
mA).
Using this bias point, a sweep for drain supply voltage was performed. Fig. 6.26.b shows
110
90
90
100
PAE [%]
Pout [dBm]
Pout_ideal
90
80
PAEideal
80
70
PAErealised
70
Pout_realised
80
1.6
1.7
1.8
1.9
2.0
Freq. [GHz]
(a)
2.1
2.2
2.3
60
1.6
1.7
1.8
1.9
2.0
Freq. [GHz]
(b)
Figure 6.23: Ideal (hollow symbol) and realies from ideal lumped OMN (filled
symbol) for a) output power and b) PAE. The input power was 40 dBm, Vdd =
28 V and Id = 400 mA.
2.1
2.2
60
2.3
114
120
90
100
80
80
70
60
1.6
1.7
1.8
1.9
2.0
2.1
2.2
PAE [%]
Pout [dBm]
6. L and S Band Broadband PA
60
2.3
Freq. [GHz]
Figure 6.24: Simulated output power and PAE performances for different
case temperature (i.e., 25◦ C, 50◦ C and 85◦ C). The input power was 40 dBm,
Vdd = 28 V and Id = 400 mA.
the PAE and the output power behaviour vs. the drain supply voltage Vdd . It is seen that the PAE
varies by less than ±3 % for every frequency point, with a drain voltage variation of 10 V.
Maintaining high PAE over a wide range of drain bias voltages makes the designed amplifier
suitable for supply modulation techniques such as envelope elimination and restoration (EER)
or envelop tracking (ET). After a suitable gate voltage was found, the suitable drain supply
voltage can be found from Fig. 6.26.b to be 28 V for all frequency points. Hence, all subsequent
measurements’ bias point will be Vdd = 28 V and Idq = 650 mA (Vgg = −2.9 V).
6.2.4.2
Small Signal Behaviour
The small signal gain is measured by stimulating the amplifier with very small signals where the
output is measured with a spectrum analyser. The measurement (symbol) and simulated (solid)
results are shown in Fig. 6.27. It can be seen clearly that both measured and simulated results are
in a close fit together. The maximum small signal gain is 16.4 dB at 1.65 GHz, and the minimum
small signal gain is 12.4 dB at 2.25 GHz. This makes a flatness of ±2 dB of small signal gain.
Input
Output
Figure 6.25: Photo of the fabricated broad-band harmonically tuned power
amplifier using 120 W GaN HEMT from Cree Inc.
70
54
70
54
65
52
65
52
@Freq = 1.65 GHz
@Freq = 1.95 GHz
@Freq = 2.25 GHz
60
Vdd = 28 V
Pin = 40 dBm
50
PAE [%]
Pout [dBm]
Pout [dBm]
56
50
55
48
50
46
20
Vgg = −2.9 V
48
-3.5
-3.0
-2.5
-2.0
60
Vgg = −2.9 V
Pin = 40 dBm
@Freq = 1.65 GHz
@Freq = 1.95 GHz
@Freq = 2.25 GHz
PAE [%]
115
6.2 100 W L-Band Power Amplifier
55
Vdd = 28 V
50
24
28
32
36
Drain Voltage, Vdd [V]
Gate Voltage, Vgg [V]
(a)
(b)
Figure 6.26: Measured output power and PAE performances of the designed
PA for different frequency vs.(a) gate bias voltage (b) drain supply voltage.
6.2.4.3
Large Signal Behaviour
Fig. 6.28 shows a comparison between simulation (solid) and measurements (symbol) for output
power, gain, drain efficiency and power added efficiency at the centre frequency of the targeted
band, i.e., 1.95 GHz. From the measurement, the maximum PAE of 64 % with power gain of
10 dB is achieved at output power of 49.8 dBm, where the drain efficiency η is 72 %. The peak
drain efficiency is 75 %, and the peak output power is 50 dBm. However, it is worth mentioning
that the measurements fit the simulations over all the frequency points.
Fig. 6.29.a and 6.29.b show the measured output power, power gain (G p ), PAE and drain
efficiency as a function of frequency for different input power levels, respectively. The measurements show that the 3 dB bandwidth is larger than the designed one and covers 1.55 GHz to
2.35 GHz. With the same targeted centre frequency, i.e., 1.95 GHz, the relative bandwidth is
higher than 41 %. The maximum output power was 50 dBm over the bandwidth with a power
gain of 10 dB.
The worst case PAE of 60 % was achieved in combination with 100 W of output power across
the bandwidth from 1.55 GHz to 2.25 GHz. Best value for PAE is 70 % as was measured.
17
Gss [dB]
16
15
14
Gss_sim
Gss_meas
13
12
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
Freq [GHz]
Figure 6.27: Simulated (solid) and measured (symbol) Small signal gain. The
input power was −20 dBm, Vdd = 28 V and Id = 650 mA.
116
50
100
40
80
30
60
20
40
10
20
0
20
25
30
35
40
Efficiency [%]
Pout [dBm], Gain [dB]
6. L and S Band Broadband PA
0
45
Pin [dBm]
Figure 6.28: Simulated (solid) and measured (symbol) performances at 28 V
drain supply voltage and Id = 650 mA for CW signal at frequency of 1.95 GHz.
In order to improve the output power of the amplifier, post-tuning was implemented. Reducing
the width of some microstrip lines was performed until a maximum power at the centre frequency
is achieved. As a result of this, the output power reached more than 100 W, Fig. 6.30. The
efficiency in this case is degraded by approximately 10 % from the maximum PAE achieved in
Fig 6.29.b.
6.2.4.4
Linearity Measurement
40
80
80
45
30
60
60
35
20
Pin
25
10
15
0
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
40
40
Pin
20
20
0
0
1.6
1.7
1.8
1.9
2.0
Freq. [GHz]
Freq. [GHz]
(a)
(b)
2.1
Figure 6.29: performance over the frequency for different input power i.e.; 22,
27, 32, 37 and 40 dBm for (a) output power (black) and power gain (blue) ,
(b) drain efficiency (green) and power added efficiency (brown). The supply
voltage is Vdd = 28 V and Id = 650 mA.
2.2
2.3
η [%]
55
Gain [dB]
PAE [%]
Pout [dBm]
A WCDMA signal with 8.5 dB peak to average power ratio (PAPR) centered at 2.15 GHz and
5 MHz bandwidth was used as a stimulating signal for the designed power amplifier. Fig. 6.31
shows the measured upper and lower ACLR for different average output power Pout_avg . A
memory polynomial DPD was used to improve linearity and ACLR. An ACLR of more than
40 dBc was achieved with memory polynomial DPD with 38.5 dBm average output power. At
this point, the average drain efficiency was 25 %. The implemented memory polynomial model
117
6.2 100 W L-Band Power Amplifier
Pout [dBm]
120
80
Pout _sat
Pout _3dB
Pout _1dB
40
0
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
Freq [GHz]
Figure 6.30: Performance over the frequency for the post-tuned power amplifier
with different output power levels i.e.; Pout_sat , Pout_3dB and Pout_1dB . The supply
voltage is Vdd = 28 V and Id = 650 mA.
follows the Hyunchul and Kenney model [58]:
m
y(n) =
p
∑ ∑ c2P−1,M |x(n − M)|2(P−1) x(n − M)
(6.9)
M=0 P=1
where x(n) is the input complex base band signal, y(n) is the output complex base band signal,
c p,q are complex valued parameters, m is the memory depth and p is the order of the polynomial.
The polynomial depth used in this DPD was p = 6 and the memory depth m = 2.
-25
ACLR [dBc]
-30
Lower ACLR w/o DPD
Upper ACLR w/o DPD
Lower ACLR w DPD
Upper ACLR w DPD
-35
-40
-45
-50
30
35
40
45
Pout_avg [dBm]
Figure 6.31: Measured upper (red) and lower (black) ACLR without memory
DPD (hollow symbol) and with memory DPD (filled symbol) vs. average output
power at 2.15 GHz operating frequency. The supply voltage is Vdd = 28 V and
Id = 650 mA.
118
6. L and S Band Broadband PA
7|
Conclusion
This work presents different techniques to maintain a highly efficient operation over wide
bandwidth. It was shown that the designed amplifiers are among the state of the art in the last few
years, Table 1.1. Comprehensive studies of different modes of operation are discussed to choose
the best suitable operation for targeted band and applications. After the introductory chapter,
where the motivation and the state of the art comparisons are discussed, three main parts are
presented to give a better overview.
7.1
Thesis Outcome
The first part is the theory work which is discussed in the first two chapters. Chapter two gives
the most important figure of merits of power amplifier design and measurements regarding to this
work. The stability analysis is discussed where the suitable suppression techniques are presented.
Chapter three starts with the key design of any power amplifier, i.e., load line theory and loadpull techniques. Class-A PA design equations were derived from the load line theory. Later in the
chapter, design equations for all classical classes were derived. General closed form equations for
the efficiency and output power were given and analysed. Furthermore, highly efficient classes
were presented in details starting from switch mode power amplifier through harmonic tuning
classes, i.e., Class-J PA, and finally to the mixed mode of operation like Class-E/F PA. In the end
of the chapter, physical limitations from a small signal FET model on the PA performances, in
terms of output power, gain and efficiency, were analysed and discussed. It was shown that the
square of the quality factors of the output parasitic capacitors are the limiting factors of these
performances. However, the input transconductance degrades the performances also because of
the presence of the feedback capacitor (Cgd ).
In the fourth Chapter, two single band power amplifiers working with high efficiency are
demonstrated. The first was designed for UMTS applications, i.e., 2.14 GHz using Class-D−1
power amplifiers. The resonator utilizes the fact that the microstrip DC-feed has small inductance.
The capacitors of the resonator were implemented using wide microstrip stub, and a gap capacitor
120
7. Conclusion
obtained between the ends of these stubs. The input/output-BALUNs were designed from 3-dB
hybrid 90◦ couplers with one λ/4 implemented at one side of the balanced terminal. This PA
showed outstanding results at 50W output power with η and PAE equal to 62.7% and 60.3%,
respectively.
The second amplifier in this chapter is working on 2.45 GHz for ISM applications. The
designed amplifier is working on a Class-F−1 power amplifier. This class requires different
termination for different harmonic. Hence, multi resonator output matching network is designed
to provide the correct termination for each harmonic. The novel technique for this OMN allows
separate harmonic control with an integrated matching for the fundamental frequency. During the
measurements, the maximum performance was observed at 2.35 GHz. An output power of 46
dBm at this frequency was measured with 10 dB power gain. A maximum drain efficiency of
60.8 % (PAE = 55.7 %) was observed at the same frequency. Drain bias voltage was swept to
determine the ability of this amplifier in the envelope elimination and restoration and/or envelope
tracking EER/ET applications. Over 14V of Vdd range down from Vdd = 48 V, the drain efficiency
remained within 4 % of the maximum efficiency level, and the output power within 2.3 dB of the
1 dB compression point.
Chapter five presented the first two broadband power amplifies working in high efficiency
operation. These two amplifiers are working below 1 GHz frequency. The chapter started with the
theoretical limits on designing a broadband PA using Bode-Fano theorem. Furthermore, matching
network design technique, which is implemented for all the designed broadband PAs in this work,
is shown. This technique depends on the understanding of the matching elements movement on
the smitch chart.
A broadband Class-E power amplifier (PA) was presented in this chapter for a frequency range
that covers 250 - 400 MHz using 45 W GaN HEMT from Eudyna. A novel and easy method of
designing broadband Class-E PA was presented. It was shown that a good matching network with
certain considerations followed with a bandpass filter gave a good broadband highly efficient PA.
All the considerations for this design were discussed and presented. Optimum load impedances
were extracted using the load/source-pull simulation, and it was observed that it has a constant
phase over the entire band and a constant negative slope for the magnitude. The drain efficiency
between 63.7 % and 80.3 % and maximum output power with output power from 45.9 dBm to
47.8 dBm, gain flatness: 2.3 dB at the 1 dB compression point, power added efficiency in the
range of 62.5 % - 78.5 %. This amplifier showed a good PA reliability over a wide range of
impedance mismatch and drain supply voltage. It is because of the filter which eliminates any
influences on the performances from any harmonic impedance mismatch.
A second broadband amplifier working on a higher frequency band was, furthermore, discussed in this chapter. It used the same matching network discussed as the preceding PA. The
impedances in this amplifier also have a constant phase over the entire band and a definite negative
slope for the magnitude. Maximum drain efficiency of 87.8 % and peak output power of 46.9 dBm
7.2 Future Work
121
was measured. A 49 W highest output power was achieved with a flatness of 1.7 dB over the
entire band (600 MHz - 1000 MHz).
This PA has minimum drain efficiency which was 66 %. This fluctuation of the measured
drain efficiency requires more clarification. An analysis based on time domain waveforms was
presented. This analysis presented the extraction method of the time domain waveforms. The
analysis was based on two different characteristics at the die reference plane; the time domain
drain current/voltage and the load impedances. A different operational mode over the entire
frequency was the result of this analysis. The PA started from Class-E/F2 PA (i.e.; at 600 MHz)
passing by optimal Class-E PA (i.e.; at 800 MHz) and ending with weak Class-E PA (i.e.; at
1000 MHz). Overall, the broadband PA operation is maintained within the Class-E PA mode of
operation that it is designed for (i.e.; either weakly or strongly).
In chapter six, two power amplifiers working on L and S band were presented. The first one
presented a highly efficient broadband power amplifier with harmonic tuning for a 10 W GaN
HEMT transistor. Studying the harmonic impedances effect on the output power and the efficiency
makes it easy to realize the broadband matching network that gives adequate performance. Drain
efficiency and PAE between 71 % and 84 % and between 58.5 % and 78.0 %, respectively, was
achieved across the bandwidth between 1.5-2.7 GHz (60 % BW at 2.125 GHz center frequency)
at 3 dB compression point, Pout is 40 dBm ±1.5 across this band. An ACPR of -36 dBc with
35 dBm Pout_avg and 35 % ηavg was found by sweeping the drain supply voltage and the bias
point for a typical WCDMA signal with 8.51 dB PAR centered at 2.15 GHz.
The second amplifier presented in this chapter is a broadband power amplifier centered at
1.95 GHz with relative bandwidth of 41 %. Harmonic termination is designed using 3-poles
output matching network. The realized output matching network is using step impedances. This
network fits the optimum load impedance obtained from the load-pull data as well as an initial
lumped element output matching network very well. The PA is fabricated using a 120 W GaN
HEMT device from Cree Inc. Worst case PAE of 60 % was achieved in combination with 100W
of output power across the bandwidth from 1.55 GHz to 2.25 GHz. PAE best values up to 70 %
was measured. Using an UMTS input signal, more than 40 dBc ACLR can be achieved with
memory DPD for an average output power up to 38.5 dBm.
7.2
Future Work
These broadband power amplifiers give a good starting point for multi-standard applications.
However, most of these standards require high average drain efficiency with good linearity
performance. Hence, different techniques can be used to investigate the PA for these standards.
These can include (but not restrictively):
• Harmonic injection concept which aims for an improvement of the efficiency of RF power
amplifiers showed good results as shown in [Paper N]. For that purpose a triplexer is
122
7. Conclusion
designed, which allows combining the fundamental signal at 2.6 GHz with the respective
second and third harmonic. This component is used to study the effect of the second
harmonic injection on the efficiency of a 25 W GaN HEMT device. It is shown that,
choosing the correct injection phase and power level, the efficiency of the device can be
improved by up to 6 % compared with the classic Class-AB operation without harmonic
injection.
• Broadband Doherty PA (DPA) is one of the optimistic solutions in terms of efficiency and
linearity. However, a broadband impedance transformer is the bottle neck for the DPA.
• Source and load modulation using a variable lumped elements is a unique method to
increase the efficiency over a wide range of the input power. However, because it changes
the source impedance it can keep the linearity as high as possible during high efficiency
operation. This technique, ideally, can give high efficiency over 20 dB output power back
off.
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List of Publications
[Paper A] A. Al Tanany, A. Sayed, and G. Boeck, “Broadband GaN switch mode class E power
amplifier for UHF applications,” in Microwave Symposium Digest, 2009. MTT ’09.
IEEE MTT-S International, 2009, pp. 761–764.
[Paper B] A. Al Tanany, D. Gruner, A. Sayed, and G. Boeck, “Highly efficient harmonically
tuned broadband GaN power amplifier,” in Microwave Integrated Circuits Conference
(EuMIC), 2010 European, 2010, pp. 5–8.
[Paper C] A. Al Tanany, D. Gruner, and G. Boeck, “Harmonically tuned 100 W broadband
GaN HEMT power amplifier with more than 60% PAE,” in Microwave Conference
(EuMC), 2011 41st European, 2011, pp. 159–162.
[Paper D] A. Al Tanany, A. Sayed, and G. Boeck, “A 2.14 GHz 50 Watt 60% Power Added
Efficiency GaN Current Mode Class D Power Amplifier,” in Microwave Conference,
2008. EuMC 2008. 38th European, 2008, pp. 432–435.
[Paper E] A. Al Tanany, A. Sayed, and G. Boeck, “Design of Class F−1 Power Amplifier Using
GaN pHEMT for Industrial Applications,” in German Microwave Conference, 2009,
2009, pp. 1–4.
[Paper F] A. Al Tanany, A. Sayed, O. Bengtsson, and G. Boeck, “Time domain analysis
of broadband GaN switch mode class-E power amplifier,” in German Microwave
Conference, 2010, 2010, pp. 254–257.
[Paper G] A. Al Tanany, A. Sayed, and G. Boeck, “Analysis of Broadband GaN Switch Mode
Class-E Power Amplifier,” Progress In Electromagnetics Research Letters, vol. 38,
pp. 151–160, 2013.
[Paper H] A. Sayed, A. Al Tanany, and G. Boeck, “20 W Class A Power Amplifier for Wideband,” in Microwave Conference (GeMIC), 2008 German, 2008, pp. 1–4.
[Paper I] A. Sajjad, A. Sayed, A. Al Tanany, and G. Boeck, “10 W Class AB power amplifier
design for UMTS applications using GaN HEMT,” in Radio Science Conference,
2009. NRSC 2009. National, 2009, pp. 1–8.
[Paper J] A. Sayed, A. Al Tanany, and G. Boeck, “5W, 0.35-8 GHz linear power amplifier
using GaN HEMT,” in Microwave Conference, 2009. EuMC 2009. European, 2009,
pp. 488–491.
128
LIST OF PUBLICATIONS
[Paper K] D. Gruner, R. Sorge, O. Bengtsson, A. Al Tanany, and G. Boeck, “Analysis, Design,
and Evaluation of LDMOS FETs for RF Power Applications up to 6 GHz, ” Microwave Theory and Techniques, IEEE Transactions on, vol. 58, no. 12, pp. 4022–
4030, 2010.
[Paper L] A. Sayed, A. Sajjad, A. Al Tanany, O. Bengtsson, and G. Boeck, “Comparative
analysis of RF wide bandgap technologies for UMTS applications,” in German
Microwave Conference, 2010, 2010, pp. 126–129.
[Paper M] D. Gruner, K. Bathich, A. Al Tanany, and G. Boeck, “Harmonically tuned GaNHEMT Doherty power amplifier for 6 GHz applications,” in Microwave Integrated
Circuits Conference (EuMIC), 2011 European, 2011, pp. 112–115.
[Paper N] A. Al Tanany, D. Gruner, F. Goelden, K. Bathich, R. Kahl, and G. Boeck, “Efficiency
improvement for RF power amplifiers by employing harmonic injection at the input,”
in Microwave Conference (GeMIC), 2011 German, 2011, pp. 1–4.