Bipolar Transistor Structures
Modern Si/SiGe Bipolar Transistors
Vertical current Super Selfaligned Transistors (SST)
SOI Lateral bipolar
Transistors (LBT)
Department of Electronics, Microelectronics, Computer and Intelligent Systems
SST Structures - Advantages
Mainstream Si/SiGe bipolar technology,
Optimized intrinsic region, high electrical performance:
fT, GHz fmax, GHz
Si
54
65
SiGe 200-300 200-300
Department of Electronics, Microelectronics, Computer and Intelligent Systems
1
SST Structures - Limitations
Large volume of parasitic regions:
COLLECTOR
CONTACT
BASE
CONTACT
EMITTER
INT. EMITTER
INT. BASE
INT. COLLECTOR
ABE/ACS=1-4 %,
high CBC, CCS, RB,
fT(IC),
complicated technology.
Scaling limitations due to the vertical current flow:
trench isolation, perimeter depletion effect
Department of Electronics, Microelectronics, Computer and Intelligent Systems
Lateral Bipolar Transistors (LBT)
Silicon-on Insulator (SOI) LBT
SOI LBT:
• Simple technology,
• Reduced capacitances,
• Compatible with thin-body
silicon SOI CMOS technology.
LBT
fT, GHz fmax, GHz
3-16
15-67
High fmax => reduced CBC.
Low-power and/or SOI BiCMOS
applications.
Low fT => wide base, unoptimized
geometry and doping profile.
Department of Electronics, Microelectronics, Computer and Intelligent Systems
2
HCBT Structure - Advantages
A novel Horizontal Current Bipolar Transistor (HCBT) is introduced:
Advantages:
• optimized doping profiles,
• low CBC and CCS,
• scaling possibilities,
• simple technology:
–
–
–
–
–
P. Biljanovic, T. Suligoj, et al, IEEE Trans.
ED, vol. 48, p. 2551, 2001.
single poly,
no epitaxy, no buried layer,
5 masks,
no trench processing,
reduced etch and high-temp.
steps,
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Technology
• 0.5 µm - lithography resolution,
• 0.1 µm - alignment margins.
nitride
n-implanted
<110> p-substrate
n-hill
p-channel
stopper
nitride
<111>
sidewalls
<110> p-substrate
<110> wafer as substrate
• n-hill implantation,
• annealing,
• buffer oxidation,
• nitride deposition,
1st mask
• n-hill etching – RIE + TMAH,
• P-channel stopper
implantation,
<111> defect-free, smooth
sidewalls
Department of Electronics, Microelectronics, Computer and Intelligent Systems
3
HCBT Technology (cont’d)
after CMP
CVD oxide
nitride
<111>
sidewalls
n-hill
p
•
•
•
CVD oxide deposition,
Densification,
Chemical-mechanical
Planarization (CMP),
<110> p-substrate
n-hill
hT
isolation SiO2
<110> p-substrate
• Etch-back
n-hills are separated by
isolation oxide,
hT: active transistor height.
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Technology (cont’d)
ext. base I/I
int. base I/I
photoresist p+
hT
p isolation SiO2
<110> p-substrate
after CMP
n+polySi
p+
p
2nd mask
• Extrinsic base implantation,
30°,
• Intrinsic base implantation,
-40°,
Specific base shape,
•
•
Polysilicon deposition,
CMP
<110> p-substrate
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HCBT Technology (cont’d)
n+polySi
p+
p
• Polysilicon etch-back,
3rd mask
• Polysilicon etching
hE: emitter height.
hE
<110> p-substrate
COLLECTOR
n+polySi
BASE
EMITTER
• Passivation oxide deposition,
• Annealing, RTA 1050°C,
4th mask
• Contacts etch
5th mask
• Metallization
hE
SiO2
<110> p-substrate
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Technology (cont’d)
HCBT key process parameters:
HCBT A
HCBT B
Active height, hT
0.52µm
0.75µm
Emitter height x length
(hExlE)
0.21 x 5 µm2
0.38 x 5 µm2
Collector I/I dose, @
200keV
6·1013 cm-2
4.5·1013cm-2
Collector annealing, N2
Channel stopper I/I, 0º
1050ºC, 150’
BF2, 6·1013
cm-2
-
14
14
-2
Int. base I/I, BF2
3·10 cm ,
20keV, 35º
2.3·10 cm-2,
33keV, 30º
Base annealing, RTA
1050ºC, 30”
900ºC, 30” +
1030ºC, 35”
Department of Electronics, Microelectronics, Computer and Intelligent Systems
5
HCBT Technology
Scaled HCBT is successfully processed in <110> wafers
N-hill width:
Extrinsic base width:
Emitter height (hE):
0.58 µm
<0.3 µm
0.38 µm
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Electrical Characteristics
Gummel plots of a typical HCBT structure
-2
10
-3
Collector, Base Current (A)
10
-4
1x10
Base current ideality factor ≈1
HCBT
2
S E=0.38 x 5 µm
V CE =2 V
Low-defect-density sidewalls,
High quality interface with
isolation oxide
-5
1x10
-6
10
IC
-7
10
-8
10
IB
Max. current gain = 75
-9
10
10
-10
0.4
0.6
0.8
1.0
Base-Emitter Voltage (V)
1.2
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6
HCBT Electrical Characteristics
Output characteristics of HCBT structure
2.0
BVCBO (V)
Collector Current (mA)
∆I B=5 µ A
1.5
10.8
BVCEO (V)
5.6
VA (V), IB=5 µA
7.8
1.0
0.5
0.0
BVCEO
0
1
2
3
4
5
Collector-Emitter Voltage (V)
6
CBC (fF) @ 0 V
16
CBE (fF) @ 0 V
18
RB (Ω)*circle
imp. meth.
120
RE (Ω)
63
RC (Ω),
saturation
530
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Electrical Characteristics
fT and fmax vs. IC of HCBT Structure
40
35
Frequency (GHz)
30
VCE =3V:
fT
f max
Peak fT (GHz),
VCE=5 V
25
20
15
VCE =5V:
fT
f max
10
23.5
Peak fmax (GHz),
VCE=5 V
36
JC @ peak fT
(µA/µm2)
165
fTBVCEO (GHzV)
131.6
5
0
-8
10
10
-7
-6
-5
-4
10
1x10
1x10
Collector Current (A)
10
-3
10
-2
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HCBT Process Analysis - N-hill Etching
Sidewall roughness
Horizontal roughness
Vertical roughness
Time multiplexed DRIE
process
Photoresist edge
roughness
RIE etch profile
Mass transport of etched
species
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Process Analysis - N-hill Etching
Lithography optimization for sidewall roughness minimization
Unoptimized Lithography
Optimized Lithography
Hardbake: 130 °C, 6’,
no descum, 3000 rpm.
Hardbake: 150 °C, 5’ ,
descum, 5000 rpm.
6-05-a1
6-18-51
Hardbake cannot be afforded in every process; still not perfectly flat
Department of Electronics, Microelectronics, Computer and Intelligent Systems
8
HCBT Process Analysis - N-hill Etching
Roughness by lithography and DRIE optimization: ≈10-80 nm,
Base width of HCBT: ≈60-150 nm,
Emitter depth: ≈20-50 nm.
Still too rough for high-performance bipolar and MOS transistors !!
Solution: Usage of Crystallographic etches (e.g. KOH, TMAH, EDP):
•
High selectivity between
<111> and <100> crystal
planes: from 60:1 to 120:1.
•
The usage of <110>
wafers: <111> plane is
perpendicular to surface.
8-4-3b1
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Effects Analyses
HCBT n-collector doping:
Collector doping process:
18
4.5·1013cm-2, 200keV implant.
+
1050°C, 150 min. annealing.
-3
N-hill doping (cm )
10
HCBT
active transistor region
17
10
16
10
vertical doping
profile
p-substrate
-
High collector doping:
-
15
10
-
n-hill
Kirk effect pushed to
higher currents,
high fT,
14
10
0.0
0.5
1.0
1.5
Depth (µm)
n+polySi
SiO2
p-substrate
Vertical doping in the n-hill
Department of Electronics, Microelectronics, Computer and Intelligent Systems
9
HCBT Simulation Analyses
High breakdown achieved despite high collector doping:
Collector-base electric field shielding by extrinsic base
HCBT narrow ext. base
HCBT long ext. base
Lower breakdown voltage
Higher breakdown voltage
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Simulation Analyses
5
Total Electric Field (10 V/cm)
14
C-B depletion region
12
1.5
HCBT with:
No ext. base
Ext. base
1.0
10
8
6
4
Neutral
Collector 2
0.5
0.0
0.1
0.2 0.3 0.4 0.5 0.6 0.7
Distance from Emitter (µm)
0
0.8
3
23
16
2.0
Impact Ionization Rate (10 pairs/(cm /s))
E-field of HCBT structure with and without ext. base:
Peak E-field reduced in HCBT
with ext. base:
Shielding effect
Lower impact ionization rate
Increased BVCEO
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10
HCBT Simulation Analyses
Maximum E-field of HCBT structure vs. ext. base width:
7.0
7.0
VCE=2 V
VCE=6 V
VCE=10 V
6.0
w bext=0.2 µm
w bext=0.5 µm
VBE=0.1 V
6.5
Electric Field (10 V/cm)
5.5
5
5
Electric Field (10 V/cm)
6.5
5.0
4.5
4.0
3.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
0.2
0.4
0.6
0.8
3.0
1.0
2
4
6
w bext (µm)
8
10
VCE (V)
Peak E-field reduced for ext.
base width wbext>0.3 µm
The larger wbext, the larger
max. E-field =>
Increased BVCEO by 1.7 V
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT Simulation Analyses
Old HCBT Process: (1 µm / 1 µm) Technology:
wext
n+ poly Si
p-chan.stop.
p+
n-hill
oxide
p-substrate
fT and fmax limited by the wide
ext. base.
Frequency, GHz
50
40
f T, 1 V
f T, 3 V
f max, 1 V
f max, 3 V
narrower
intrinsic base
30
measured
20
10
0
0,0
0,5
1,0
1,5
2,0
2,5
3,0
Extrinsic Base Width, µ m
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11
HCBT Process Scaling
Reduction of n-hill and extrinsic base widths should improve HCBT characteristics:
Scaling
<1µm
5µm
3µm
n+ poly Si
n-hill
p-chan.stop.
p+
<0.5µm
n+polySi
oxide
SiO2
p-substrate
<110> p-substrate
T. Suligoj, et al, IEEE Trans. ED, vol. 50, p. 1645, 2003.
N-hill width:
Extrinsic base width:
fT
fmax
BVCEO
fTBVCEO
This work
5 µm
Scaling
5 µm
4.2 GHz
12 GHz
15.5 V
65.1 GHzV
<1 µm
<0.5 µm
23.5 GHz
35 GHz
5.6 V
131.6 GHzV
Department of Electronics, Microelectronics, Computer and Intelligent Systems
HCBT vs. SOI LBTs
HCBT vs. SOI Lateral Bipolar Transistors (LBT):
10
Ref.[3]
BVCEO (V)
Ref.[4]
Ref.[2]
Ref.[1]
HCBT
HCBT:
The highest absolute fT (23.5 GHz),
and fTBVCEO (131.6 GHzV) !!
Ref.[5]
Among SOI LBTs
SOI LBT
HCBT
1
120 GHzV
100 GHzV
80 GHzV
60 GHzV
10
fT (GHz)
[1] H. Nii, et al, IEEE Trans. ED, vol. 47, p. 1536, 2000.
[2] R. Dekker, et al, IEDM Tech. Dig., p. 75, 1993.
[3] T. Shino, et al, , IEDM Tech. Dig., p. 953, 1998.
[4] M. Kumar, et al, IEEE Trans. ED, vol. 49, p. 200, 2002.
[5] W.-L. M. Huang, et al, IEEE Trans. ED, vol. 42, p. 506, 1995.
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12
HCBT vs. SST BJT’s
HCBT vs. vertical-current Super Self-Aligned bipolar Transistors (SST)
HCBT:
Comparable with state-of-art Si
BJT’s !!
HCBT Characteristics can be
improved further by using SiGe
base !!
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13