DIE
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S h d l Schedule 02. 09/22/16 Chapter 5 (Memory types, Set-up & hold time) 03. 09/29/16 Chapter 5 (Memory devices: Latch, FF, & ROM) 04. 10/06/16 Chapter 5 (Memory devices: RAM , Clock skew) 05. 10/13/16 Chapter 5 (Memory timing and clock, Testing) 06 10/20/16 (QZ1) Chapter 06. Ch t 5 (Sequential machine, State graph) 07. 10/27/16 Packaging g g 08. 11/03/16 Midterm Examination VLSI Design : Package 1 Midterm Examination Next Week!! 35% Please Bring Your Photo ID !! Covered Chapter 5 to Today’s material S t will Seats ill be b rearrangedd VLSI Design : Package 2 P k i Packaging Functional: Signal and Power connections Make possible for the next level connections Provide adequate protection (mechanical and environmental) Electrical: Low parasitic Thermal Removal: Efficient heat removal Mechanical: Reliable and robust Economical: Cheap (material and manufacture throughput) VLSI Design : Package 3 M i l Materials Metal -- Signal connection -- Heat conductivity C Ceramic i -- Expensive -- Physical characteristics Plastic -- Cheap -- Physical characteristics (heat……) VLSI Design : Package 4 Design Layout Package Masks Wafer Photolithographic Process P k i Fl Packaging Flow Chi Chips Wafer => Wafer Probe (WP) => Dicing => Bonding => Packaged => >B Burn-in, i Final Fi l Test T t (FT) VLSI Design : Package 5 Appearance ( DIE ) Lead Frame Chip Lead Frame VLSI Design : Package 6 Design Layout Package Masks Wafer Photolithographic B di Bonding Process Chips Chi Wire Bonding Wire Substrate Die Pad Lead Frame VLSI Design : Package 7 TAB (T (Tape-Automated A dB Bonding) di ) Sprocket hole Film + Pattern Solder Bump Die Test pads Lead frame Substrate (b) Die attachment using solder bumps. Polymer y film (a) Polymer Tape with imprinted wiring pattern. VLSI Design : Package 8 VLSI Design : Package 9 R Requirement i t ffor Q Qualification lifi ti Testing Items Conditions Criteria (Target) =================================================================================== High Temp. Operating Life 125deg.C/VCC abs max r=0@1,000hr Low Temp. Operating Life -40deg.C/VCC abs max r=0@1,000hr High Temp. Storage 150deg.C r=0@1,000hr deg.C [*3] Low Temp. Storage -65 r=0@1,000hr Temp. Humidity with Bias [*1] 85deg.C/85%RH/VCC r=0@1,000hr deg.C %RH HAST [*1] 130 /85 r=0@100hr (r=0@500hr) Temp. e p Cyc Cycling g [[*1]] -65/150 65/ 50deg.C r=0@100 0@ 00cy ((r=0@1,000 0@ ,000cy) Heat Shock [*1] -65/150deg.C r=0@15cy (r=0@100cy) deg.C sec % Solderability 245 /5 more than 95 soldering ESD Immunity HBM +/-2,000V MM +/-200V CDM +/ 1 000V as JEITA +/-1,000 (+/ 1 500V) (+/-1,500 Corner:+/-750V, Other:+/-500V as ESDA Latch-up Immunity PCIM +/-125mA as JEITA&JEDEC [*4] (+/-150mA) PSOV VCC abs max.as JEITA&JEDEC Package Immunity [*2] No delamination & no cracking [*5] =================================================================================== [*1] Pre-conditioning : for SMD : Bake(125deg.C/24hr) Soak(30deg.C/70%RH/240hr) Re-flow [*2] for THD : Soldering heat (260deg.C/10sec), immersed to stopper [*2] Re-flow profile : according to JEDEC profile, SMD only [[*3]] Renesas condition : -40deg.C [*4] Renesas criterion : +/-100mA [*5] Refer to next page VLSI Design : Package 10 C it i for Criteria f Package P k Immunity I it <<Top View>> Outer lead <<Cross-section View>> Inner lead Chip Wire Molding VLSI Design : Package Acceptable delamination area 11 C Cross-section i di die Gold / Copper Wire Wafer backside grinding Silver Epoxy Die Pad Lead Frame Coating: 10% Pb, 90% Ti Buffer for different thermal expansion coefficients VLSI Design : Package 12 Design Layout Package Masks Wafer Photolithographic Process P k Package and dH Heat Chi Chips Package types: – Plastic: – Ceramic: – Special: VLSI Design : Package Below 1 watt Below 5 watt Up to 30 watt 13 CIP / SIP PKG Thickness (Min): 2.05mm 80mil 12 mil Min. 30 mil Min. 12mil il Max DIE 2 : 10mil 8 mil Min. DIE 1 : 10 mil BLT 1 0.2~1.4 mil VLSI Design : Package L/F thickness : 0.15mm 6mil BLT 2 (1~2 mil) 14 MCM (M (Multi-Chip l i Chi Module) M d l ) dies The module f il d if failed, any die failed VLSI Design : Package 15 MCM Size and weight Better performance: Decrease loading of external signals Reduce packaging cost of individual chips Yield Problem: (will increase the cost) – If Single chip faults: 5% – MCM yield i ld with i h 10 chips: hi (0.95) (0 95)10 = 60% Heat density problem VLSI Design : Package 16 Design Package Layout Masks Wafer Chi Chips Photolithographic Fli Chip Flip Chi Process Di Die Solder bumps Interconnect layers Substrate VLSI Design : Package 17 COF D I CL VLSI Design : Package 96.36 9 F 88.5 G A C E CL 18 S f PCB Soft VLSI Design : Package 19 W f Level Wafer L l Packaging P k i VLSI Design : Package 20 WLP Dallas Semiconductor Wafer Level Package VLSI Design : Package 21 What is a 3D IC? Could be Heterogeneous… VLSI Design : Package “Stacked” 2D (Conventional) ICs 22 VLSI Design : Package 23 Th Thermal l Dissipation Di i i 15 ~ 20 % (with heat sink 40 ~ 75%) 5 ~ 10 % (about the same) VLSI Design : Package 70 ~ 80 % (25 ~ 50%) 24 P Prepackaging k i Flow Fl I VLSI Design : Package 25 P Prepackaging k i (1) 於 wafer 正面貼上研磨膠 紙 避免刮傷或污染 研磨 wafer 被面 VLSI Design : Package 26 P Prepackaging k i (2) 撕下wafer 正面研磨膠紙 避免留下任何殘留 於 wafer afer 被面貼上切割膠紙 以避免切割時晶粒飛濺 VLSI Design : Package 27 P Prepackaging k i (3) 於 wafer 正面切割 wafer 切割膠紙並未切斷 照射 照射UV 軟化切割膠紙的 黏性 VLSI Design : Package 28 P Prepackaging k i Flow Fl II VLSI Design : Package 29 P Prepackaging k i (3) VLSI Design : Package 30 Gl R Glue Requirements i Thickness: > 0.2mils 80% on each side and < 0.2mm Overflow < 2/3 of the die thickness Tilt < 2 mils il VLSI Design : Package Bubble area < 15% 31 E Example l VLSI Design : Package 32 Di C Die Cracking ki VLSI Design : Package 33 R li bili Reliability Different applications * Medical parts * Transportation components * 3C parts t * Gifts, toys Testing items * Thermal shock, shipping, vibration, humidity, chemical * Over Life time , burn-in VLSI Design : Package 34 P Prepackagingk i B di Bonding VLSI Design : Package 35 G ld Wire Gold Wi VLSI Design : Package 36 VLSI Design : Package 37 晶片邊緣與晶片座的間距 VLSI Design : Package 38 內部鋁墊與晶體邊緣的距離 為避免金線與晶體邊緣短路，最長線長應被考慮，且與模 流方向有關係 VLSI Design : Package 39 銲墊設計 VLSI Design : Package 40 金線弧高設定 有接地線 交錯鋁墊 VLSI Design : Package 41 VLSI Design : Package 42 銲墊設計 VLSI Design : Package 43 VLSI Design : Package 44 I Inner L Leadd Short Sh CWT QFP64(14*14) VLSI Design : Package 45 L d Frame Lead F Tape T VLSI Design : Package 46 L d Frame Lead F Tape T VLSI Design : Package 47 耗材 金線 99.99% Holding Clamps 熱壓版 Capillary 針頭 VLSI Design : Package 48 阻抗 VLSI Design : Package 49 B di Analysis Bonding A l i VLSI Design : Package 50 D f Defects VLSI Design : Package 51 D f Defects VLSI Design : Package 52 D f Defects (Fli (Flip Chip) Chi ) VLSI Design : Package 53 P Post-packaging k i - Molding M ldi 175 degree C preheat VLSI Design : Package 54 D j k and Dejunk dT Trimming i i Dam Bar D j k Dejunk VLSI Design : Package 55 F Forming i VLSI Design : Package 56 M k/L Mark Labling bli Ink Mark: Delivered the information including manufacture, product type, design g code,, or team,, revision,, date,, area,, tracking special codes Laser Mark: Used in tiny packages or for the environmental protection VLSI Design : Package 57 Pi h Pitch Center 2 center VLSI Design : Package 58 B di Options Bonding O i Wire Bonding: ~ 1000 connections TAB: 10 ~ couple 1000 connections Flip Chip: ~ 10000 connections VLSI Design : Package 59 Testing for Active/Passive D i Devices Active Devices: MOSs Transistors Related to function (and timing) Passive Devices: RLC Related to timing (and function) VLSI Design : Package 60 Design Layout Package Masks Wafer Photolithographic Process T Types Chips Chi DIP QFP SOP PGA PLCC VLSI Design : Package 61 VLSI Design : Package 62 P6: Processor + L2 cache VLSI Design : Package 63 Intel Itanium VLSI Design : Package 64 Design P k Package Layout Masks W f Wafer Photolithographic P Process Chips CQFP, PQFP BGA VLSI Design : Package 65 List of Acronyms VLSI Design : Package P-DIP PLCC QFP SOP SSOP TSOP SOJ LQFP TQFP Plactic Dual In-line Package p Carrier Plastic Leaded Chip Quad Flat Pack Small Outline Package Shrink Small Outline Package Thin Small Outline Package Small Outline J-lead package Low-profile Quad Flat Pack Thin Quad Flat Pack BGA TFBGA VFBGA LBGA BCC COS BGA uBGA MCM BGA LGA MCC QFN TCP WLCSP WFBGA Ball Grid Array Thin & Fine-pitch Ball Grid Array Very-thin & Fine-pitch Ball Grid Array Low-profile Ball Grid Array Bumped Chip Carrier Chip On Substrate Ball Grid Array Micro Ball Grid Array M lti Chip Multi Chi Module M d l Ball B ll Grid G id Array A Land Grid Array Micro Chip Carrier Quad Flat No-lead Tape Carrier Package Wafer Level Chip Scale Package Very Very-thin & Fine-pitch Ball Grid Array 66 Diff Different P Packages k TO: (before 70’s) ZIP: Zig-Zag Zig Zag In-Line In Line Package SIP Single In-Line Package DIP: Dual In-Line Package (early 70 70’s) s) SOP: Small Outline Package SOJ: Small Outline JJ-lead lead PLCC: Plastic Leaded Chip Carrier QFP: Q Q Quad Flat Package g ((late 70’s)) PGA: Pin Grid Array (mid 70’s) BGA: Ball Grid Array (mid 80’s) VLSI Design : Package 67 Thi k Thickness SOP/SOJ: 1.47/2.24/2.34 mm TSOP: 1.0mm Q 2.0~3.4mm PQFP: LQFP: 1.4mm TQFP: 11.0mm 0mm DIP: 3.3/3.8mm PGA/BGA: 0.8/0.9/1.17mm Mini BGA:0.7mm VLSI Design : Package 68 Cost Cost C PGA C-PGA P PGA P-PGA QFP VLSI Design : Package Pin count 69 P k i T Packaging Technologies h l i VOLUME VO U Surface Mount Thru Hole DIP Pin Grid 1960 QFP TSOP SOJ BGA 1980 Chip Scale CSP Wafer Level Stacked Die SiP 2000 YEAR VLSI Design : Package 70 IC Package 24L PDIP VLSI Design : Package 48L PDIP PGA 71 IC Package 48SOIP VLSI Design : Package 84PLCC 208QFP 72 IC Package 196BGA VLSI Design : Package 432EBGA 73 Diff Different T Technologies h l i Surface Mount Through Hole CSP / WLP CSP/WLP TSOP Area array 0.8 mm to 0.5 mm Limited by substrate wiring 25 mil pitch Limited by perimeter leads DIP 100 mil pitch Limited by through hole spacing VLSI Design : Package 74 D i i Forces Driving F Mobile Computation: -- Miniaturization g Lightening g g -- Weight -- Performance -- Larger dice -- Cost VLSI Design : Package 75 D l Delay Timing Packaging Delay Die Delay Process Tech VLSI Design : Package 76 Design Package Layout Masks Wafer Photolithographic Diff Different P Packaging k i Fl Flow Process Chi Chips Wafer Probe (WP) => Dicing Bonding => Packaged => Burn-in …… Bonding => Packaged => Burn-in …… Bonding => > Packaged => > Burn-in …… Wafer f Packaging k i => Wafer f Burn-in i => FT => Dicing i i VLSI Design : Package 77 Design Package Layout Masks Wafer Photolithographic Process LC on the h Package P k Chips Chi VLSI Design : Package 78 Design Package Layout Masks Wafer Photolithographic Process RLC on the h Package P k Chips Chi VLSI Design : Package P Parameter t Wi b d Wirebond TAB Resistance 0.38mΩ 0.31mΩ Inductance 10nH 6.7nH Capacitance 0.21pF 0.11pF 79 Design Package Layout Masks Wafer Photolithographic Process El i l Characteristics Electrical Ch i i Chips Chi Basic characteristeristics Wire resistance, contact resistance Wire inductance Loading capacitance All elements of the package are included Noise imutation VLSI Design : Package 80 A Assembly: bl Soldering S ld i Temp. 200 C 215 ~ 220 C S k Soak 100 C Max 120 S Max. Pre Heat Pre-Heat + 2 ~ 3 C/sec VLSI Design : Package Max. 90 S Cool - 3 ~ 4 C/sec Time 81 Fli Chip Flip Chi Failure F il Solder migration causes signals shortage or open VLSI Design : Package 82 Ch ll Challenges Probe Density, Pin count (force and contact alignment) p Testingg Speed Electrical characteristics of probing pins Burn in test Burn-in OLT test Environment change g g of wafer fabrication and ppackaging g g Merging VLSI Design : Package 83 Midterm Examination Next Week!! 35% Please Bring Your Photo ID !! Covered Chapter 5 & Packaging S t will Seats ill be b rearrangedd VLSI Design : Package 84