ON Semiconductor
Low Input Offset, High Slew
Rate, Wide Bandwidth, JFET
Input Operational Amplifiers
The MC33282/284 series of high performance operational amplifiers are
quality fabricated with innovative bipolar and JFET design concepts. This
dual and quad amplifier series incorporates JFET inputs along with a
patented ZIP R TRIM element for input offset voltage reduction. These
devices exhibit low input offset voltage, low input bias current, high gain
bandwidth and high slew rate. Dual–doublet frequency compensation is
incorporated to produce high quality phase/gain performance. In addition,
the MC33282/284 series exhibit low input noise characteristics for JFET
input amplifiers. Its all NPN output stage exhibits no deadband crossover
distortion and a large output voltage swing. They also provide a low open
loop high frequency output impedance with symmetrical source and sink AC
frequency performance.
The MC33282/284 series are specified over –40° to +85°C and are
available in plastic DIP and SOIC surface mount packages.
• Low Input Offset Voltage: Trimmed to 200 µV
•
•
•
•
•
•
•
•
•
•
•
•
MC33282
MC33284
HIGH PERFORMANCE
OPERATIONAL AMPLIFIERS
SEMICONDUCTOR
TECHNICAL DATA
DUAL
8
1
8
1
P SUFFIX
PLASTIC PACKAGE
CASE 626
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO–8)
PIN CONNECTIONS
Low Input Bias Current: 30 pA
Low Input Offset Current: 6.0 pA
Output 1 1
High Input Resistance: 1012 Ω
2
Low Noise: 18 nV √ Hz @ 1.0 kHz
Inputs 1
High Gain Bandwidth Products: 35 MHz @ 100 kHz
3
High Slew Rate: 15 V/µs
+
1
2
VEE 4
Power Bandwidth: 175 kHz
Unity Gain Stable: w/Capacitance Loads to 300 pF
8
VCC
7
Output 2
-
6
+
5
Inputs 2
(Top View)
Large Output Voltage Swing: +14.1 V/–14.6 V
Low Total Harmonic Distortion: 0.003%
QUAD
Power Supply Drain Current: 2.15 mA per Amplifier
Dual Supply Operation: ±2.5 V to ±18 V (Max)
14
1
14
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
1
P SUFFIX
PLASTIC PACKAGE
CASE 646
PIN CONNECTIONS
ORDERING INFORMATION
Op Amp
Function
Device
Operating
Temperature Range
MC33282D
Dual
Quad
SOP–8
MC33282P
MC33284D
Output 1
Package
Plastic DIP
TA = –40°
40° to +85°C
MC33284P
SO–14
Plastic DIP
2
Inputs 1
14 Output 4
1
3
1
+
+
4
Output 2
5
6
12
Inputs 4
11 VEE
VCC 4
Inputs 2
13
+
2
-
3
+
-
10
9
Inputs 3
8 Output 3
7
(Top View)
 Semiconductor Components Industries, LLC, 2002
March, 2002 – Rev. 1
1
Publication Order Number:
MC33282/D
MC33282 MC33284
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VS
+36
V
Input Differential Voltage Range
VIDR
(Note 1)
V
Input Voltage Range
VIR
(Note 1)
V
Output Short Circuit Duration (Note 2)
tSC
Indefinite
sec
Maximum Junction Temperature
TJ
+150
°C
Storage Temperature
Tstg
– 60 to +150
°C
Maximum Power Dissipation
PD
(Note 2)
mW
Supply Voltage (VCC to VEE)
NOTES: 1. Either or both input voltages should not exceed VCC or VEE.
2. Power dissipation must be considered to ensure maximum junction temperature
(TJ) is not exceeded (see Figure 2).
DC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Input Offset Voltage (RS = 10 Ω, VCM = 0 V, VO = 0 V)
TA = +25°C
TA = –40° to +85°C
Average Temperature Coefficient of Input Offset Voltage
RS = 10 Ω, VCM = 0 V, VO = 0 V, TA = Tlow to Thigh
Symbol
Figure
|VIO|
3
|∆VIO|/∆T
Input Bias Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = –40° to +85°C
IIB
Input Offset Current (VCM = 0 V, VO = 0 V)
TA = +25°C
TA = –40° to +85°C
IIO
Min
Typ
Max
—
—
0.2
—
2.0
4.0
—
15
—
–200
–2.0
30
—
200
2.0
pA
nA
–100
–1.0
6.0
—
100
1.0
pA
nA
–11
—
–12
+14
—
+11
V
50
25
200
—
—
—
13.2
—
13.7
—
+13.7
–13.9
+14.1
–14.6
—
–13.2
—
–14.3
70
90
—
75
100
—
15
—
+21
–27
—
–15
—
—
2.15
—
2.75
3.0
mV
µV/°C
3
4, 5
Common Mode Input Voltage Range
(∆VIO = 5.0 mV, VO = 0 V)
VICR
6
Large Signal Voltage Gain (VO = ±10 V, RL = 2.0 kΩ)
TA = +25°C
TA = –40° to +85°C
AVOL
7
Output Voltage Swing (VID = ±1.0 V)
RL = 2.0 kΩ
RL = 2.0 kΩ
RL = 10 kΩ
RL = 10 kΩ
VO+
VO–
VO+
VO–
Common Mode Rejection (Vin = ±11 V)
CMR
11
Power Supply Rejection
VCC/VEE = +15 V/–15 V, +5.0 V/–15 V, +15 V/–5.0 V
PSR
12
V/mV
8, 9, 10
Output Short Circuit Current (VID = 1.0 V, output to ground)
Source
Sink
ISC
Power Supply Current (VO = 0 V, per amplifier)
TA = +25°C
TA = –40° to +85°C
ID
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2
Unit
V
dB
dB
13, 14
mA
15
mA
MC33282 MC33284
AC ELECTRICAL CHARACTERISTICS (VCC = +15 V, VEE = –15 V, TA = 25°C, unless otherwise noted.)
Characteristics
Symbol
Figure
Min
Typ
Unit
SR
16, 28, 29
8.0
15
V/µs
GBW
17
20
35
MHz
AVO
18, 21
—
1750
V/V
—
5.5
MHz
15
dB
Slew Rate (Vin = –10 V to +10 V, RL = 2.0 kΩ, CL = 100 pF, AV = +1.0)
Gain Bandwidth Product (f = 100 kHz)
AC Voltage Gain (RL = 2.0 kΩ, VO = 0 V, f = 20 kHz)
Unity Gain Frequency (Open Loop)
fU
Gain Margin (RL = 2.0 kΩ, CL = 0 pF)
Am
19, 20
—
Phase Margin (RL = 2.0 kΩ, CL = 0 pF)
φm
19, 20
—
40
Degrees
Channel Separation (f = 20 Hz to 20 kHz)
CS
22
—
–120
dB
—
175
kHz
Power Bandwidth (VO = 20 Vpp, RL = 2.0 kΩ, THD ≤ 1.0%)
BWP
Distortion (RL = 2.0 kΩ, f = 20 Hz to 20 kHz, VO = 3.0 Vrms, AV = +1.0)
THD
23
—
0.003
%
Open Loop Output Impedance (VO = 0 V, f = 9.0 MHz)
|ZO|
24
—
37
Ω
—
1012
Ω
—
5.0
pF
—
18
nV/ √ Hz
—
0.01
pA/ √ Hz
Differential Input Resistance (VCM = 0 V)
Rin
Differential Input Capacitance (VCM = 0 V)
Cin
Equivalent Input Noise Voltage (RS = 100 Ω, f = 1.0 kHz)
en
Equivalent Input Noise Current (f = 1.0 kHz)
in
25
Figure 1. Equivalent Circuit Schematic
(Each Amplifier)
VCC
D1
R2
R3
R6
R10
R13
Q15
Q8
D2
C1
J3
J4
Q5
Vin
+
Q11
J2
D3
C3
J5
C4
B
C
Q7
D
Q4
Z1
Q1
Q2
Q3
R1
C6
R17
Q10
D5
Q13
VO
Q6
C2
D4
Q18
C5
A
Vin
R16
Q9
J1
Q17
Q12
R4
Q14
R5
R12
R8
R13
VEE
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3
R15
Q16
PD (max), MAXIMUM POWER DISSIPATION (mW)
MC33282 MC33284
Figure 2. Maximum Power Dissipation
versus Temperature
Figure 3. Input Offset Voltage versus
Temperature for Typical Units
2000
VIO , INPUT OFFSET VOLTAGE (mV)
2400
MC33282P & MC33284P
1600
1200
MC33284D
800
MC33282D
400
0
-60 -40 -20
0
20
40
60
80
5.0
3.0
1.0
-1.0
Unit 2
Unit 2
Unit 3
Unit 1
-25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C)
TA, AMBIENT TEMPERATURE (°C)
Figure 4. Input Bias Current
versus Temperature
Figure 5. Input Bias Current versus
Common Mode Voltage
125
600
IIB, INPUT BIAS CURRENT (pA)
350
300
250
200
VCC, VEE=±2.5 V
150
100
50
0
-55
VCC, VEE=±15 V
-25
0
25
50
75
100
500
400
300
200
100
0
-15
125
VCC=+15 V
VEE=-15 V
TA = 25°C
-12 -9.0 -6.0
TA, AMBIENT TEMPERATURE (°C)
Figure 6. Input Common Mode Voltage
Range versus Temperature
VCC=+5.0 V to +18 V
VEE=-5.0 V to -18 V
∆VIO = 5.0 mV
VO = 0 V
VCC-1.0 V
VCC-1.5 V
VEE+1.5 V
VEE+1.0 V
VEE+0.5 V
VEE
-55
-25
0
25
50
0
3.0
6.0
9.0
12
15
Figure 7. Open Loop Voltage Gain
versus Temperature
VCC
VCC-0.5 V
-3.0
VCM, COMMON MODE VOLTAGE (V)
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
VICR , INPUT COMMON MODE VOLTAGE RANGE (V)
Unit 3
-3.0
400
IIB, INPUT BIAS CURRENT (pA)
Unit 1
-5.0
-55
100 120 140 160 180
VCC=+15 V
VEE=-15 V
RS = 10 Ω
VCM = 0 V
75
100
125
150
140
130
VCC=+15 V
VEE=-15V
RL = 2.0 kΩ
f = 10 Hz
∆VO = 10 V to +10 V
120
110
100
-55
TA, AMBIENT TEMPERATURE (°C)
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
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4
100
125
MC33282 MC33284
Figure 8. Output Voltage Swing
versus Supply Voltage
Figure 9. Output Voltage
versus Frequency
30
36
VO, OUTPUT VOLTAGE (Vpp )
VO, OUTPUT VOLTAGE (Vpp )
40
TA=25°C
32
28
24
RL=10 k
20
RL=2.0 k
16
12
8.0
4.0
0
0
27
24
21
18
15
12
9.0
6.0
3.0
2.0
4.0
6.0
8.0
10
12
14
16
18
VCC=+15 V
VEE=-15 V
RL = 2.0 kΩ
AV = +1.0
THD = ≤ 1.0%
TA = 25°C
0
1.0 k
20
10 k
VCC, VEE SUPPLY VOLTAGE (V)
VCC
TA=-55°C
VCC= +15 V
RL to Gnd
VEE=-15 V
VCC-8.0 V
TA=125°C
TA=+25°C
VCC-12 V
VEE+4.0 V
TA=125°C
VEE+2.0 V
VEE
2.0
TA=-55°C
4.0
6.0
8.0
10
12
TA=+25°C
14
16
18
120
VCC=+15 V
VEE=-15 V
VCM=0 V
∆VCM = ±1.5 V
100
80
60
ADM
+
∆VCM
40
20
0
10
20
CMR=20Log
∆VCM
100
1.0 k
|ISC|, OUTPUT SHORT CIRCUIT CURRENT (mA)
+PSR, POWER SUPPLY REJECTION (dB)
PSR+
PSR-
40
20
0
10
VCC
ADM
+
VEE
+PSR=20Lo
g
100
∆VO
∆VO/ADM
MMNI
∆VCC
MMM
1.0 k
VCC=+15 V
VEE=-15 V
∆VCC = ±1.5 V
TA = 25°C
10 k
100 k
10 k
100 k
1.0 M
Figure 13. Output Short Circuit Source
Current versus Temperature
120
60
x ADM
∆VO
f, FREQUENCY (Hz)
Figure 12. Positive Power Supply
Rejection versus Frequency
80
∆VO
MVMNI
xmi MMM
IL, LOAD CURRENT (mA)
100
1.0 M
Figure 11. Common Mode Rejection
versus Frequency
CMR, COMMON MODE REJECTION (dB)
Vsat , OUTPUT SATURATION VOLTAGE (V)
Figure 10. Output Saturation Voltage
versus Load Current
VCC-4.0 V
100 k
f, FREQUENCY (Hz)
1.0 M
50
VID=±1.0 V
RL < 100 Ω
45
40
35
30
VCC, VEE=±15 V
25
20
15
10
VCC, VEE=±2.5 V
5.0
0
-55
-25
0
25
50
75
TA, AMBIENT TEMPERATURE (°C)
f, FREQUENCY (Hz)
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5
100
125
Figure 14. Output Short Circuit Sink
Current versus Temperature
50
Figure 15. Power Supply Current
versus Supply Voltage
VCC, VEE=±15 V
35
30
25
20
VCC, VEE=±2.5 V
15
10
5.0
0
-55
-25
0
25
50
75
100
SR, SLEW RATE (V/µs)
1.5
VCC, VEE=±2.5 V
1.0
0.5
0
-55
-25
0
Noninverting Amplifier
VCC=+15 V
VEE=-15 V
∆Vin=20 V
CL=100 pF
RL=2.0 kΩ
6.0
4.0
2.0
100
0
25
50
75
100
50
40
30
20
10
0
-55
125
-25
0
1A
10
0
1B
2A
2B
1A) Phase VCC=18 V, VEE=-18 V
-30 2A) Phase VCC=1.5 V, VEE=-1.5 V
-40 1B) Gain VCC=18 V, VEE=-18 V
2B) Gain VCC=1.5 V, VEE=-1.5 V
-50
100k
1.0 M
10 M
20
100
120
140
160
180
200
220
240
A m, GAIN MARGIN (dB)
20
80
φ , PHASE (DEGREES)
30
50
75
100
125
Figure 19. Phase Margin and Gain Margin
versus Differential Source Resistance
TA=25°C
CL=0 pF
40
25
TA, AMBIENT TEMPERATURE (°C)
Figure 18. Gain and Phase
versus Frequency
50
125
VCC=+15 V
VEE=-15 V
f=100 kHz
RL = 2 kΩ
CL = 0 pF
TA, AMBIENT TEMPERATURE (°C)
A V , VOLTAGE GAIN (dB)
75
Figure 17. Gain Bandwidth Product
versus Temperature
8.0
-20
50
Figure 16. Slew Rate
versus Temperature
10
-10
25
TA, AMBIENT TEMPERATURE (°C)
Inverting Amplifier
-25
2.0
TA, AMBIENT TEMPERATURE (°C)
12
0
-55
VCC, VEE=±15 V
2.5
125
16
14
3.0
16
Vin
R2
50
+
4.0
260
0
10
f, FREQUENCY (Hz)
40
30
Gain Margin
VCC=+15 V
VEE=-15 V
RT=R1+R2
VO=0 V
TA=25°C
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20
10
100
1.0 k
RT, DIFFERENTIAL SOURCE RESISTANCE (Ω)
6
VO
12
8.0
100 M
Phase Margin
R1
10 k
0
φ m , PHASE MARGIN (DEGREES)
40
ID , POWER SUPPLY CURRENT (mA)
VID=±1.0 V
RL < 100 Ω
45
GBW, GAIN BANDWIDTH PRODUCT (MHz)
|ISC |, OUTPUT SHORT CIRCUIT CURRENT (mA)
MC33282 MC33284
MC33282 MC33284
Figure 21. Gain and Phase
versus Frequency
10
Gain Margin
8.0
20
6.0
30
Phase Margin
40
4.0
Vin
2.0
+
CL
2.0 kΩ
10
VO
50
VCC=+15 V
VEE=-15 V
VO=0 V
100
50
20
10
-10
-20
-30
THD, TOTAL HARMONIC DISTORTION (%)
Drive Channel
VCC=+15 V
VEE=-15 V
RL = 2.0 kΩ
∆VOD = 20 Vpp
TA = 25°C
|zo |, OUTPUT IMPEDANCE (Ω )
100
90
80
70
10 k
100 k
10 M
240
100 M
1.0 M
AV=+1000
AV=+100
0.01
AV=+10
AV=+1.0
10
100
1.0 k
10 k
100 k
f, FREQUENCY (Hz)
Figure 24. Output Impedance
versus Frequency
Figure 25. Input Referred Noise Voltage
versus Frequency
AV=10
AV=100
AV=1000
30
20
10
0
10 k
220
f, FREQUENCY (Hz)
60
40
200
2B
1.0 M
VCC=+15V
VEE=-15V
VO=2 Vpp
TA=25°C
0.1
0.001
VCC=+15 V
VEE=-15 V
VO=0 V
TA=25°C
50
1.0
e n , INPUT REFERRED NOISE VOLTAGE (nV/√ Hz)
CS, CHANNEL SEPARATION (dB)
140
1.0 k
180
1B
Figure 23. Total Harmonic Distortion
versus Frequency
150
100
100
160
2A
f, FREQUENCY (Hz)
160
110
140
VCC=15 V
VEE=-15 V
1A) Phase, VO=10 V
2A) Phase, VO=-10 V
1B) Gain, VO=10 V
2B) Gain, VO=-10 V
Figure 22. Channel Separation
versus Frequency
120
120
1A
Gain
CL, OUTPUT LOAD CAPACITANCE (pF)
130
100
Phase
-40
-50
100k
60
1.0 k
500
30
0
80
TA=25°C
CL=0 pF
40
A V , VOLTAGE GAIN (dB)
10
0
50
0
φ m , PHASE MARGIN (DEGREES)
A m, OPEN LOOP GAIN MARGIN (dB)
12
AV=1.0
100 k
1.0 M
φ, PHASE (DEGREES)
Figure 20. Open Loop Gain and Phase
Margin versus Output Load Capacitance
10 M
50
40
30
Input Noise Voltage Test
Circuit
+
200
20
10 VCC = +15 V
VEE = -15 V
TA = 25° C
0
10
100
f, FREQUENCY (Hz)
1.0 k
f, FREQUENCY (Hz)
http://onsemi.com
7
200
VO
2.0k
10 k
100 k
MC33282 MC33284
Figure 26. Percent Overshoot versus
Load Capacitance
80
70
VCC = +15 V
VEE = -15 V
RL = 2.0 k
TA = 25° C
VO, OUTPUT VOLTAGE (50 MV/DIV)
90
60
50
40
30
20
10
0
10
100
CL, LOAD CAPACITANCE (pF)
1.0 k
t, TIME (1.0 µS/DIV)
Figure 28. Noninverting
Amplifier Slew Rate
Figure 29. Inverting
Amplifier Slew Rate
VO, OUTPUT VOLTAGE (5.0 V/DIV)
VO, OUTPUT VOLTAGE (5.0 V/DIV)
PERCENT OVERSHOOT (%)
100
Figure 27. Noninverting
Amplifier Overshoot
t, TIME (1.0 µS/DIV)
t, TIME (1.0 µS/DIV)
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8
MC33282 MC33284
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
8
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5
–B–
1
4
DIM
A
B
C
D
F
G
H
J
K
L
M
N
F
–A–
NOTE 2
L
C
J
–T–
MILLIMETERS
MIN
MAX
9.40
10.16
6.10
6.60
3.94
4.45
0.38
0.51
1.02
1.78
2.54 BSC
0.76
1.27
0.20
0.30
2.92
3.43
7.62 BSC
--10
0.76
1.01
INCHES
MIN
MAX
0.370
0.400
0.240
0.260
0.155
0.175
0.015
0.020
0.040
0.070
0.100 BSC
0.030
0.050
0.008
0.012
0.115
0.135
0.300 BSC
--10
0.030
0.040
N
SEATING
PLANE
D
M
K
G
H
0.13 (0.005)
M
T A
M
B
M
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
(SO–8)
ISSUE R
D
A
8
E
5
0.25
H
1
M
B
M
4
h
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETERS.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
C
e
X 45 A
C
SEATING
PLANE
L
0.10
A1
B
0.25
M
C B
S
A
S
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9
DIM
A
A1
B
C
D
E
e
H
h
L
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.35
0.49
0.18
0.25
4.80
5.00
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
7
MC33282 MC33284
OUTLINE DIMENSIONS
P SUFFIX
PLASTIC PACKAGE
CASE 646–06
ISSUE L
14
NOTES:
1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
4. ROUNDED CORNERS OPTIONAL.
8
B
1
7
A
F
DIM
A
B
C
D
F
G
H
J
K
L
M
N
L
C
J
N
H
G
SEATING
PLANE
D
K
M
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
8
–B–
1
P 7 PL
0.25 (0.010)
7
G
B
M
M
F
R X 45 C
–T–
SEATING
PLANE
D 14 PL
0.25 (0.010)
M
K
M
T B
S
A
S
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10
MILLIMETERS
MIN
MAX
18.16
19.56
6.10
6.60
3.69
4.69
0.38
0.53
1.02
1.78
2.54 BSC
1.32
2.41
0.20
0.38
2.92
3.43
7.62 BSC
0
10
0.39
1.01
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
INCHES
MIN
MAX
0.715
0.770
0.240
0.260
0.145
0.185
0.015
0.021
0.040
0.070
0.100 BSC
0.052
0.095
0.008
0.015
0.115
0.135
0.300 BSC
0
10
0.015
0.039
J
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.55
8.75
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0
7
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337
0.344
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0
7
0.228
0.244
0.010
0.019
MC33282 MC33284
Notes
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11
MC33282 MC33284
ZIP R TRIM is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor is a trademark and
is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right
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MC33282/D