Silicon Realization—A New Approach to
Faster, Better, and More Profitable Silicon
Authored by David Desharnais, Product Management, Silicon Realization
While Silicon Realization encompasses most of what the industry has defined as traditional “EDA,”
it goes far beyond this definition by outlining a deterministic path to silicon that is broader, more
efficient, and more effective than today’s point-tool based approaches. In its fullness, Silicon
Realization addresses the business and technology challenges of complex silicon development,
and enables design, implementation, and verification teams to attain higher levels of productivity,
predictability, and profitability.
Introduction
Contents
Introduction.................................. 1
A Crisis In Productivity,
Predictability, and Profitability....... 2
Disjointed Phases of Design........... 4
EDA360: A Holistic Solution.......... 5
Intent, Abstraction, and
Convergence................................. 6
Mixed-Signal Silicon
Realization.................................... 8
Other Silicon Realization
Examples.................................... 10
Conclusion.................................. 10
References.................................. 10
Part of the EDA360 vision1 for application-driven design, Silicon Realization
covers the entire scope of tools and capabilities required to get a design into
silicon—be it an analog or digital intellectual property (IP) block, an IP subsystem for a system on chip (SoC), or a completed IC or SoC—including the
package in which the silicon sits. While all aspects of design, verification, and
implementation are part of Silicon Realization, its primary focus is on providing complete, end-to-end deterministic flows to solve real customer challenges.
These challenges include mixed-signal design; low-power design; large-scale,
complex, high-performance advanced node design (also known as giga-gates/
GHz design); verification; IC/system-in-package (SiP) co-design; and the
measurements and metrics that drive enhanced communication and global
productivity across design groups.
These challenges cannot be solved by stitching together isolated point tools
in an iterative, sequential design flow. They can only be solved with the deterministic, interoperable, end-to-end flow envisioned by Silicon Realization. This
flow concurrently optimizes functionality, electrical specifications, and physical requirements throughout the design process. The success of this approach
hinges on three critical requirements:
• A consistent representation of design and verification intent
• The appropriate use of accurate models and higher levels of abstraction
• The convergence of late-stage design and manufacturing data into the early
phases of the design process
In contrast to traditional EDA, Silicon Realization is not solely about solving a
place-and-route problem, or building a more efficient op amp, or getting a tool
to run 1.3x faster—it’s all of that and more. Silicon Realization is about solving
the overall silicon design problem and bringing together everything that’s
needed to produce complex silicon or IP.
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
These days, Silicon Realization nearly always involves both analog and digital design, requiring a fully integrated
mixed-signal design, verification, and implementation flow. Further, most silicon designs have aggressive power,
performance, and form factor requirements in order to provide differentiated functionality for the end user. These
demands often require advanced process nodes, where integrated circuits (ICs) sometimes exceed a billion transistors or more.
With all of these demands, how can a design team expect to create a mixed-signal, low-power, giga-gate/GHz
design on a predictable schedule and still attain profitability? That’s what Silicon Realization is all about. This
whitepaper further discusses the motivations behind Silicon Realization, its ability to concurrently tackle functional,
electrical, and physical requirements, and its use of intent, abstraction, and convergence. It illustrates how these
concepts can be applied in an end-to-end flow, using mixed-signal design and verification as an example.
A Crisis In Productivity, Predictability, and Profitability
Silicon designers today are under tremendous technology and business pressure. On the technology side, chip
complexity is exploding and designers must meet multiple objectives including functionality, low power, high
performance, and manufacturability. On the business side, design and manufacturing costs are skyrocketing, with
SoC development costs approaching $100 million at the 32nm node.
Time to market has continued to accelerate as product windows shrink, and even when the design makes it to
tapeout, the key question becomes “will it yield?” There are many public case studies where silicon failure has cost
companies hundreds of millions of dollars in direct losses. If one considers the indirect costs, class action suits, and
implications to a company’s brand, the cost of failure is stratospheric. This is how people lose their jobs, and how
companies get shuttered entirely.
Technology
Multi-dimension chip complexity growing
• Functionality
• Performance
• Power
Productivity
• Process nodes
Business
Design, R&D, and manufacturing
costs skyrocketing
• Design re-use
Predictability
Profitability
• Time to market
• Silicon yield
• Design failure
Figure 1: Technology and business challenges are driving the need for Silicon Realization
The end result of these challenges is a growing crisis in three related areas: productivity, predictability, and profitability. Because iterative, sequential, point-tool–based flows can no longer address this crisis, it has become a key
driver for Silicon Realization.
Productivity
According to Cadence ® calculations, silicon complexity in terms of transistors per chip has had a compound annual
growth rate of 58% per year since the 1970s, while productivity in terms of gates per designer has only had a
compound annual growth rate of 21%. This results in a growing productivity gap in which silicon capacity outstrips
the ability to make use of that capacity. While silicon processing techniques and algorithms for synthesis, place and
route, and simulation have done a reasonable job of keeping pace with the density enabled by Moore’s Law, tasks
such as variation control, design rule checking, optical proximity correction, and overall timing verification have not.
www.cadence.com
2
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Since the emergence of a commercial EDA industry, IC implementation tools have been developed and successively
improved. As different eras of EDA have come and gone, loosely integrated “solutions” have attempted to bring
point tools together. This evolution has been necessary, but it’s insufficient for the future. Now it’s time to take
the next step and move from loosely integrated “solutions” to true solutions that allow a much more unified and
deterministic approach to design, verification, and implementation.
Predictability
The lack of predictability is a serious challenge for silicon design teams. At 130nm, according to industry sources,
the probability of meeting performance requirements is 96%. At 40nm it drops to 71%, and at 22nm it will drop
to 33%. The result: more re-spins, more silicon failures, and more design teams staying at older process nodes.
Re-spins occur for multiple reasons. The chart below shows major causes of re-spins at the 40nm process node. (In
this IBS survey, respondents were allowed to make multiple choices.) Leakage was cited as a problem in 87% of the
re-spins, while I/O functionality, which includes analog/digital integration, was cited at 50%.
90.0
80.0
100.0
70.0
60.0
50.0
50.7
40.0
30.0
27.3
20.0
10.0
0.0
12.2
8.9
Leakage
Verification Design Rule
I/O
Bugs
Violation
Functionality
Testability
Problems
11.4
(Source IBS)
Percentage of Designs with Problems (%)
100.0
Other
Figure 2: Leakage ranks highest among causes of silicon re-spins (Source IBS)
The point here is that most re-spins are due to multiple, interacting problems. Thus, today’s sequential design
flows, where point tools attempt to solve individual problems in isolation, cannot result in optimal solutions.
The yield ramp for new processes is another growing concern. Ramp-up to volume production can stretch out to
36 months and beyond at 32/28nm, a two-fold increase over 65nm. This makes it more difficult and more risky to
migrate to advanced process nodes.
The lack of predictability leads to significant waste and anxiety, with designers having to over-design in every step
of the flow, never knowing silicon results until silicon comes back from the foundry. Time-to-market and time-toyield pressures are relentless and unforgiving. Shipment windows today are often six months or less, compared to
nearly 24 months in the early 2000s. Simply put, design teams have to design, implement, and verify much more
complex, performance-hungry, and power-limited chips in less time than ever before.
Profitability
The exorbitant cost of design—as much as $100 million for 32nm SoCs—means that fewer designs will be done,
especially at advanced process nodes. According to a GLOBALFOUNDRIES Design Automation Conference 2010
keynote speaker, there will be more than 1,000 design starts at 65nm in the first five years, but only 156 design
starts at 22nm during the first five years. One reason for the high costs is that 32nm fabs cost $5–8 billion,
and 32nm process R&D costs around $1 billion, and these costs must be amortized over a smaller number of
design starts.
www.cadence.com
3
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Semiconductor companies will have to bear the burden of these costs, and in order to achieve positive future
return on their investments today, they can only target extremely high-volume markets that promise upwards of 50
million units of sales. This translates into multi-function chips that are mixed signal, low power, high performance,
and have a small form factor. Add in a tough economic environment, and it’s increasingly difficult for semiconductor design companies—as well as foundry and IP providers—to attain profitability.
The EDA360 vision paper published by Cadence in early 2010 speaks of a growing “profitability gap,” which is
the difference between what companies can build and what they can make money on. This gap is driven by both
design costs and semiconductor unit costs. To control these costs, companies must not only reduce development
costs, but also pay close attention to packaging, manufacturing, and test. They must also maximize revenue opportunities by meeting time-to-market goals and by designing the right product for the right market, avoiding “feature
overshoot” that provides more than consumers are willing to pay for.
Faced with escalating costs and both technical and business challenges at advanced process nodes, many semiconductor companies are shifting their focus from design creation to design integration using pre-built, pre-verified
blocks of silicon IP. Silicon Realization addresses both the creation of IP and its integration into SoCs. Traditional
EDA, in contrast, focuses primarily on design creation. Even though individual IP blocks may have been pre-verified,
integration of IP into SoCs requires another level of verification, and this is where EDA providers can add value.
Disjointed Phases of Design
All silicon designs have functional, electrical, and physical requirements, and these identify separate phases of the
design process. The functional design phase determines what a chip does and verifies that it will meet the intended
functionality. The physical design phase uses physical implementation tools to produce a layout that meets size and
form factor requirements. The electrical design phase uses analysis and optimization tools to reach the required
performance and power specifications. The diagram below shows the functional, electrical, and physical domains
as separate axes.
Functional
Electrical
Physical
Figure 3: Functional, physical, and electrical characteristics of the design have traditionally been
treated as orthogonal concerns
Despite their close interdependency, functional, physical, and electrical design have typically been done in isolation
from one another. Typically, the design team will work out the functionality first, starting with high-level models
and (manually) working their way toward a verified RTL description. Eventually, they will throw a netlist “over the
wall” to the physical design team. Although some high-level floorplanning and prototyping tools do exist, most
physical design teams today dive right into placement and routing, and time-consuming iterations with the logical
design team are almost guaranteed.
A separate effort uses various tools and techniques to “close” the design in terms of timing, power, signal integrity,
design for manufacturability (DFM), and yield. This effort starts late in the design process and is likely to result in
numerous iterations between the logical and physical design teams. One result is a high chance of silicon failure. As
previously noted, leakage problems are involved in most silicon re-spins at the 40nm node.
www.cadence.com
4
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Why are functional, physical, and electrical design so isolated? One reason is the “siloed” nature of the EDA industry, which is divided into different segments with different tools that are often provided by different companies.
The EDA industry has tools for RTL verification, synthesis, analysis, physical design, packaging, and many other
niches. EDA vendors optimize tools within a given niche, but pay little attention to end-to-end flows. This disjointed
approach is no longer adequate for today’s complex, high-performance, low-power silicon.
Silicon Realization, in contrast, proposes a deterministic flow that concurrently addresses functional, physical, and
electrical requirements. It calls for capabilities to represent these requirements at all levels of abstraction. Today,
it is very difficult to represent physical and electrical concerns early in the functional definition and optimization
phase, but this is an important capability for tomorrow’s silicon designs. Silicon design teams also need to make
sure that functional verification done in the front end stays valid during physical and electrical implementation.
EDA360: A Holistic Solution
One way the EDA industry can break out of its “point tool” orientation is described in the EDA360 vision paper.
A vision for the entire industry—not a Cadence product roadmap—EDA360 recognizes an industry shift in which
software applications have become the primary differentiator for electronics manufacturers. Semiconductor
companies can no longer just provide silicon, but are increasingly expected to provide hardware/software platforms
ready for applications deployment. In this shift, most semiconductor companies will become “integrators” in
addition to, or instead of, “creators.”
With the EDA360 approach, users start with an understanding of the software applications that will run on a given
hardware/software platform, define the system requirements, and then work their way down to hardware and software
IP creation and integration. EDA360 includes three “realizations:”
• System Realization is the development of a complete hardware/software platform, including the software
stack up to the applications level. It thus includes one or more SoCs and other components, and adds an
embedded software infrastructure including an OS, middleware, and reference applications.
• SoC Realization is the completion of an individual system on chip comprising silicon IP. It includes “bare metal”
software such as the drivers that are used to control system hardware.
• Silicon Realization is the creation and verification of the silicon hardware upon which complex software
applications can run. In addition to processors and digital logic, it includes the analog and RF circuitry that
electronic systems require to interact with the real world.
EDA360
System Realization
SoC Realization
Silicon Realization
Figure 4: EDA360 includes System Realization, SoC Realization, and Silicon Realization
The key difference between Silicon Realization and contemporary EDA flows is the reliance of Silicon Realization on
three emerging concepts: unified intent, higher abstraction, and convergence.
www.cadence.com
5
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Intent, Abstraction, and Convergence
Intent
Design and verification intent provides an early, unified representation of the targeted functional, physical, and electrical
characteristics of a silicon design. A unified intent representation can be comprehended and used throughout the design
flow in a consistent way. It serves design, verification, and implementation, and it spans different abstraction levels. It
can thus be used by all team members.
Unified intent brings many benefits to users. It reduces errors, misunderstandings, and unnecessary iterations.
It allows a global knowledge transfer among design teams. It avoids duplication of effort, produces consistent
results throughout the flow, and fosters predictability and productivity. It also affects profitability—working from a
common set of design constraints or intent greatly reduces the risk of specification misses and re-spins.
One example of unified intent is the Common Power Format (CPF). Initially developed by Cadence and now available as an industry standard, CPF ensures that power intent is consistently interpreted, correctly implemented,
and thoroughly verified at every stage of the design. It’s part of the Cadence Low-Power Solution. Some other
examples of unified intent, all supported by Cadence, include the following:
• Common physical design constraints between digital and analog environments
• Verification planning that allows a single, metric-driven verification plan encompassing both analog and digital
methodologies and tools
• Co-design optimization across ICs, packages, and boards to improve performance, size, cost,
and power
Abstraction
As silicon complexity skyrockets, traditional design methods—such as RTL coding in the digital world or Spicelevel simulation in the analog/mixed-signal world—must be complemented or replaced by moving to higher levels
of abstraction. Only through higher levels of abstraction will it be possible to perform concurrent design between
functional, physical, and electrical domains, or to design, verify, and implement chips with hundreds of millions of
transistors. With abstraction, models provide only the level of detail needed at any given stage of the design, verification, or implementation effort. Through successive refinement, the models become progressively more detailed
as the design flow moves forward.
Abstraction allows a divide-and-conquer approach in which blocks are designed separately, and then stitched back
together during SoC integration. Similarly, it facilitates the integration of third-party IP into SoCs. That’s because
integrators can use high-level models that do not go into unneeded details about the internal workings of the
blocks. Abstraction also enables hierarchical design, which is increasingly necessary for large ICs.
Abstraction has some additional advantages. For example, it allows the handling of large data sets, reduces tool
capacity problems, and ensures much faster time to market, since there is less data to process and verify. It also
permits an early tradeoff analysis of functional, physical, and electrical characteristics.
One example of abstraction is the current move from RTL to transaction-level modeling (TLM) in the digital realm.
Strongly advocated by Cadence, 2 this approach greatly reduces coding (and therefore bugs), allows for orders-ofmagnitude faster verification, and makes it possible to try a number of potential micro-architectures using highlevel synthesis. But abstraction is not just confined to the digital realm. Other examples of abstraction supported by
Cadence include:
• Verilog-AMS wreal model creation, validation, and integration to drive mixed-signal SoC verification at digital
speeds
• Rapid analog and digital prototyping for architectural exploration and floorplanning in the early phases of
physical design, with complete visibility into the electrical domain
• Block data abstraction for large-scale digital optimization and design closure
• Modeling of gigabit signal interfaces across IC, package, and board
• Hierarchical, low-power IP macro-modeling
www.cadence.com
6
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Convergence
Despite the focus on higher levels of abstraction, Silicon Realization is not purely a “top-down” methodology.
Physical, manufacturing, and packaging information must also flow upward into the early stages of the design
and verification process, making intelligent tradeoffs possible. The result is what some might call a “meet in the
middle” flow. Here, the term “convergence” represents the marriage of top-down and bottom-up methodologies.
Convergence is about building a solution where successive refinements and concurrent optimizations ensure intent
is met in all aspects.
A strong benefit of convergence is the ability to run early-stage “what if” analyses of power, performance, cost,
and packaging with meaningful data. This allows designers to make the right tradeoffs to attain the best possible
architecture. It can be a great cost-saver; for instance, fitting into a cheaper package can greatly impact the cost—
and profit potential—of a chip. Convergence also speeds design closure, eliminates iterations, makes engineering
change orders (ECOs) less disruptive, and reduces the risk of re-spins.
It should be clear that convergence requires very close collaboration with silicon foundries. Cadence has collaborative efforts with all major foundries, including TSMC, GLOBALFOUNDRIES, UMC, SMIC, and the Common Platform.
These joint efforts have included a 28nm analog/mixed signal flow with GLOBALFOUNDRIES, an electronic systemlevel (ESL) flow with TSMC, and a 40nm low-power reference flow with UMC.
Examples of convergence supported by Cadence include the following:
• “In design” electrical, physical, and manufacturing signoff, including lithography and chemical-mechanical
polishing (CMP) hotspot identification and closure for advanced nodes
• Multi-objective, concurrent, physically- and electrically-aware optimization from the RTL level through to final
design closure
• IC/package device optimization to validate device-level timing and power performance while minimizing package
complexity and cost
• Power delivery network optimization using concurrent chip and package power modeling
One view of Silicon Realization is represented in the following graphic, where functional, electrical, and physical
constraints are modeled at all levels of abstraction, and where intent, abstraction, and convergence are the central
tenets. The graphic depicts areas in which Cadence offers Silicon Realization capabilities today.
Mixed Signal
Functional
Low Power
SiP/Co-Design
Electrical
Physical
Giga-Gates/GHz
INTENT
Verification
Global Productivity
and Metrics
ABSTRACTION
CONVERGENCE
Figure 5: Driven by unified intent, abstraction, and convergence, Silicon Realization unifies functional,
physical, and electrical design
www.cadence.com
7
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Mixed-Signal Silicon Realization
Because nearly all SoCs today are mixed signal, various methodologies for developing mixed-signal SoCs are available. A
typical mixed-signal design flow is shown below. It covers verification, chip planning, analog and digital block creation,
chip integration, and signoff. This flow can produce silicon, but it traditionally poses many challenges, as shown in
the text boxes below. As a consequence, there’s a high silicon re-spin rate for mixed-signal ICs, often due to “simple”
problems such as an incorrect signal polarity or wrong bus ordering.
Analog behavioral model
availability and accuracy
SoC spec
Specification and model
validation in concurrent
analog design
Soft
A
Hard
A
Custom
D
RF
No analog testbench
automation and coverage
metrics
Verification plan
SoC validation
Chip planning
Analog/mixedsignal block
creation
Digital block
creation
Chip integration
Logic equivalence/low-power checks
Mixed-signal parasitic
simulation flow
Hard
D
Metric-driven verification
and testbench automation
Analog/mixed-signal simulation
Consistent low-power
specification
Soft
D
Connectivity checks for
analog interface logic
No physical and electrical
constraints for analog
mixed-signal blocks
Timing, SI, power signoff
Metric-driven verification
and testbench automation
ECO and signoff flow,
post-chip finishing
Accurate timing/SI
modeling of analog/
mixed-signal blocks
Chip finishing
GDSII
Figure 6: Today’s mixed-signal design flows can produce silicon, but have many challenges and limitations
Challenges start with the difficulty of finding, or creating, the analog behavioral models that are needed for SoC
integration. The digital metric-driven verification (MDV) flow traditionally doesn’t extend to analog; there is no
analog testbench automation, and there are no analog coverage metrics. Analog design constraints such as shielding requirements, electromigration (EM), or capacitive loading may or may not be passed along to chip integration.
Analog and digital power and ground planes are represented differently—analog uses inherited connections while
digital uses a power intent specification.
Verification speed is a big stumbling block for mixed-signal chips. Spice-based simulation is much too slow for
top-level, full-chip verification, and “FastSpice” simulators aren’t enough of an improvement. An alternative is real
number modeling (RNM), where digital simulators can use
real values that represent voltage levels, making true mixed-signal simulation possible at near-digital speeds.
It is important to look beyond the mixed-signal chip and pay attention to parasitics and noise on the package and
board. These are affected by, and will affect, the silicon. 3D ICs will be increasingly used for mixed-signal integration in the future. These raise some additional challenges, such as the need for thermal analysis on various levels of
stacked die.
Using a holistic Silicon Realization approach, Cadence addresses the problems cited above through its end-to-end
flow for mixed-signal design, verification, and implementation. The end-to-end flow includes technology from the
Encounter ® Digital Implementation (EDI) System, the Virtuoso ® custom layout suite, the Incisive ® verification suite,
and Allegro® packaging and printed circuit board (PCB) tools.
www.cadence.com
8
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
OpenAccess provides a common database to represent the intent and abstraction that makes concurrent analog/
digital design possible. Interoperability between digital and analog domains enables mixed-signal concurrent
floorplanning, pin optimization, hierarchical optimization, full-context late-stage ECOs, electrical, physical, and
manufacturing signoff, and verification.
There are many unique aspects of the Cadence Mixed-Signal Solution. In verification, for example, wreal model
generation and verification brings RNM into SoC simulations and into metric-driven verification. Cadence is
currently working with Accellera and the IEEE to enhance wreal modeling. Furthermore, automatic generation and
validation of behavioral models is an essential part of the solution to ensure wide adoption of this new verification methodology for analog/mixed-signal designs. Incisive metric-driven and verification planning capabilities have
been expanded to include mixed-signal verification as well.
In mixed-signal implementation, the OpenAccess database allows immediate data transfers without translation.
Floorplanning can become a joint exercise between analog and digital groups, who concurrently optimize the floorplan and pin placement using the timing-driven methodology in the digital design environment, and take advantage of the interactive capabilities of the analog design environment. Late-stage ECOs in either the digital or analog
environment are possible because design information is stored consistently in OpenAccess.
Analysis and signoff include an integrated transistor-level and gate-level extraction. Static timing signoff is eased
because accurate timing and signal integrity (SI) analysis is possible within mixed-signal blocks, without any need
for analog designers to create .lib models.
Intent, abstraction, and convergence are at work throughout the Cadence Mixed-Signal Silicon Realization flow,
as shown in the diagram below. Design and verification intent, for example, is conveyed in electrical and physical constraints, bi-directional constraint management, and power intent specifications. Abstraction is reflected in
analog behavioral modeling and real number model support. Convergence is illustrated by integrated signoff analysis, and late-stage ECO capabilities are enabled by the consistent intent representation in OpenAccess.
INTENT
ABSTRACTION
CONVERGENCE
• Design intent via electrical and physical constraints
• Constraints management (bi-directional front/back-end)
• Power intent specification/verification throughout flow
• Unified OA database for design data and constraints
• Analog behavioral modeling and characterization
• Real number model simulation support
• AMS IP timing/power/noise views for SoC integration
• Automated die abstraction for IC-package co-design
• Integrated signoff analysis in implementation
• Full-chip timing/SI/IR/EM signoff covering AMS IP
• Analog and digital ECO capabilities including late stage
• IC-package predictability and co-design
Figure 7: The Cadence Mixed-Signal Silicon Realization flow leverages intent, abstraction, and convergence
www.cadence.com
9
Silicon Realization—A New Approach to Faster, Better, and More Profitable Silicon
Other Silicon Realization Examples
Other examples of Cadence Silicon Realization capabilities include the following:
Low power. Power intent is captured in CPF files, which stand apart from the RTL design description. The entire
end-to-end Cadence low-power flow preserves, manages, and re-validates the low-power intent as the design
progresses. Verification tools understand low-power intent, including power shutoff in mixed-signal as well as
digital blocks. The low-power flow includes power-aware IP reuse, multi-objective synthesis including power
constraints, full-flow multi-power domain awareness, power-aware test, and multi-corner/multi-mode analysis,
optimization, and signoff.
Giga-gates/gigahertz (GHz). In addition to a re-architected, memory-efficient database and a multi-core
backplane, analog and digital design exploration capabilities allow for rapid chip-level prototyping and floorplanning with abstracted models that come very close to handcrafted results in a fraction of the time. A clock and bus
interface file captures intent, allowing high-speed clock and bus optimization. Hierarchical, high-speed design
closure is possible through multi-level data optimizations that can be done following integration and assembly for
high-capacity blocks and high-speed nets.
Metric-driven verification (MDV). An executable verification plan (vPlan) states the verification intent and tracks
coverage metrics to ensure goals are met. MDV works with multiple languages, including SystemVerilog, SystemC®,
and e. The same verification environment is used at all levels of abstraction, with no need to re-write or re-verify
models at each stage. The metric-driven flow automatically converges on verification goals and helps determine
design closure for digital and mixed-signal designs.
System in package (SiP)/co-design. Capabilities range from constraint-driven logic authoring to physical
implementation. System connectivity management enables layout-versus-schematic (LVS) checking and ECOs. A
co-design methodology makes it possible to optimize interconnect at the interface level, thus raising the abstraction level. Convergence occurs as the co-design methodology validates chip-to-package power and timing, and
optimizes I/Os.
Conclusion
In this whitepaper, we’ve seen how Silicon Realization is a fundamentally new approach to semiconductor design,
verification, and implementation. It extends traditional EDA to cover both integration and creation. It unites
functional, physical, and electrical concerns. And it’s based on three important, emerging concepts: unified intent,
higher abstraction levels, and convergence.
It’s important to remember that Silicon Realization is part of a larger vision called EDA360. Silicon Realization is
contained within SoC Realization and System Realization, both of which bring embedded software into the picture.
Silicon today must be designed with software in mind, not just thrown “over the wall” to firmware, OS, and application developers. Success and profitability will come only with a strong focus on the end product and the applications that silicon will enable.
References
1 EDA360: The Way Forward for Electronic Design. http://www.cadence.com/eda360
2 TLM-Driven Design and Verification Methodology. http://www.cadence.com/products/sd/
Pages/tlm.aspx
Cadence is transforming the global electronics industry through a vision called EDA360.
With an application-driven approach to design, our software, hardware, IP, and services help
customers realize silicon, SoCs, and complete systems efficiently and profitably. www.cadence.com
© 2010 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, Allegro, Encounter, Incisive, and Virtuoso are registered
trademarks of Cadence Design Systems, Inc. All others are properties of their respective holders.
SystemC is a registered trademark of the Open SystemC Initiative, Inc. in the U.S. and other countries and is used with permission.
21730 10/10 MK/DM/PDF