The Microelectronics Training Center, IMEC v.z.w.
www.imec.be/mtc
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EPITAXIAL DEPOSITION AND
SILICON ON INSULATOR
(SOI)
RNT-IMEC EPI/SOI
1
OUTLINE
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Definitions
Applications
Epi process
Epi tools
Epi film characterization
SOI
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„
SIMOX
SmartCut
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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www.imec.be/mtc
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DEFINITIONS
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Epitaxial- “arranged upon”
Homoepitaxy – same substrate and film
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Si on Si
Heteroepitaxy- different substrate and film
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Silicon on sapphire or Si on Si-Ge (HBT, strained Si)
RNT-IMEC EPI/SOI
3
TYPES OF EPITAXY
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Liquid phase epitaxy (LPE)
„ III-V epi layer; GaAs
„ Refreeze of laser melted silicon
Solid phase epitaxy (SPE)
„ Crystalline regrowth of an ion implanted amorphized layerα-Si
„ 550C
Vapor phase epitaxy (VPE) is performed by Chemical
Vapor Deposition (CVD)
„ Provides excellent control of thickness, doping, and
crystallinity
„ High temperature (800-1100C)- autodoping and solid
state diffusion
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
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EPI DEVICE APPLICATIONS
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Bipolar transistors
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All bipolar are built in epi to provide low collector resistance
and high breakdown voltages
CMOS
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Improved latchup
Improve oxide breakdown characteristics by
eliminating polishing defects, COPs, surface
roughness
Standard in Microprocessors and advanced logic
devices
Not used in DRAM because of cost issue
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Inexpensive epi may be used in DRAM
Can relax wafer requirements
RNT-IMEC EPI/SOI
5
EPI LAYERS IN DEVICES
epi layer
Bipolar
transistor
Buried layer
CMOS
transistors
epi layer
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GASES USED IN SILICON EPI
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Silane (SiH4) pyrolysis
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H2 reduction
Silicon tetrachloride (Sil Tet) – SiCl4
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H2 reduction
Trichlorosilane (TCS) – SiHCl3
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Si + 2H2
Dichlorosilane (DCS)- SiH2Cl2
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SiH4 (H2)
H2 reduction
Disilane Si2H6
RNT-IMEC EPI/SOI
7
GASES USED IN SILICON EPI
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Dopant gases
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Diborane (B2H6)
Phosphine (PH3)
Arsine (AsH3)
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MTC 2003 : Silicon Processing course
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EPI DEPOSITION
Growth rate
Silane>DCS>TCS>sil tet
For same temperature
Reaction rate controlled
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9
TYPES OF EPI DEPOSITION
Deposition system
APCVD
LPCVD
RTCVD
UHVCVD
GSMBE
„
Pressure range (torr)
760
0.1-10
1-10
10-5
10-5-10-6
Silicon precursor
DCS
DCS
Silane, disilane (Si2H6) and DCS
Silane, disilane
Silane, disilane
For CVD below 800C the reaction is
surface controlled with an activation
energy of ~1.6-2.0 eV
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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EPITAXIAL CVD PROCESSES
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APCVD- atmospheric pressure CVD (cold-wall reactor)
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„ Pressure 760 torr
RTCVD (rapid thermal CVD) cold/warm wall
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LPCVD- cold/warm wall
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Pressure ~0.1 torr
Gas source molecular beam epitaxy (GSMBE)
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Pressure ~10 torr
Pressure ~10-5 torr
Ultra-high vacuum CVD (UHVCVD) hot wall
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Pressure ~10-5-10-6 torr
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DOPING CONTROL
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Intentional doping
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Use PH3, AsH3, or B2H6 for controlled doping
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Incorporation not linear with dopant in gas phase
Dopants change growth rates
Doping range for B is 1016-1019/cm3
Doping range for As and P is 1016-1020/cm3
Autodoping
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Outdiffusion from heavily doped substrate
Impurity incorporation from dopant in gas phase
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DOPING PROFILE IN EPI
LAYER
RNT-IMEC EPI/SOI
13
MINIMIZING AUTODOPING
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Fast growth rate to minimize out-diffusion
Vapor phase autodoping slows down once surface
becomes depleted of dopants
Low temperature deposition reduces boron
autodoping (not As, however)
Seal backside of substrate with lightly doped poly or
LT oxide
Avoid the use of HCl etching
Cap (thin undoped Si) -purge-grow (doped film)
Reduced pressure epitaxy
„
Minimize boundary layer and removes dopants to the
exhaust
RNT-IMEC EPI/SOI
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GROWING EPI LAYERS
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Wafer prep
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Scrub + SC-1 + SC-2- leaves thin oxide layer
Remove oxide by high temperature HCl (1-5% in
H2) etch
Remove oxide by H2 treatment at >800C
RNT-IMEC EPI/SOI
15
HYDROGEN PRE-BAKE
Hydrogen pre-bake in epi tool in low O2/H2O partial pressure
Oxide stable
Si stable
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TYPICAL PROCESS
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17
EPI TOOL
Upper Outer Lamps
Process Gas
Injection
Quartz
Upper Inner Lamps
Pyrometer #1
Exhaust
Laminar Gas Flow
Lower Outer Lamps
Lower Inner Lamps
Stainless Steel
Energy from Lamps
Pyrometer #2
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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LOW TEMPERATURE EPI
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Low temperature required for
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Si-Ge HBT
Selective epi
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Raised source drain
isolation
Low temperature conventional epi
Ultra-high vacuum (UHV) deposition (IBM)
Low temperature rapid thermal deposition
(RTCVD)
RNT-IMEC EPI/SOI
19
SELECTIVE EPI GROWTH
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Growth over exposed silicon only
TYPE 1
Siltet>TCS>DCS
TYPE 2
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SELECTIVE EPI GROWTH
RNT-IMEC EPI/SOI
21
CHARACTERIZATION OF EPI
FILMS
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Optical surface inspection for defects
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Electrical
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Slip, Stacking fault, and dislocations
Sheet resistance – 4-pt. Probe
SRP to interface to measure the doping
profile
Thickness
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FTIR tools
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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STRAINED SILICON
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Put strain in the lattice by using Si-Ge then
depositing strained Si on top- processing is
done in the Si
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Different than using Si-Ge for process layer
Increased electron and hole mobility
Drive current increased by about 10-20%
RNT-IMEC EPI/SOI
23
STRAINED SILICON
SOURCE: SOITEC
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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STRAINED SILICON LAYERS
IBM web site
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25
STRAINED SILICON LATTICE
Intel web site
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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STRAINED SILICON IMPROVES
CHANNEL MOBILITY
SOURCE IMEC
http://www.imec.be
/wwwinter/processing/asd
/activities/strained.shtml
RNT-IMEC EPI/SOI
27
WHY SILICON ON INSULATOR
(SOI)
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Reduced junction capacitance
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Reduced reverse body effect
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Oxide capacitance less than reversed biased p-n
junction
The SOI transistor body potential is floating
instead of contacted as in bulk devices. More
devices can be stacked at low voltage (e.g., 3
input vs. 2- input logic gates can be designed
Faster speeds
„
Enhanced circuit speed as much as 20-50% at
device operating temperatures
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
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WHY SOI?
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Reduced soft error sensitivity
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Charge collection volumes are limited by the
buried oxide layer. Becomes more important as
voltages and device dimensions decrease
Devices are free of latch-up
Fabrication process is simplified by reducing
the number of masking steps by as much as
30%
Result in smaller circuit layout
RNT-IMEC EPI/SOI
29
IMPROVED CIRCUIT LAYOUT
PMOS
N+
P+
NMOS
P+
N+
N-well
NMOS
P+
N+
N+
Buried oxide
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
P+
Bulk inverter
PMOS
P+
N+
SOI inverter
30
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ISSUES WITH SOI
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Substrate costs
Low thermal conductivity (buried oxide)
for high power devices
Floating body electrical effects
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31
APPLICATIONS OF SOI
IBIS website
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
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SIMOX FORMATION
High dose oxygen implant in the bulk Si substrate
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4x1017-2x1018 atoms/cm2
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Requires special implanters
Buried oxide thickness control(energy) 80-400 nm
Implant causes damage to silicon
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Dislocations, stacking faults, etc
Requires special dedicated implanters (IBIS, Hitachi)
High temperature anneal (~1320C)
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Forms buried oxide layer (BOX)
Damaged silicon layer recrystallizes
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Requires capping layer to prevent silicon evaporation
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33
SIMOX PROCESS
O+,
4x1017-2x1018
atoms/cm2
O in silicon
1320C anneal to form
Buried oxide (BOX)
BOX
epi
May deposit epi to
increase Si thickness
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MTC 2003 : Silicon Processing course
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MODIFIED LOW DOSE (MLD) SIMOX
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Reduces implant time
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BOX thickness ~ 135 nm
SOI thickness ~ 145 nm
SIMOX implanter –IBIS
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45 mA beam current
T (wafer) 300-570C
13 wafers/batch 300mm
RNT-IMEC EPI/SOI
35
SMARTCUT (SOITEC
Unibond) PROCESS
„ :
Initial
silicon
A
Buried oxide
Oxidation
H+ ions 5x1016 cm-2
Smart-Cut
implant
Cleaning and
bonding
A
B
RNT-IMEC EPI/SOI
MTC 2003 : Silicon Processing course
IMEC© 2003
B
He can also be used
Can be performed
using PII
Wet clean or plasma
treated bonding
36
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SMARTCUT PROCESS
A
SmartCut
splitting at 500°C
B
Annealing 1100°C
CMP touch polishing
SOI wafer
Wafer A becomes B
A
New A
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37
SMARTCUT VS SIMOX
SIMOX
Oxygen implant
Specific implanter
3 low-dose wafers/hour (8")
No bonding
No splitting
1300°C anneal
Recrystallized
SmartCut
Thermal buried oxide
Hydrogen implant
Standard implanter
16 wafers/hour (8")
SiO2/Si bonding
Splitting
1100°C anneal
Polishing
Starting silicon quality
RNT-IMEC EPI/SOI
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TEM OF SILICON/OXIDE
SMARTCUT INTERFACE
Silicon film
Top interface
Bottom interface
Substrate
(Back gate)
RNT-IMEC EPI/SOI
39
STRAINED SILICON ON
INSULATOR
SOURCE: SOITEC
RNT-IMEC EPI/SOI
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