High-Efficiency Silicon Heterojunction Solar cells
Properties, Processing, and Perspectives
Stefaan De Wolf
EPFL, IMT, PV-lab Neuchâtel
stefaan.dewolf@epfl.ch
1
Outline
1. Introduction and some features of crystalline silicon PV
2. Need for passivating contacts
3. Basics of SHJ technology
4. Process sequences and impacts on layers and passivation
5. Wafer type
6. Current losses
7. IBC heterojunction
8. Metallization
9. Industrialisation
10. Perspectives
Why solar energy?
1 hour of sun irradiation on earth = total annual world energy consumption
3
Why solar energy?
Typical sun intensity at sea level 1000 W/m2
In Switzerland
~ 1000-1500 full hours annually
 1000-1500 kWh/m2 annually
 Close to 1 barrel (159 liters) per m2 per year!
How to tap this source?
Source: PV course EPFL, C. Ballif
4
*1 liter of oil ~10 kWh chemical
Various ways to use solar energy
Solar thermal systems: light  heat
•
•
•
Sanitary water 1 m3/person (CH)
Can support heating needs in winter
Can be stored as reserve heat for the winter…
(usually large water tanks)
•
•
•
Efficiency 50-70% (high T, or low T heat)
Thermal kWh 8-15 cts !
Installation costs can be quite high !
Concentrated solar thermal: light  heat  electricity
• Focus light on receiver ( e.g. tower or tube)
• Create high T heat (300-600°C)
• Run turbine with heated gas
• Short term perspective for electricity at < 8-10 €cts/Kwh
• Complex systems, global efficiency 17-20%
Source: PV course EPFL, C. Ballif
Various ways to use solar energy
Photovoltaics: light  electricity
-
Useful power
dissipated on RM
Vmax
I
+
6
Source: PV course EPFL, C. Ballif
Various ways to use solar energy
Photovoltaics: light  electricity
Source: Schweizer-Metallbau
7
Source: PV course EPFL, C. Ballif
PV market growth
8
PV technologies: an overview
9
Technology shares in PV
 Crystalline Si dominates the market (>90%)…
10
Technology shares in PV
11
 Crystalline Si dominates the market…
… and will do so for quite a few years.
Crystalline silicon technology
Advantages
• Standard technology « mature »
• Reliable modules, high efficiency
• Continuous improvement of the processes
• Assembly line split in 50-100 steps « sand to module »
Weakness
• Need of high quality Si feedstock / many steps
12
Source: PV course EPFL, C. Ballif
Advantages of high efficiency
High eff cell
 reduction per Wp of non-cell module components
 Way to finally reduce $/Wp
Requires less mounting space
 lower area related balance of system costs
 Reduce renting of space
 can advantageously be combined with trackers
(1 or two axis)
Improved Voc and Tcoeff
 Better energy yield at low ill. and at high T
Because of their inherent benefits « high
efficiency » technologies can sell at higher price
… typically 0.1 €/Wp more per absolute
efficiency % in 2010 ! Today the difference is
reduced
Dual axis tracking can bring 25-45% increased energy
depending on the location …
Now 1 axis tracking is becoming a standard for large parks
13
Source: PV course EPFL, C. Ballif
Silicon solar cell
Intensity [kW/m2nm]
3
2
1
Energy [eV]
CBM
c-Si, Eg= 1.12 eV
EF
VBM
Wavelength [nm]
Source: PV course EPFL, C. Ballif
 Theoretical efficiency: 29.4%
 Main practical limitation: surface defects
Silicon solar cell
 Usually Fermi-level pinning of surface
 Surface also heavily recombinative
 Contacting not possible, however
 No carrier selectivity possible
CBM
EF
E
T
M
VBM
H
T
M
Doped silicon solar cell
Contacting remedied with surface doping
Carrier selectivity achieved!
CBM
But… Optical losses
p+
n+
Free carrier absorption
Electronic losses
Bandgap narrowing
Auger recombination
Surface states
EF
Efficiency: 17-19 %
VBM
Old record cell c-Si: PERL cell
The PERL (Passivated Emitter, Rear Locally diffused) cell of the University of South
Wales, Australia is an example for a high efficiency cell. Most of the surface is
covered by an oxide to lower surface recombination. It reaches up to 25 % efficiency.
4 cm2 cell
706 mV
42.7 mA/cm2,
82.8% FF
25.0% efficiency
Challenge:
• Numerous production steps
• All openings at «the limit»
• FZ material (p-type)
• …
Bases for today’s evolutive process (in particular PERC solar cells)
17
M. Green et al. Prog. Photovolt: Res. 22,2014
J. Zhao et al. APL. 22,2014
http://pveducation.org
Source: PV course EPFL, C. Ballif
Back contacted cells
interdigitated back-contacted solar cells
 no contact at the front side
No shadowing losses !
 high current
Easy interconnection in modules
 closer cell/lower costs
• But …. Not an easy process …..
• Requires low cost « masking/aligning »
procedures
Cells at 23% in production (module up to 21.5%), 25 % record
18
Source: PV course EPFL, C. Ballif
Passivating contacts
CBM
EF
Efficiency: 22 – +25 %
VBM
ETM
HTM
Prime example: amorphous/crystalline silicon heterojunction solar cells
Heterojunction c-Si technology
extremely high Voc
contacting challenging
 Hydrogenated a-Si:H provides excellent passivation of c-Si surface
 Recombination-active contacts are displaced from c-Si surface
 Charge can «trickle» through a-Si:H layers, which act as membranes
20
Crystalline Si technology
Diffused junction solar cell
Direct contact between
absorber and metal
=
Recombinative contact
 Lower Voc
Efficiency: 17-19 %
Heterojunction solar cell
Thin semiconductor layer between
absorber and metal
=
Passivated contact
 Higher Voc
Efficiency: 22 – >25 %
Heterojunction c-Si technology
Chemical
baths
c-Si surface
preparation
PECVD
a-Si:H thin films
deposition, intrinsic
and doped: i-n, i-p
PVD
TCO
Metallization
Metallization
Screen printing
+ curing
at 200°C
• SIMPLE PROCESS FLOW, LOW T⁰ / HIGH EFFICIENCY > 22 %
• THIN WAFERS ok even < 100 µm  Voc ~ 750 mV
• LOW TCOEFF < 0.3 %/⁰C / BIFACIAL > 94 %
• LOW LCOE : 4 to 6 €cts/kWh in EU
FRONT EMITTER
REAR EMITTER
Source: C. Ballif, SNEC 2015
VIP SNEC 2015
Thin wafers
Low T process allows use of very thin wafers (no warping of substrates etc.)
Note: current losses may be avoided by improved optical confinement
23
T. Mishima et al, Solar Energy Materials & Solar Cells 95 (1), 2011, 18-21,
B. Terheiden Phys. Stat. A 2015
Thin wafers
Efficiency [%]
24.7
Jsc [mA/cm2]
39.5
Voc [mV]
750
FF [%]
83.2
Pmax [W]
2.510
Total cell area [cm2]
101.8
Cell thickness [mm]
98
M. Taguchi et al, IEEE Journal of Photovoltaics 4(1), 2014, 96-99
 Highest reporeted Voc on any c-Si solar cell with a FF > 80 % !
24
High T advantages
T. Mishima et al, Solar Energy Materials &
Solar Cells 95 (1), 2011, 18-21
Best Tcoefficient for c-Si
between 0.2 and 0.3%/°C (for Voc of around 725 mV)  absolute best value for c-Si
25
Bifacial modules
No full metal coverage at rearside: Bifacial cells and modules
D. Ide, Proc. 33rd IEEE PVSC (2008)
26
Historically
Invented by Sanyo (now Panasonic) , about 25 years ago…
Commerciallized under ‘HIT’ name
27
Processing sequence
Chemical
baths
c-Si surface
preparation
PECVD I
Intrinsic
film
deposition
a-Si:H(i)
PECVD II
Doped film
deposition
a-Si:H(n/p)
Metallization
Screen
TCO
printing
sputtering
and curing
at 200°C
PVD
all processing < 200 degr. C
28
Process flow
Chemical
baths
c-Si surface
preparation
31
PECVD I
Intrinsic
film
deposition
a-Si:H(i)
PECVD a-Si:H
Process:
plasma enhanced chemical vapour
deposition
Process gas
Process gas
Features:
- Process-gas: silane (SiH4) + hydrogen (H2)
- Films can be doped by adding dopant
gasses
-Deposition-rate: ~1-10 Å/s
-Deposition-temperature: ~200 degrees C
-Cross-contamination may be an issue,
hence use of separate chambers for
intrinsic, p-type, and n-type deposition
-employed gasses are explosive – caution
needed
32
Taken from Aberle & Hezel, Prog. in Photovolt.:
Res. Appl. 5 (1997) 29-50
Intrinsic films
For good passivation:
•
•
No epitaxial film growth
Annealing may lead to drastic improvement
[De Wolf et al., Appl. Phys. Lett 90, 042111 (2007)]
[Demaurex et al., J. Appl. Phys. 116, 053519 (2014)]
33
Intrinsic films
For good passivation:
•
•
No epitaxial film growth
Annealing may lead to drastic improvement
[De Wolf et al., Appl. Phys. Lett. 93, 032101 (2008)]
34
Intrinsic films
For good passivation:
•
•
No epitaxial film growth
Annealing may lead to drastic improvement
ATR-FTIR spectrum on thin a-Si:H films
 Stretched exponential behavior as well
 Electronic changes are driven by
microstructural changes!
35
[El Mamdhi et al., Appl. Phys. Lett. 104, 252108 (2014)]
[Holovsky et al., Rev. Sci. Instr. 86, 073108 (2015)]
Intrinsic films
For good passivation:
•
•
•
No epitaxial film growth
Annealing may lead to drastic improvement
a-Si:H/c-Si interface and a-Si:H bulk defect kinetics quite similar
36
[De Wolf et al., Phys. Rev. B 83, 233301 (2011)]
[De Wolf et al., Phys. Rev. B 85, 113302 (2012)]
Intrinsic films
For good devices:
•Go towards the amorphous-to-crystalline transition as much as possible, but NO EPITAXY !
 Use highly depleted silane plasmas
 H2 plasma during a-Si:H growth (‘layer-by-layer’)
power
H2
[Bartlome et al., Appl. Phys. Lett. 94, 201501 (2009)]
[Descoeudres et al., Appl. Phys. Lett. 97, 183505 (2010)]
[Bartlome et al., J. Appl. Phys. 117, 203303 (2015)]
SiH4
t
[Descoeudres et al., Appl. Phys. Lett. 99, 123506 (2011)]
[Geissbuehler et al., Appl. Phys. Lett. 102, 231604 (2013)]
37
Intrinsic films
For good devices:
•Go towards the amorphous-to-crystalline transition as much as possible, but NO EPITAXY !
 Use highly depleted silane plasmas
 H2 plasma during a-Si:H growth (‘layer-by-layer’)
•
Layer properties
 Increase in hydrogen content
ATR-FTIR
 Increase in band gap
 More disordered
 Etching effect if H2 plasma is too long
[Descoeudres et al., Appl. Phys. Lett. 99, 123506 (2011)]
38
Intrinsic films
For good devices:
•Go towards the amorphous-to-crystalline transition as much as possible, but NO EPITAXY !
 Use highly depleted silane plasmas
 H2 plasma during a-Si:H growth (‘layer-by-layer’)
•
Layer properties
 Increase in hydrogen content
 Increase in band gap
 More disordered
 Etching effect if H2 plasma is too long
 Minimum buffer layer thickness to be present!
•
Globally beneficial for devices
5-20 mV gain in Voc
[Geissbuehler et al., Appl. Phys. Lett. 102, 231604 (2013)]
39
Process flow
Chemical
baths
c-Si surface
preparation
40
PECVD I
Intrinsic
film
deposition
a-Si:H(i)
PECVD II
Doped film
deposition
a-Si:H(n/p)
•
Film doping can lead to severe passivation losses
Doped overlayers
[De Wolf et al, Appl. Phys. Lett. 88, 022104 (2006)]
41
•
•
•
Film doping can lead to severe passivation losses
Boron doping can lead to defect formation in intrinsic buffer
Defect formation is governed by Fermi-level position
Doped overlayers
[De Wolf et al, J. Appl. Phys. 105, 103707 (2009)]
42
Process flow
Chemical
baths
c-Si surface
preparation
43
PECVD I
Intrinsic
film
deposition
a-Si:H(i)
PECVD II
Doped film
deposition
a-Si:H(n/p)
PVD
TCO
sputtering
Transparent conductive oxide deposition
Process:
usually done by sputtering
(also known as physical vapour deposition)
Variants include DC and RF-sputtering
(shown example is DC sputtering)
Typical target-material: indium-tin-oxide (ITO)
See e.g. M. Ohring, “Materials Science of Thin
Films”, 2nd Ed., Academic Press (2002)
44
•
•
•
Electronic passivation losses by sputtering
Cause: plasma UV illumination + …
Curing  passivation restored
•
Problem may be further mitigated by ALD TCO’s
[Demaurex, et al. IEEE JPV 4, 1387 (2014)]
[Demaurex, et al. Appl. Phys. Lett. 101, 171604 (2012)]
45
TCO sputtering
Sputtered-induced damage
• Some companies reports excellent results with the use of so-call
ion-plating technique for TCO coating
• The use of sputtering allows likely similar results to be achieved,
but the requirements on the amorphous layers might be
different !
Principle of RPD
or ion assited
evaporation,
Sumitomo
46
Process flow
Chemical
baths
c-Si surface
preparation
47
PECVD I
Intrinsic
film
deposition
a-Si:H(i)
PECVD II
Doped film
deposition
a-Si:H(n/p)
Metallization
Screen
TCO
printing
sputtering
and curing
at 200°C
PVD
Type of wafer
Beyond the B-O complex
Which wafer type is best?
48
n- or p-type c-Si?
• Empirically, higher efficiencies obtained on n-doped wafers
– n-type : several companies and labs with > 20% efficiency, Voc > 720 mV
(Sanyo-Panasonic, Kaneka, LG, INES, CIC, Roth&Rau, AUO, Hyundai HI…)
– p-type : so far all results < 20%, Voc < 700 mV (also less R&D effort)
• But p-type c-Si is the standard for conventional diffused solar cells…
• n-type wafers are therefore much less available on the market
 great practical interest in using p-type substrates !
But is it really possible to produce high-efficiency SHJ cells on p-type ?
Fundamental limitation(s) for p-type SHJ cells ?
49
n- or p-type c-Si?
n-type wafer
p-type wafer
50
standard configuration
Passivation : n-type vs p-type wafers
Solar cell precursors (c-Si passivated with a-Si:H in/ip stacks)
 Loss for p-type due to asymmetry in interface defect (dangling bond)
capture cross-sections for e– and h+ (sn / sp ≈ 10)
[A. Descoeudres et al, IEEE JPV 3, 83 (2013)]
51
Passivation : impact on FF
V
implied
kT æ ( n0 + Dn) ( p0 + Dp) ö
=
ln ç
÷
q è
n0 p0
ø
-
At open circuit  Voc
-
At max powerpoint  Vmpp  FF
[A. Descoeudres et al, IEEE JPV 3, 83 (2013)]
estimation for p-type : 2% in FF is lost compared to the n-type sample
To obtain high FF : high Voc not sufficient, high lifetime at MPP required as well
52
Cells after optimization (4 cm2)
n-type wafer
p-type wafer
(screen-printed contacts)
[A. Descoeudres et al, IEEE JPV 3, 83 (2013)]
On high quality wafers (FZ), cells on p-type are almost as good as on n-type Voc > 720
mV, FF > 77%, eta > 21%
53
Light management
 Reflection from Ag grid and TCO anti-reflection coating
 UV and blue parasitic absorption in front a-Si layers
 UV and IR parasitic absorption in front TCO; IR parasitic
absorption in rear TCO
 Incomplete trapping of IR light
54
Current losses at the front
2
Front Ag grid reflection = 2.8 mA/cm = 6.1%
2
Front ARC reflection = 1.4 mA/cm = 3.0%
EQE and 1-reflection (%)
100
90
80
70
60
50
40
30
20
10
0
2
Escape reflection = 1.3 mA/cm = 2.8%
2
Short- parasitic absorption = 1.5 mA/cm = 3.2%
2
Long- parasitic absorption = 2.4 mA/cm = 5.3%
2
Aperature-area Jsc = 36.7 mA/cm = 79.8%
400
600
800
1000
1200
Wavelength (nm)
 Over 2 mA/cm2 is lost in an optimized heterojunction cell
 All light absorbed in ITO and p-layer is lost, ~70% of light in i-layer is lost
 Model allows us to predict UV/blue current loss for arbitrary layers, provided optical
constants are known
[Z. Holman et al., IEEE JPV 2, 7 (2012).]
55
Current losses at the front
New window layers
Reduction of parasitic absorption through
single-, mixed-phase and alloyed materials:
microstructure and band gap variation
Doped µc-Si:H
Doped and intrinsic µc-SiOx:H
and a-SiOx:H
Doped a-SiC:H
Potential gain in current of up to
~0.8 mA/cm2, but at the expense of
lower FF  transport barrier.
[J.P. Seif et al., JAP 115, 024502 (2014).]
56
a-SiOx layers: results at higher T
Oc120307x - 8xComparison
- 15x
of standard a-Si:H cell
to a-SiOx:H cell (different set)
[J. Seif et al., JAP 2014]
[J.P. Seif et al, IEEE JPV 2015]
For a-SiOx:H cell:
Despite losses in FF at 25 °C
lower temperature coefficient for
a-SiOx:H (-0.1 %/°C) as
compared to a-Si:H (-0.3 %/°C)
(for investigated temperature
range)
Opportunities for tunable temperature coefficient, explanation for
dispersion of Tcoeff among various cells: transport through heterocontact activated thermally
Current losses at the front
Carrier-selective contacts
Reduction of parasitic absorption through wide
bandgap work-function metal oxides
Example: MoOx to replace p-type a-Si:H
[C. Battaglia et al., APL 104, 113902 (2014).]
Combine - Surface passivation
- Carrier selectivity
- Transparency
J. Geisbühler, et al., Appl. Phys. Lett. 107 (2015).
Next step: doping-free solar cells?
58
Current losses at the front
New TCO layers
!!!!
Contact resistance
issue at IO:H / Ag
grid interface
ultrathin ITO
capping layer
needed
-
Free-carrier absorption erodes Jsc
-
Replace ITO with IO:H or other high mobilty TCO
[T. Koida et al, JJAP (2008); L. Barraud et al., SOLMAT (2013).]
59
Current losses at the rear
Evanescent
wave at rear
-3
 parasitic plasmonic absorption at metal surface
 displacement layer needed
cm )
SiNx, 70 nm
Si
dielectric, variable t, nd
Ag
[Z. Holman et al., JAP 113, 013107 (2013).]
[Z. Holman et al., Light Science & Applications (2013).]
500
For a 300-nm-thick layer of air (nd = 1), only 4% of
incident light is absorbed in the Ag layer (rr = 99.8%)
60
New reflectors
Current losses at the rear
100
90
Reflectance (%)
80
70
60
50
40
30
20
10
0
900
1000
1100
1200
Wavelength (nm)
Sub-bandgap reflectance still remains
very high in full device structure.
[Z. Holman et al., IEEE JPV 3, 1243 (2013).]
61
1300
New reflectors
Current losses at the rear
Internal quantum efficiency (%)
100
90
80
Rear reflector
70
ZnO/Ag
ZnO/MgF2/Ag
60
50
ZnO/Al
ZnO/MgF2/Al
40
30
Sanyo, MRS 2010
PERL, Taira 2007
20
10
0
400
600
800
1000
Wavelength (nm)
Jsc, active area
40.5 mA/cm2
[Z. Holman et al., IEEE JPV 3, 1243 (2013).]
41.0 mA/cm2
Best rear reflector ever?
62
1200
Current losses at the front
new world record! 25.6%
Best Jsc: 41.8 mA/cm2
Key points:
1. Silicon heterojunction contacts
2. Interdigitated design
63
 Ultimate single-junction architecture ?
Current losses at the front
1 example of simple manufacturing process for IBC-SHJ Fabrication Process @
EPFL-CSEM
 Full-area intrinsic and n-type aSi:H
 n- and p-type a-Si:H via in-situ
shadow masks
 Full-area a-SiN:H and
TCO/metal
 Interdigitated back-electrode via
inkjet-based process
[A. Tomasi et al., IEEE JPV 4(4), 2014]
[A. Tomasi et al., Proc. 40th IEEE PVSC, 2014]
[B. Paviet-Salomon et al. IEEE JPV 2015]
Current losses at the front
Hot melt
Hot melt
TCO/metal
Metal
a-Si:H
2 mm
a-Si:H
2 mm
2 mm
 Hot melt inkjet printing
 Wet Etching
 Hot melt stripping
[A. Tomasi et al., IEEE JPV 4(4), 2014]
[A. Tomasi et al., Proc. 40th IEEE PVSC, 2014]
[B. Paviet-Salomon et al. IEEE JPV 2015]
Current losses at the front
Back-contacted SHJ
Fully back contacted solar cells
Simple patterning techniques
(3 × 3) cm2 IBC-SHJ devices
Back-side view
[A. Tomasi et al., IEEE JPV 4(4), 2014]
[A. Tomasi et al., Proc. 40th IEEE PVSC, 2014]
[B. Paviet-Salomon et al. IEEE JPV 2015]
66
Metallization
Metallization
Stencil printing
 Mesh + polymer replaced by metal foil
 Narrow lines, high aspect ratio
Screen
Stencil
Plating
[J. Geissbuehler et al. IEEE JPV 4, 1055 (2014).]
67
Screen
Stencil
Reducing the cost of metallization
Cost of metallization (pastes 3 times less conductive)  move away
from standard design
Cu Plating
[Silevo, Kaneka,
Ines, IMT, CSEM ]
5 busbars
[R&R CH]
J. L. Hernandez et al, Proc.
28th EU-PVSEC (2013)
Munoz et al.
J. Geissbühler et al.
P. Papet et al.
D. Bätzner et al.
Proc. 26th EU-PVSEC
2011
Arrays of wire
[Day4 –MBT]
Yoshida et al. Proc. 26th
EU-PVSEC 2011
Cu paste
[AIST, JP]
Source: C. Ballif, SNEC 2015
FINE LINE PRINTING with low T paste
 Fine Line printing with 32 ± 2 µm spreading on HJT cell precursor
 Height of 6 ± 2 µm
 ~ 4- 6 Ohm/cm: compatible w. SmartWire w. low dissipation losses!
32 µm
Source: C. Ballif, SNEC 2015
Other developments: metallization
Low Ag use by smart-wires
 down to 40mg for 156x156 cells, 2-4 c$/Wp saving
on process cost due to low Ag consumption
 Full Al back side for Conventional solar cells ( no
back Ag print and additional process need)
 No need of busbars
 Compatible with fine fingers &
resistive paste
 Outstanding Module longevity
Performance loss of SWCT modules after thermocycling aging
compared to alternative connection technologies. The cells are
metallized with a low temperature silver based paste.
Metallization
Current losses at the front
- Improvement in current
- Ag free
10 micron Ni/Cu plated lines on TCO
[J. Geissbuehler et al. IEEE JPV 4, 1055 (2014).]
Excellent plating results reported by Silevo ( prod), Kaneka, CSEM, INES….!
71
c-Si heterojunction cells: what’s more ?
•
•
•
•
•
Based on coating technologies: all matured in the last years
Infinite number of possibilities to change the layers (plasma !)
Wide variety of TCO’s and interface
Other opportunities for metallization (plating)
…..
a class of technology to reach > 24% ….
72
Source: C. Ballif, SNEC 2015
Becoming a mainstream technology ?
Increase R&D
activities.
Several groups
and industries
above 20% with
screen-printing or
plated contacts
(CIC, INES/EDF,
Kaneka, R&R, LG,
Hyunday,…….)
[De Wolf et al, Green 2, 7 (2012).]
Becoming a mainstream technology ?
• 8-10 process steps depending on counting ….
• Large area reactors for PECVD and PVD well developped
for thin film silicon and flat panel display (not the case 10
years ago)
 Reliable processes with potential for ultra-low cost
compare e.g. for thin film Si, 2xTCO of 1 micron + 2 cells of
200 and 800 nm  COO of 20 €/m2 !
Source: C. Ballif, SNEC 2015
Industrialisation
• What are the manufacturing costs ?
• Panasonic  1 GW, Silevo/Solar city announces >> 1 GW, CIC
with 80 MW, Sunpreme, AUO………
• Meyer Burger, Jusung, efforts with equipment
• All companies starting R&D
75
Source: C. Ballif, SNEC 2015
One example of industrialisation effort
SILICON HETEROJUNCTION IN NEUCHATEL
Microcity
EPFL PVlab
New clean rooms 450 m2
Production and
commercialization
1994 first patent on SHF
2005 resume activity
Dedicated developments
w. industrials on key steps
Source: C. Ballif, SNEC 2015
Partnership with Meyer Burger group
for cell & module production
technologies, w. PASAN for metrology
CSEM Silicon Heterojunction
Solar Cell Platform
PROCESSES UPSCALED in 2014 to
n-Cz full wafer cells
Record cell @ 22.8 %, front emitter cell,
screen printed metallization, busbar less
measured w. GridTouch 
HJT CELL
Full 6’’ PS
wafer printed
n-type Cz
150 µm
VOC
mV
FF
%
JSC
mA/c
m2
EFF
2013
2014
4 cm2 cells,
FZ wafer
Full Cz wafer
cells (5’’ to 6’’)
736
79.8
38.77
22.8 %
Measured with GridTouch
Source: C. Ballif, SNEC 2015
MEYER BURGER RESEARCH PILOT SCALE R&D LINE
In Hauterive, Neuchatel:
MEYER BURGER
RESEARCH
clean room facility
dedicated to pilot scale
R&D for HJT
Alpha tools R&R
PECVD & PVD
Source: C. Ballif, SNEC 2015
MEYER BURGER RESEARCH PILOT SCALE R&D LINE
wafer
Voc
(mV)
FF
(%)
Jsc
(mA/cm2)
eff.
CZ
736.7
81.3
38.64
23.14%GT
Source: C. Ballif, SNEC 2015
achieved in Meyer Burger
PECVD and PVD reactors
with busbar less
screen printed front grid
on diamond wire cut
CZ wafer
Demo line at Roth and Rau /
Germany, Production tools
2000 cells run
22.3% average efficiency,
Measured with grid touch
Courtesy J. Zhao
Source: C. Ballif, SNEC 2015
New record module measurement at
Meyer Burger
329 W module
1.66 m2.
60 cells, full square,
Smart wire
Courtesy T. Söderström
Source: C. Ballif, SNEC 2015
VIP SNEC 2015
Courtesy Y. Watanabe
Perspectives
In principle SHJ technology could displace part of the standard c-Si
technology
• n-type ingot can be made of high quality (higher lifetime than p-type)
• PECVD processes can be mastered, learned from thin film and FPD
• TCO’s coating is mastered
• There are low Ag or no (plating) content solutions
This can give a benchmark at 22% cell efficiency with 0.4-0.5$/W at the
module level !
Questions:
• What with replacement of today’s standard cell capacity, outside
PERC ? Who takes the «risk» first ?
• When do new equipements come in the market ?
• Are the markets based on incentives identical for all technologies
good to bring technologies to the market ?
83
Source: C. Ballif, SNEC 2015
Perspectives
Building block for very high efficiencies
Source: C. Ballif, PV course, EPFL
Intensity [kW/m2nm]
3
2
1
Energy [eV]
c-Si, Eg= 1.12 eV
Top cell, Eg = 1.7 eV
Topcell
Si
Mechanically stacked
Topcell
Si
Wavelength [nm]
Monolithical integrated
Perspectives
CH3NH3PbI3 perovskites
T. White et al., IEEE JPV 4, 208 (2014)
 See talk on Monday!!
Summary
• For any high-efficiency technology, surfce passivation of extrem
concern
• Electricial contact passivation is key to reach Voc > 700 mV
• Intense R&D activities in SHJ, technology ready for mass
industrialization !
• Production technologies with low Ag content readily available !
• With best temperature coefficient (-0.2%-0.27%/°C), and good ntype Cz with little constraint on doping,  SHJ ideal PV technology !
• Ideal building block for ultra-high efficiency (tandem) concepts
• They are multiple variation of SHJ allowing differentation for
industries and research institute.
Thank you for your attention !
Thanks also to
Organizing commitee!
C. Ballif, Loris Barraud, Richard Bartlome, Benedicte Demaurex, Antoine
Descoeudres, Jonas Geissbuhler, Bertrand Paviet-Salomon, Johannes Seif,
Andrea Tomasi;
All members PVcenter, CSEM & PVlab, EPFL;
C. Battaglia, A. Javey, UC Berkeley;
J. Bullock, A. Cuevas, ANU;
M. Filipec, M. Topic, Uni Ljubljana;
Z. Holman, ASU;
J. Holovsky, M. Ledinksy, Institute of Physics, Prague
Acknowledgement for funding
• Swiss Federal Office for Energy
• EU FP6 and FP7, CTI, FNS, Axponaturstromfonds, Eurotech
• Meyer-Burger