REFERENCE VOLTAGE DRIVER FOR LOW-VOLTAGE CMOS A/D CONVERTERS
Mikko Waltari, Kari Halonen
Helsinki University of Technology, Electronic Circuit Design Laboratory
P.O.Box 3000, FIN-02015 HUT, Finland
Tel: +358-9-4512274, Fax: +358-9-4512269, Email: Mikko.Waltari@hut.fi
ABSTRACT
A circuit for generating reference voltages for an A/D
converter is presented. The circuit consisting of a bandgap
reference and a driver circuit is capable of operating on
sub 1-volt supply voltages. The circuit is designed using a standard 0.5 m CMOS technology. Simulations
show maximum 0.24% variation in the generated reference voltage over a temperature range from -20 Æ C to
100Æ C and a supply voltage range from 0.95 V to 1.50 V.
The circuit is capable of driving a 2 pF switched capacitor load at 5 MHz clock rate while consuming 450 W
of power from a 1.0 V supply.
−
V2
+
V1
Vref
V2
R3
R1
N
R2
R4
Figure 1: Low voltage bandgap reference proposed in
[5].
by folding a traditional BGR circuit from nodes V1 and
V2 to ground. The feedback loop consisting of an opamp
and a pair of matched controlled current sources forces
the voltages V1 and V2 to be equal. Consequently the
current through the resistor R1 is proportional to the built
in diode voltage V f and the current through the resistor R3 to the difference of two built in voltages ( V f ).
Setting the resistor R2 equal to R1 makes their currents
the same. Since the current of the controlled source is
the sum of currents through R2 and R3, it will be proportional to V f K V f , which is exactly what is
needed for a temperature independent reference. This is
based on the fact that the two terms in the sum have temperature coefficients of different sign and thus by adjusting the factor K they can be made to cancel each other.
The generated current is mirrored through the resistor R4
producing the reference voltage over the resistor.
In this design some modifications are made to the
circuit of Fig. 1. The resulted circuit is shown in Fig. 2.
First the output impedance of the current sources is improved by adding cascode devices. This is important in
order to reduce the supply voltage sensitivity of the voltage V ref . In the original design the opamp inputs are
connected to the voltages V1 and V2 that are roughly in
0.7 V level, which is not a suitable input for an opamp
in a 1-volt design. To overcome that the resistors R1 and
R2 are divided into two series connected parts. Now the
voltages V3 and V4, which are nominally set between
150 and 200 mV, are in proper range for an opamp with
PMOS input transistors.
The BGR circuit has two stable operation points: the
desired one and the case when the current is zero i.e.
1. INTRODUCTION
The increased demand for portable devices and the technology scaling are driving down the supply voltages of
digital circuits. A large number of application contain
some analog circuitry which is beneficial to integrate in
the same die with the digital system in order to increase
the integration level. A typical example of such an analog circuit is an analog-to-digital converter (ADC). The
switched-opamp (SO) technique [1], which is a low voltage modification to the well known switched-capacitor
(SC) technique, has been successfully employed to realize ADCs operating on sub 1-volt supply voltages [2],
[3], [4]. Their usability, however, is limited by the fact
that the reference voltage has to be supplied externally.
To fill this gap there is a need for a low-voltage on-chip
circuit that can provide a stable reference voltage and
drive it into a switched capacitor load. The best way to
generate the voltage is to use a bandgap reference (BGR)
circuit. Unfortunately, the most of the known CMOS realizations are not suitable for 1.0 V supply voltage. The
design presented in this paper utilizes a modified version
of the bandgap reference proposed in [5] and also contains a driver circuit that provides differential reference
voltages to the switched capacitor load.
+
2. CIRCUIT DESCRIPTION
2.1. Bandgap Reference
The low voltage bandgap reference proposed in [5] is
shown in Fig. 1. Its low voltage capability is achieved
0-7803-6542-9/00/$10.00 © 2000 IEEE
V1
28
V3
−
V4
+
Vc
Ib
V1
V2
R1a
R3
Vref
R2a
V3
n5
V4
N
R1b
Ib
R4
R2b
Bias Circuit
Figure 2: Designed bandgap reference including a bias circuit.
Rstart
V1
V1
n5
Iref
Vc
−
M1
+
n1
A1
Vref+
R1
n2
n3
A2
Vref-
M2
V1
Figure 5: Driver circuit for generating differential references voltages from the current provided by the bandgap
reference.
Figure 3: Startup circuit for the bandgap reference.
voltages V1 and V2 are both zero. To ensure that the
circuit always ends up to the correct operation point the
startup circuit shown in Fig. 3 is added. There the resistor Rstart is used to produce a current which is injected
into the node V1 of the BGR circuit if the voltage V1
goes below one threshold voltage of a NMOS transistor. In the desired operation point the voltage V1 is well
above the threshold and thus the startup circuit has no effect on the BGR circuit. Since the opamp is biased from
the BGR the startup circuit also ensures that its bias current doesn’t go to zero.
The opamp used in the circuit is shown in Fig. 4.
It consists of a PMOS input folded cascode first stage
with a low voltage current mirror and a rail-to-rail output
stage.
tween the supply rails. The operation of the circuitry in
these ADCs consists of two phases — each lasting half
of the clock cycle. Consequently the capacitors have to
be loaded to the reference voltages in half a clock period.
The proposed driver circuit is shown in Fig. 5. There
the reference current Iref is supplied by the bandgap reference, which is the circuit of Fig. 2 without the resistor
R4. The current is mirrored with transistor M2 to go
through a floating resistor R1 matched with the resistors
in the bandgap reference circuit. As a result the differential reference voltage appears across the resistor R1. A
feedback circuit consisting of an opamp controlling the
current source transistor M1 is used to set the common
mode level of the reference voltages. The bias voltage V1
is generated with a dummy circuit. To improve the accuracy of the current mirroring the voltage Vc is adjusted
in such a way that the voltage of the node n3 tracks the
node n2.
The generated reference voltages in nodes n1 and n2
are buffered with the unity gain buffers A1 and A2. The
circuit of the buffer A1 is shown in Fig. 6. It is a amplifier, which consists of a differential pair and a low voltage current mirror load, connected in unity gain feedback. The cascode transistor is biased in such a man-
2.2. Driver Circuit
The voltage provided by the bandgap reference is generated over a resistor and thus not suitable for supplying a
switched capacitor load. Typically the ADCs (pipelined
or delta-sigma) based on switched-capacitor or switchedopamp technique utilize fully differential circuitry which
demands the reference voltage also to be differential i.e.
to be a difference of two voltages set symmetrically be-
29
Cc
Ib
In-
In+
Out
Figure 4: Low voltage opamp employed in the bandgap reference.
and its voltage is reset. The other capacitor is controlled
using the opposite clock phase. The output waveform
simulated using a 1.0 V supply and 5 MHz clock rate is
shown in Fig. 8. There the upper plot shows the single
ended voltages while the differential signal is shown in
the lower one. It is seen that the voltages are well settled in the available time. The power consumption of the
circuit is 450 W and it is dominated by the unity gain
buffers.
n1
Vc
Ib
Out
In
4. CONCLUSION
This paper described the design of a reference voltage
source and a driver circuit that are capable of providing
differential reference voltages for a low voltage pipelined
or delta-sigma ADC. The design utilizes a low voltage
bandgap reference circuit to produce a reference current
from which the differential reference voltages are generated across a floating resistor and buffered with unity
gain buffers. This design fills yet another gap in the
way of commercial usage of analog-to-digital converters
based on the switched-opamp technique.
Figure 6: Unity gain buffer for driving the positive reference voltage.
ner that the node n1 tracks the input voltage in order to
minimize the systematic offset due to the amplifier imbalance. The buffer A2 is similar to A1 except that all
NMOS transistors are replaced with PMOS devices and
vice versa.
3. SIMULATIONS
5. REFERENCES
The bandgap reference was simulated by sweeping the
temperature from -20 ÆC to 100Æ C and the supply voltage from 0.95 V to 1.50 V. The resulted output voltage
as a function of the temperature is presented Fig. 7. The
two curves represent the simulations made using the supply voltages at the extremes of the desired range while
the other supply values in the range will give results in
between. Calculated from the curves the difference between the maximum and the minimum voltage is less
than 0.24%.
A transient analysis is used to verify the operation
of the driver circuit. A pair of 2 pF capacitors is used
as a load in both differential outputs. One capacitor is
connected to the reference for half of the clock period —
during the other half it is disconnected from the driver
[1] J. Crols, M. Steyaert, “Switched-opamp: an approach to realize full CMOS switched capacitor circuits at very low power supply voltages.”, IEEE
J. Solid-State Circuits, vol. 29, pp. 936–924, Aug.
1994.
[2] M. Waltari, K. Halonen, “An 8-bit Low-Voltage
Pipelined ADC Utilizing Switched-Opamp Technique”, in Proceedings of the 25th European SolidState Circuits Conference, Sep 1999, pp. 174–177.
[3] M. Waltari, K. Halonen, “1.0-Volt, 9-bit Pipelined
CMOS ADC,” in Proceedings of the 26th European Solid-State Circuits Conference, Sep. 2000, pp.
360–363.
30
Generated reference voltage versus temperature
721.2m
721m
720.8m
Voltages (lin)
720.6m
720.4m
720.2m
720m
719.8m
719.6m
-20
0
20
40
60
Temperature (lin) (DEG_C)
80
100
Figure 7: Generated reference voltage versus temperature using a 0.95 V (solid curve) and a 1.5 V (dashed curve)
supply voltage.
[4] V. Peluso, P. Vancorenland, A. M. Marques, M. S.
Steyaert, W. Sansen, “A 900-mV Low-Power
A/D Converter with 77-dB Dynamic Range”, IEEE
J. Solid-State Circuits, vol. 33, pp. 1887–1897, Dec.
1998.
1
Voltages (lin)
800m
[5] H. Banba, H. Shiga, S. Umezawa, T. Miyaba, T.
Tanzawa, S. Atsumi, K. Sakui, “A CMOS Bandgap
Reference Circuit with Sub-1-V Operation,” IEEE
J. Solid-State Circuits, vol. 34, pp. 670–674, May
1999.
600m
400m
200m
0
280u
280.1u
280.2u
280.3u
Time (lin) (TIME)
280.4u
280.1u
280.2u
280.3u
Time (lin) (TIME)
280.4u
280.5u
1
Result (lin)
800m
600m
400m
200m
0
280u
280.5u
Figure 8: Simulated driver output waveform showing
single-ended voltages in upper plot and differential voltage in the lower one.
31