Doing DSP Workshop
Summer 2009
Lab Exercise 5
Contents
1 Overview
1.1 Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
3
4
2 Exercise
2.1 Timer-BlinkingLED . . . . . . . . . . .
2.2 ADC-Simple DACtoADC . . . . . . .
2.3 Adding high resolution to the DAC
2.3.1 Some research needed . . . .
2.3.2 Making the needed changes .
2.3.3 For what it might be worth .
2.4 Direct Digital Synthesizer . . . . . .
2.5 Using interrupts . . . . . . . . . . . .
2.6 Measuring transfer functions . . . .
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A Transfer Function Measurement main code
14
B Spartan-3 filter and display combined top VHDL
14
Lab Exercise 5
1
August 3, 2009
Doing DSP Workshop
Summer 2009
1 Overview
This exercise pretty much reflects what one does in actual practice to learn about
working with the Piccolo control stick. One buys the unit, hunts on the web for
more information, installs the software and experiments. Lots of scanning and
reading of pdf files in order to what information is available and where. Much
of the available information has been included on the Workshop CD saving you
a part of the effort.
The major parts of the exercise are:
• The blinking LED example contained in V1.1 controlSTICK collection is
used as a practice piece. The controlSTICK collection supports execution
from RAM and from flash EPROM. The blinking LED code is to be built and
tested using both methods. A blinking LED is often handy to show activity
when running programs that otherwise do not have any activity indication.
• The C28027 has several channels of A/D conversion but does have provision for an external D/A converter. The controlSTICK is designed to make
use one of the pulse width modulators (PWM) as a one-bit D/A converter.
The bit is switched at a high rate relative to the frequencies in the desired
waveform. A simple RC low pass filter is used to reject most/much of the
high frequency content leaving the desired low pass waveform.
The controlSTICK SimpleDACtoADC example is used as given given and
with the resulting DC output and its ripple being studied as a function of
duty cycle.
• The SimpleDACtoADC code is modified to allow setting the A/D sample
rate and using the sample values to control the PWM duty cycle. This is
done simulating a 5 bit D/A and a 7 bit D/A.
• The SimpleDACtoADC code is further modified using the high resolution
mode which allows controlling pulse width to very small fractions of one
CPU clock cycle. This essentially allows attaining 12-bit DAC performance.
The amount of remaining ripple at the RC filter output is examined.
• The code is further modified by replacing the A/D converter with a direct
digital frequency synthesizer turning the controlSTICK into a sine wave
signal generator. Sine values are obtained using the boot ROM sine table.
• Exercise 3 of the One-Day Workshop is used as the starting point for a
simple filter transfer function measurement program. This program brings
together the A/D, high resolution PWM D/A, and direct digital synthesizer
Lab Exercise 5
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August 3, 2009
Doing DSP Workshop
Summer 2009
and adds complex demodulation, filtering and display generation. An SPI
channel is used to link the controlSTICK and the S3SB.
The filter tested as well as the display support are implemented on the
Spartan-3 Starter Board. This is a good illustration of merging two existing
VHDL projects into a single project by the use of a higher top VHDL level.
The transfer function measurement code is provided in complete final
form. The main thrust of this part of the exercise is using it to measure a
transfer function. Practice. I haven’t figured how to make this code into a
more user involved exercise.
More concisely, the exercise
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•
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•
•
provides practice using the supplied LED blinker code,
introduces the use of a PWM modulator as a D/A converter,
makes use of a timer to control A/D sample times,
demonstrates A/D in to D/A out operation,
extends the D/A quality using the PWM high resolution support,
implements a DDS using the boot sine table,
combines the above along with adding an A/D channel with SPI link to a
VHDL display design along with demodulator and display generation code.
The result is a very usable transfer function system.
As is often the case with my lab exercises this one is on the long side. It
consists a collection of developmental steps that lead to the implementation of
a working test/evaluation instrument. It pretty much follows the steps that I
took to reach this goal. I started, as the student will, pretty much cold having
had little previous contact with the controlSTICK.
Enhancement of the result will be left for possible future work or as a project
for the student.
1.1
Files
The files for this exercise are contained in
• Piccolo controlSTICK_v1.1.exe. You get to choose the installation directory. It is suggested that you specify a subdirectory, controlSTICK, in
your copy of the lab05 directory. These files are version 1.1 of the files
supplied on the CD that comes with the controlSTICK.
• sprt517.zip. This contains the executable for setting up the C2000 Piccolo 1-Day workshop materials. You get to choose the installation directory. It is suggested that you specify a subdirectory, OneDay, in your copy
of the lab05 directory. These are the files used in the controlSTICK introductory exercise. You should already be quite familiar with them.
Lab Exercise 5
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August 3, 2009
Doing DSP Workshop
Summer 2009
• The directory TFmeasV01. These are the files used to generate the controlSTICK filter transfer function measurement program.
After installing the files, spend some time browsing them to see what’s there.
We will be working with only a small subset.
The controlSTICK collection appear to be derived from versions used on earlier C28x devices. They apparently work on the controlSTICK but the conversion,
in particular for the .cmd files, is not complete. The controlSTICK exercise are
designed to be executed from either RAM or flash ROM. The top left box is used
to select the project version.
1.2
References
The following are in addition to the documentation files included with the controSTICK software and the TI One Day Workshop files.
• TMS320x2802x Piccolo Enhanced Pulse Width Modulator Module Reference
Guide, spruge9.pdf.
• TMS320x2802x Piccolo High Resolution PWM Reference Guide, spruge8.pdf.
• Using PWM Output as a Digital-to-Analog Converter on a TMS320F280x Digital Signal Controller, spraa88.pdf.
• Running an Application from Internal Flash Memory on the TMS320F28xxx
DSP, spra958h.pdf.
It is suggested that you also read the chip errata. Mainly for the experience.
Devices like the Piccolo are very complex. There will be bugs. It sure helps if one
is aware of the known ones.
PWM is frequently used to implement low cost D/As in embedded systems.
Information can be found using Google.
2 Exercise
2.1
Timer-BlinkingLED
This is a controlSTICK v1.1 exercise. This exercise gives practice with the controlSTICK and the associated tools.
Illustrates timer use. Look at the cmd file. Does the memory usage reflect the
memory present in the C28027? If not, this cmd file will need to be modified if
used by other programs. This file appears to be from earlier project.
Lab Exercise 5
4
August 3, 2009
Doing DSP Workshop
2.2
Summer 2009
ADC-Simple DACtoADC
This is a controlSTICK v1.1 exercise. This was my starting point for investigating
use of a pulse width modulation to implement a digital-to-analog converter.
Run as given. Investigate the output waveform. Can you see any significant
amount of ripple?
The A/D converter is programmed to convert samples as fast it can. The end
of conversion (EOC) is used cause the next start of conversion (SOC). We want to
have more control over the sample rate. One way to do this is to use one of the
timers.
Insert the code below just following the existing ADC initialization code.
// CPU TIMER 0 INITIALIZATION .. KM
//===============================
#define fs 16000
CpuTimer0Regs.PRD.all = 60000000/fs;
CpuTimer0Regs.TCR.bit.TIE = 1;
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 1;
// let timer assert ireq
// use trigger on timer 0 TINT
The value of fs sets the A/D sample rate in Hz, within truncation error.
Change period from 30 to 32, an integer power of 2. Note that this use of
period as a variable was not uniform. Locate possible other uses that need to be
made variable (e.g., is 15 supposed to be half the period?).
The period value determines the number of cpu cycles there are between
pulse starts. The duty cycle of the pulse establishes the pulse’s average value. A
period of 32 gives separation of 0.53 µs between pulses. A duty cycle value of 0
produces no pulses, DC value of 0. A duty cycle of 1 gives a DC level of vcc/32.
A duty cycle of 16 gives a DC level vcc/2. Etc.
Modify the code so that the top 5 bits of A/D samples are used to control the
pulse width. The Piccolo A/D values are in straight binary, use the low 12-bits
of a 16-bit word. Use the signal generator set at 1000 Hz to examine the D/A
output as the input level is varied. Will need to use a offset on the generator or
use level shifting amplifier from an earlier exercise. The quanta steps should be
very obvious on the scope output. Experiment with the input frequency to get
a feel for the range of input frequencies which this A/D, D/A combination work
well together.
Modify the code to implement a 7-bit converter. You will need to set the
period to 128 and use the top 7 bits of the A/D sample values. Look at the
Lab Exercise 5
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August 3, 2009
Doing DSP Workshop
Summer 2009
output. Measure the ripple frequency. Is you would expect? Determine the
peak-to-peak ripple amplitude for mid-scale.
Experiment with the input frequency to get a feel for the range of input frequencies which this A/D, D/A combination work well together.
Vary the signal generator frequency to determine the 3 dB down frequency at
the DAC output. Any surprises?
2.3
Adding high resolution to the DAC
This part of the exercise investigate PWM-FilteredHRPWM.
The high resolution support allows dividing a 16.67 ns clock interval into
nominally 256 sub intervals. The division process appears to make use of a
tapped delay line made using CMOS technology. The delays are operating voltage
and temperature sensitive. The Piccolo contains a subsystem that can be used to
continually monitor and adjust the delays. Use of this adds more complication
than desired at this point so we will not make use of it.
The nominal delay resolution is 1/111 of a 16.67 ns interval. We will take
this as exact and unchanging.
2.3.1
Some research needed
Compare how the timer is set up in ADC-Simple DACtoDAC and how how it is
set up in PWM-FilteredHRPWM. The difference is about three lines of code. Copy
from “Filtered” into “Simple”.
The PWM period is set to 32 clock intervals. The top five bits of the A/D
sample are used to select the coarse part of the delay that we want to use.
The low 7 bits are taken as a Q7 fractional value in the interval [0,1). This
value multiplies 111 to give a Q7 value. The integer part is used to select the
fine resolution.
The code combining the coarse and fine values into a 32-bit value is a bit
convoluted. I’ve not looked closely but it should be possible to load the 16-bit
coarse and fine registers separately.
Lab Exercise 5
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2.3.2
Summer 2009
Making the needed changes
Set the period to 32. This nominally gives a 5-bit DAC. The high resolution
capability will allow varying the pulse output in steps about 1/256 one clock
interval. We will modify the code to make the DAC output nominally correspond
to a 12-bit DAC.
Examine the ripple, period and peak-to-peak amplitude. Check the 3 dB down
frequency.
2.3.3
For what it might be worth
You should try your hand at doing the code modifications needed to make use
of the high resolution PWM capability. With some trepidation I’m including my
changes in case you need help. Use sparingly. I think that they are correct, but
....
Here is the code that I placed just following the PWM initialization code.
// Set HiRes registers
EALLOW;
EPwm1Regs.HRCNFG.all = 0x0;
//EPwm1Regs.HRCNFG.bit.EDGMODE = HR_REP;
EPwm1Regs.HRCNFG.bit.EDGMODE = HR_FEP;
EDIS;
//Initialize HiRes PWM Control Register
//Enable HiRes control on Rising edge
//Enable HiRes control on Falling edge
You should try both settings of the EDGMODE value to see what the differences
in the resulting waveforms are. The commented out setting (HR_REP) is the way
the code sort of came. I guessed at the name of setting that I ended using.
Here is the code that I inserted following reading a sample value into the
adc_result register.
// set period to power of 2
period = 32 -> 5 bits
// adc is Q12
// coarse_steps = (adc_result*period >> 12);
coarse_steps = adc_result >> 7;
//mep_steps = 255-((mep_sf*(adc_result&0x7F))>>7); // not rounded
mep_steps = ((Uint32)mep_sf*(adc_result&0x7F)+64)>>7;
duty_cycle = ((Uint32)coarse_steps<<8)+mep_steps;
EPwm1Regs.CMPAM.all = duty_cycle<<8; // Update the compare A register using the
// union of the CMPA and CMPAHR registers.
// This value will change the level of the
// PWM1A_DAC output. The value of this variable
// must be between 0 and 1E00h (period*65536)>>8
// The lower 8 bits are do not care.
mem_sf was initialized to 111.
Lab Exercise 5
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August 3, 2009
Doing DSP Workshop
2.4
Summer 2009
Direct Digital Synthesizer
In the above section we learned how to make a high resolution D/A converter
nominally having 12-bit performance (neglecting ripple). In this part the exercise
we replace the A/D converter as the D/A input by a direct digital synthesizer
creating a basic sine wave signal generator.
ROM
analog output
DAC
register
clock
fs
adder
FTV
Figure 1: Basic direct digital waveform synthesizer block diagram.
Using a ROM containing one period of a sine wave the output frequency is
f0 = FTV
fs
2B
where FTV is an integer, fs is the update rate, and B is the number of bits in the
register. The register is sometimes referred to as a phase accumulator. Use a
long as the accumulator.
Configure the controlSTICK program that we have been working to use a sample clock of 100 kHz.
Before using the boot ROM sine table we need to locate it and determine its
format. I had to work at this a bit. The TMS320x2802x Boot ROM is documented
in sprufn6.pdf. The table size is given as 1282 words. The values are 32 bits in
size and use the Q30 format. The table is said to contain 1 and a quarter cycles
of the sine function.
I unzipped the Boot ROM files. The file, IQmathTables.ASM names the table
as _IQsinTable and states that the table size is 644 × 16. I don’t know why.
The table itself contains 641 32 bit values. This implies 512 values per period,
one and a quarter periods plus 1. Values range from -1 to +1 inclusive (this is
made possible by the use of the Q30 format). I located the linker map file and
determined that this table is loaded into memory address 0x003FE000. I then
Lab Exercise 5
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August 3, 2009
Doing DSP Workshop
Summer 2009
checked using CCS to verify the location. Hopefully the table remains at this
location in future versions of the boot code.
Generate a 1000 Hz sine wave output on the PWM1A-DAC output using the
high resolution mode PWM operation. The C28027 clock has a nominal accuracy
of 1%. Using an oscilloscope check to see how the 1000 Hz DDS output frequency
is compared to the crystal controlled Agilent signal generator set to 1000 Hz
used in the lab. Suggestion: use two channels and either (or both) tune the
Agilent for zero dift or measure the time required for the the two waveforms to
drift by one cycle relative to each other.
2.5
Using interrupts
The DDS will operated stand-alone under interrupts. Transparent to the background application. Left for some future exercise.
2.6
Measuring transfer functions
The basic theory behind measuring transfer functions was covered in lecture.
The basic steps consist of
• Generate a sine wave at a given frequency using a DDS.
• Use the DDS output as input to the FPGA filter. Digitize two channels, one
at the filter input and one at the filter output.
• Use the Fourier shifting theorem to move the carrier to DC. Using the above
DDS to generate the needed sine and and cosine waveforms preserves the
phase information.
• Low pass filter to remove the −2fc component.
• Measure the magnitude and phase of the waveforms at the filter input and
at the filter output.
• The filter gain at the given frequency is the output magnitude divided by
the input magnitude.
• The filter phase shift is the phase angle measured at the output minus the
phase measured at the input.
• Plot.
• Repeat at as many frequencies as desired.
For this exercise the filter and the display system will be coresident in the
FPGA.
Figure 2 is a basic block diagram showing the implementation up to the magnitude and angle computation.
Lab Exercise 5
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Doing DSP Workshop
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low pass filter
so (n)
si (n)
xo′′ (n)
cos(2π nfc /fs )
− sin(2π nfc /fs )
low pass filter
yo′′ (n)
low pass filter
xi′′ (n)
cos(2π nfc /fs )
− sin(2π nfc /fs )
low pass filter
yi′′ (n)
Figure 2: Central operations used to make transfer function measurements. The
output values are to be converted in to relative magnitude and relative phase,
properly scaled and plotted.
Figure 3 shows the connections that need to be made between the controlSTICK and Spartan-3 Starter Board.
Figure 4 illustrates the use of a white connection white block to make the
desired connections.
Figure 5 show an example output display.
The question at this point is how to convert transfer function measurement
into a part of this lab exercise. The exercise is already on the long side. Some
thoughts are:
• to split it into a separate exercise with the display support provided with
the student doing the frequency shifting, filtering and magnitude/phase
calculations.
• to use integer arithmetic to compute the magnitude and phase. The C28x
supports 64 bit integers. The integer x and y values are 32-bits. They can
be squared and added. The magnitudes squared can be normalized to be
fractional values between [0.5,1). It is fairly straight forward to compute
the log base 2 using integer arithmetic and then convert the result into dB.
Similarly the x and y values can be converted into (-1,1) Q15 values and an
integer two argument arctangent can be writen and used to compute the
phase. Clearly this is well beyond the scope of this exercise.
Lab Exercise 5
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Doing DSP Workshop
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Piccolo
controlSTICK
PWM1A-DAC
ADC-A1
S3SB
31
12
1
J3
AD1
ADC-B1
6
MIB
1
J7
DA2
SPISIMI
SPISIMO
SPISTE
SPICLK
GND
20
24
25
29
28
1
2
3
4
5
B1
J8
Figure 3: Wiring connections for the Piccolo/S3SB transfer function measurement and display.
• to use the CORDIC algorithm to compute the magnitudes and phases. This
can be done relatively simply using integer arithmetic and is relatively
straight forward to implement in a FPGA. This leads to the thought of implement the transfer measurement device entirely in the FPGA.
• to implement various filters in the FPGA replacing the supplied sinc filter.
Confidence in the filter’s basic operation would be built by using the piccolo
transfer function measurement code. It would remain to somehow validate
filter overflow protection.
• to add off-line storage in the form of a SD card. Sparkfun sell a SD card
breakout board at low cost. This could be added either to the controlSTICK
or the FPGA. Adding to the FPGA likely makes the most sense. It could be
used to archive drawing commands in files. These could be processed on a
PC using a program that interprets the commands and generates Postscript
output.
• to ?
For the present it is left for the student to build the C executable and place
the executable into the piccolo flash ROM, build the filter/display VHDL and
download it into the S3SB and get everything to run.
The files for the controlSTICK include:
Lab Exercise 5
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Figure 4: Connections between the Piccolo controlSTICK, white block and the
Spartan-3 Starter Board. The filter output is also being observed on an oscilloscope.
Adc.c
CodeStartBranch.asm
DefaultIsr_TFmeasV01.c
DelayUs.asm
DisplayTest00.c
DSP2802x_GlovalVariableDefs.c
EPwm_TFmeas_V01.c
Flash.c
Gpio.c
PieCtl.c
PieVect.c
Spi.c
SysCtl.c
TFmeasV01.c
Watchdog.c
XVGA.c
DSP2801xHeaders_nonBIOS.cmd
TFmeasV01.cmd
initializes the A/D.
starts C28027 when stand alone.
interrupt service routines.
generates a delay.
generates the grid and labels.
initializes enhanced PWM.
needed when executing out of flash.
initializes GPIO pins.
initializes interrupts.
interrupt vector.
implements spi link to FPGA.
initializes the processor.
main. Implements the application.
watchdog support, disabled.
initialize, goto and draw routines.
memory allocation.
Spi.c is located in the support directory.
Lab Exercise 5
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Doing DSP Workshop
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Figure 5: Example filter transfer function measurement display. Magnitude vs
frequency on the left and phase vs frequency on the right.
Many of these are support files from the TI One-Day Workshop. If I managed
to keep focused on what I was doing the files that have modified have renamed
from TI’s original names. Comments containing !!KM indicate my modifications
or new lines or commented out lines.
The files for the S3SB FPGA include:
TF_top.vhd
combines FIR_test_V01 with VGA07.
This is a toptop file that merges the VGA07 files starting with VGAtop.vhd and the
lab03 files starting with FIR_test_V01.vhd. Use the lab05_spartan3.ucf file. The
support directory contains several files that are used by the two sub-projects.
Lab Exercise 5
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Doing DSP Workshop
A
Summer 2009
Transfer Function Measurement main code
B Spartan-3 filter and display combined top VHDL
Lab Exercise 5
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August 3, 2009