An On Chip Low Skew Optical Clock Receiver
by
Allan Marn Loy Lum
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulllment of the requirements for the degree of
Master of Engineering in Electrical Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
August 2001
c Massachusetts Institute of Technology 2001. All rights reserved.
Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Department of Electrical Engineering and Computer Science
August 30, 2001
Certied by. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Duane Boning
Associate Professor of Electrical Engineering and Computer Science
Thesis Supervisor
Accepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Arthur C. Smith
Chairman, Department Committee on Graduate Students
2
An On Chip Low Skew Optical Clock Receiver
by
Allan Marn Loy Lum
Submitted to the Department of Electrical Engineering and Computer Science
on August 30, 2001, in partial fulllment of the
requirements for the degree of
Master of Engineering in Electrical Engineering
Abstract
Clock distribution across a digital chip raises several serious issues in current and
future integrated circuit technology. The distribution of clocks with frequencies in
the giga-hertz range is dicult because of interconnect parasitics. Clock skew due
to variation sources is becoming dicult to control with traditional balanced distribution networks. Optical interconnects are currently being evaluated as a technique
to distribute a clock signal throughout a digital chip. Optics provides the potential
for very low skew distribution. This thesis presents a design for an optoelectric clock
receiver operating at 1 GHz. The design has been simulated successfully and a full
circuit layout has been completed. The impact of variation sources from the input
signal, process, and the environment have been evaluated. Process variation is found
to contribute most to skew. A strategy has been prepared for testing the fabricated
chip. The result is a simulation and layout of a fully functional CMOS optical clock
receiver in 0.18m technology operating at 1 GHz.
Thesis Supervisor: Duane Boning
Title: Associate Professor of Electrical Engineering and Computer Science
3
4
Acknowledgments
These past ve years here at MIT have been a very good experience for me. I am
very fortunate that it is nally culminating with the completion of this thesis. It has
been a long ride though, and as a result, there are several people that I would like to
thank for their support.
I would rst like to thank my thesis advisor, Professor Duane Boning, for taking
me on as a student for such a short time frame. He encouraged me along through
continual faith and sound advice. I would have never been able to complete this thesis
in eight months without his support.
I would also like to thank Professor Anantha Chandrakasan for referring me to
Professor Boning and for advising me throughout the thesis. Ron Roscoe, thank you
for giving me the opportunity to be TA. I have learned many wonderful things from
that experience.
Bunnie and Shamik, thank you for your friendship and awless technical support
throughout my MIT experience. They have both pulled me out of countless dicult
situations. Special thanks to Bunnie, whose Cadence tutorials cut a month o of my
thesis schedule. I would also like to thank Bginzz, Pedro, Bobby, and all my other
friends at ZBT for putting up with my complaints and rants of frustration over the
years.
I would next like to thank my oce colleagues. Mike and I were working on
similar thesis projects and compared their diculty to \trying to teach a monkey
how to speak Chinese." Well Mike, the monkey can now say a few words; I leave
it up to you to nish the job. Aaron, thank you for your computer and network
assistance and for introducing me to the great hot chocolate machine. Joe, Karen,
Vikas, Han, Dave and Brian, thank you for all the interesting conversations and for
contributing to an enjoyable work environment.
I would also like to thank my family for their support throughout the years. Mom,
Dad, thank you for shielding me from many problems and allowing me to focus on my
interests. Randy, Lyn, Shane, Jimmy, Bernie, Mike, Stephanie, and Laressa, thank
5
you for your encouragement and words of wisdom.
This work has been supported in part by MARCO and DARPA under the Interconnect Focus Center program.
6
Contents
1 Introduction
17
2 Design Strategy to Minimize Skew and Eects of Variation
23
1.1 Motivation for On-Chip Opto-Electronic Clock Distribution . . . . .
1.2 Previous Receiver Designs . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Generalized Topology . . . . . . .
2.2 Variation vs. Low Skew . . . . .
2.3 Design Implications/Challenges .
2.3.1 Photodetector . . . . . . .
2.3.2 Transimpedance Amplier
2.3.3 Voltage Amplication . . .
2.4 Receiver Topology Overview . . .
2.5 Summary . . . . . . . . . . . . .
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3 Circuit Design and Operation
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3.1 Operation Amplier Designs . . . .
3.1.1 Two-Stage Opamp . . . . .
3.1.2 Folded Cascode Opamp . .
3.2 Transimpedance Amplier . . . . .
3.3 High Bandwidth Voltage Ampliers
3.3.1 Cascode Architecture . . . .
3.3.2 Feedback Biasing . . . . . .
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31
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3.4 Output Stage . . . . . . . . . . . . . . . . . . .
3.5 Linear Voltage Regulator . . . . . . . . . . . . .
3.6 Biasing . . . . . . . . . . . . . . . . . . . . . . .
3.6.1 Bandgap Reference . . . . . . . . . . . .
3.6.2 Current Sources and Voltage References
3.6.3 Passive Elements . . . . . . . . . . . . .
3.7 Summary . . . . . . . . . . . . . . . . . . . . .
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4 Special Design Considerations and Tradeos
4.1 Power Consumption Analysis . . . . . . . . . . . . . .
4.2 Asymmetric Clipping . . . . . . . . . . . . . . . . . . .
4.3 Automatic Gain Control . . . . . . . . . . . . . . . . .
4.3.1 Variable Gain Amplier . . . . . . . . . . . . .
4.3.2 Peak Detector . . . . . . . . . . . . . . . . . . .
4.4 Convergence Issues . . . . . . . . . . . . . . . . . . . .
4.5 Balanced Switching Thresholds . . . . . . . . . . . . .
4.6 Voltage Reference Comparison - Bandgap vs. Self Bias
4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . .
5 Variation Analysis
5.1 Functionality Due to Input Signal Variation . . . . .
5.1.1 Input Frequency and Photodiode Capacitance
5.1.2 Realistic Photodiode Input Waveform . . . . .
5.1.3 Detailed Photodiode Model . . . . . . . . . .
5.1.4 Input Signal Intensity . . . . . . . . . . . . .
5.2 Process Variation . . . . . . . . . . . . . . . . . . . .
5.2.1 Channel Length Variation . . . . . . . . . . .
5.2.2 Threshold Voltage Variation . . . . . . . . . .
5.3 Environmental Variation . . . . . . . . . . . . . . . .
5.3.1 Power Supply Variation . . . . . . . . . . . .
5.3.2 Temperature Variation . . . . . . . . . . . . .
8
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41
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5.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Silicon Layout
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73
6.1 Implementation Overview . . . . . . . . . . . . . . . . . . . .
6.2 Cadence Technology Library . . . . . . . . . . . . . . . . . . .
6.3 Layout Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1 Folded Cascode Opamp Layout . . . . . . . . . . . . .
6.3.2 Two-Stage Opamp Layout . . . . . . . . . . . . . . . .
6.3.3 Transimpedance Amplier Layout . . . . . . . . . . . .
6.3.4 High Bandwidth Voltage Amplier Layout . . . . . . .
6.3.5 Output Stage Layout . . . . . . . . . . . . . . . . . . .
6.3.6 Linear Voltage Regulator Layout . . . . . . . . . . . .
6.3.7 Bandgap Voltage Reference Layout . . . . . . . . . . .
6.3.8 Full Layout with Biasing . . . . . . . . . . . . . . . . .
6.3.9 Design Verication, Extraction, and Layout Simulation
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7 Testing Strategy
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82
85
7.1 Functionality and Skew Testing . . . . . . . . . . . .
7.2 Circuit Layout Variants . . . . . . . . . . . . . . . .
7.2.1 Normal Receiver . . . . . . . . . . . . . . . .
7.2.2 Normal Receiver With Isolated Power Supply
7.2.3 External Power Supply . . . . . . . . . . . . .
7.2.4 External Voltage Reference . . . . . . . . . . .
7.2.5 Current Input Signal Injection . . . . . . . . .
7.2.6 Voltage Input Signal Injection . . . . . . . . .
7.2.7 Photodiode Variants . . . . . . . . . . . . . .
7.3 Overall Chip Layout Summary . . . . . . . . . . . . .
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8 Conclusion
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8.1 Evaluation of Variation Performance . . . . . . . . . . . . . . . . . .
8.2 Alternative Techniques Not Used . . . . . . . . . . . . . . . . . . . .
9
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89
8.2.1 Adaptive Biasing . . . . . . . .
8.2.2 Amplifying and Hard Limiting .
8.2.3 Resoanant Tank Ampliers . . .
8.2.4 Phase Locked Loops . . . . . .
8.3 Future Improvements . . . . . . . . . .
8.4 Summary of Contributions . . . . . . .
10
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90
90
90
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91
91
List of Figures
1-1 Typical H-Tree Clock Distribution Network [1] . . . . . . . . . . . . .
1-2 Global Optical Clock Network . . . . . . . . . . . . . . . . . . . . . .
18
18
2-1
2-2
2-3
2-4
2-5
Typical Overall Block Diagram . . . .
Eect of Light Absorbed in Substrate .
Traditional Transimpedance Amplier
Linear Power Supply Regulator . . . .
Receiver Block Diagram . . . . . . . .
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24
26
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29
30
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
Two-Stage Opamp . . . . . . . . . . . . . . . . . . . . . . . . . .
Folded Cascode Opamp . . . . . . . . . . . . . . . . . . . . . . . .
Transimpedance Amplier . . . . . . . . . . . . . . . . . . . . . .
Transimpedance Amplier Circuit . . . . . . . . . . . . . . . . . .
High Bandwidth Voltage Amplier . . . . . . . . . . . . . . . . .
Gain Block Representation for High Bandwidth Voltage Amplier
Gain Block Grouping for High Bandwidth Voltage Amplier . . .
Feedback Biasing Circuit . . . . . . . . . . . . . . . . . . . . . . .
Feedback Biasing Loop At DC . . . . . . . . . . . . . . . . . . . .
High Frequency Feedback Biasing Loop Model . . . . . . . . . . .
High Bandwidth Voltage Amplier Frequency Response . . . . . .
Output Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bandgap Temperature Independence Example . . . . . . . . . . .
Bandgap Reference . . . . . . . . . . . . . . . . . . . . . . . . . .
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32
33
35
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37
37
38
40
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46
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3-16
3-17
3-18
3-19
3-20
Bandgap Voltage Reference Circuit . . . . . . . . . . .
Parasitic PNP Bipolar Transistor . . . . . . . . . . . .
Current Source and Voltage Reference Biasing Circuits
Receiver Block Biasing . . . . . . . . . . . . . . . . . .
N-Well Resistor . . . . . . . . . . . . . . . . . . . . . .
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47
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49
4-1
4-2
4-3
4-4
4-5
4-6
4-7
Power Consumption Tree . . . . . . . . . . . . . . . . . . . .
Block Diagram With AGC . . . . . . . . . . . . . . . . . . .
Variable Gain Amplier for AGC . . . . . . . . . . . . . . .
Peak Detector Circuit . . . . . . . . . . . . . . . . . . . . .
Sample Peak Detector Waveform . . . . . . . . . . . . . . .
Balanced and Unbalanced Switching Threshold Comparison
Self Biasing Voltage Reference . . . . . . . . . . . . . . . . .
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52
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5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
100MHz Output Waveform With Input Capacitance Variation . .
Realistic Photodiode Input Waveform . . . . . . . . . . . . . . . .
Output Waveform Due To Realistic Photodiode Input Waveform .
Detailed Photodiode Model . . . . . . . . . . . . . . . . . . . . .
Output Waveform Using Detailed Photodiode Model . . . . . . .
Output Waveform Due to Input Signal Intensity Variation . . . .
Output Waveform Due To Channel Length Variation . . . . . . .
Output Waveform Due To Threshold Voltage Variation . . . . . .
Output Waveform Due To Power Supply Variation . . . . . . . .
Output Waveform Due To Temperature Variation . . . . . . . . .
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62
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6-1
6-2
6-3
6-4
6-5
6-6
Guide to Folded Cascode Opamp Layout . . . . . . . .
Folded Cascode Opamp Layout . . . . . . . . . . . . .
Guide to Two-Stage Opamp Layout . . . . . . . . . . .
Two-Stage Opamp Layout . . . . . . . . . . . . . . . .
Two-Stage Opamp (within Bandgap Reference) Layout
Guide to Transimpedance Amplier Layout . . . . . .
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78
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6-7
6-8
6-9
6-10
6-11
6-12
6-13
6-14
6-15
Transimpedance Amplier Layout . . . . . . . . .
Voltage Amplication Stage Layout . . . . . . . .
Output Stage Layout . . . . . . . . . . . . . . . .
Linear Voltage Regulator Layout . . . . . . . . .
Guide to Bandgap Reference Layout . . . . . . .
Bandgap Reference Layout . . . . . . . . . . . . .
Guide to Full Receiver Layout . . . . . . . . . . .
Full Receiver Layout . . . . . . . . . . . . . . . .
Layout Extraction Simulation Output Waveform .
13
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79
80
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81
81
82
83
84
14
List of Tables
3.1 Opamp Performance Comparison . . . . . . . . . . . . . . . . . . . .
3.2 Feedback Biasing Loop Poles . . . . . . . . . . . . . . . . . . . . . . .
3.3 Bandgap Variation Analysis . . . . . . . . . . . . . . . . . . . . . . .
34
41
48
4.1 Comparison Between Bandgap and Self Biasing References . . . . . .
60
5.1
5.2
5.3
5.4
5.5
66
67
68
69
70
Duty Cycle Changes Due to Input Signal Intensity .
Skew Due to Channel Length Variation . . . . . . .
Skew Due to Threshold Voltage Variation . . . . . .
Skew Due to Power Supply Variation . . . . . . . .
Skew Due to Temperature Variation . . . . . . . . .
15
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16
Chapter 1
Introduction
This chapter presents the motivation for on-chip optical clock distribution on a digital
chip. Previous receiver designs are analyzed and their limitations are discussed. This
thesis attempts to overcome these limitations and create a fully functional optical
clock receiver operating at 1GHz.
1.1 Motivation for On-Chip Opto-Electronic Clock
Distribution
Optics have been widely used in the telecommunications area to transmit high speed
data. This concept can be applied to sending high speed data across a small digital
chip. Miller [2] presents a historical summary of the transistion of optics from large
scale telecommunications networks to small, on-chip devices. In addition to transmitting data through on-chip optics, this idea can also be applied to on-chip clock
distribution.
Clock distribution is becoming a serious issue in modern digital CMOS chips.
Existing schemes for clock distribution such as H-trees and matched delay lines rely
on symmetry to achieve minimal skew (dierence in signal arrival times) across all
leaf nodes on the chip (Figure 1-1). The skew of a clock distribution network is
increased in the presence of process and environmental variations. The individual
17
lines themselves are especially prone to metal width variations. Clock buers are
often added to decrease the dependency of skew on individual delay lines. These
buers along with the initial clock driver circuitry at the heart of the distribution
network account for a signicant percentage of total power dissipation on a digital
chip.
Figure 1-1: Typical H-Tree Clock Distribution Network [1]
The fundamental idea of this project is to use light to distribute the clock signal
to multiple receivers across the chip (Figure 1-2). Light can be distributed to multiple
areas of the chip with very low skew. If this light can be reliably converted to an
electrical clock signal, this method could serve as a good replacement for current clock
distribution techniques.
Optical Clock Source
Waveguides
Local Electrical
Clock Network
Figure 1-2: Global Optical Clock Network
In order for this technique to be useful, a circuit must be constructed to convert
the light signal to an electrical clock with minimal skew. The thesis presents a design
18
for a circuit that receives a globally distributed optical clock signal through an onchip low skew opto-electrical interface and amplication network. Once the signal is
converted to an electrical clock signal, it can be distributed to individual leaf nodes
through a local clock distribution network.
This thesis evaluates various aspects of the receiver design. These include circuit
issues, design tradeos, and receiver susceptibility to variation eects. The receiver
is capable of handling a 1GHz clock signal. A previous design [3] has shown that the
most signicant variations sources are from the power supply ripple and transistor
channel length. The proposed design is engineered to yield consistent results in the
face of these and other process and environmental variations.
The next part of this chapter will discuss previous work related to optical clock
distribution and receivers. Chapter 2 describes the overall strategy of the receiver
topology. It also cites specic design choices to reject the eects of variation. Chapter
3 discusses the design and operation of the opto-electrical receiver. All functional
blocks in the receiver design will be covered here. Next, Chapter 4 will cover, in
detail, the more subtle design issues in the receiver design. Receiver performance with
respect to clock skew in the presence of input, environment, and process variation
will be evaluated in Chapter 5. The circuit layout and extraction simulation results
will be presented in Chapter 6. This thesis does not encompass the fabrication and
testing of the receiver. Because of this, Chapter 7 includes a comprehensive testing
strategy for the fabricated circuit. Finally, Chapter 8 will discuss overall receiver
performance and will present alternative ideas not implemented in this thesis.
1.2 Previous Receiver Designs
To this date, there has been little published research on on-chip optical receivers
for the purpose of clock distribution. There are many documented optical receiver
design techniques for sensor and telecommunications applications. These techniques
have fundamental problems in their immediate relation to the on-chip optical clock
application.
19
In Alexander's text [4], general high frequency optical receiver designs are presented. Although there are many useful ideas here, the majority of the circuits that
are reported cannot be applied to the task of on-chip optical clock distribution. These
designs use inductors, BJT's, non silicon photodetectors, and other components that
are not available on a standard CMOS digital process. The architecture of these receiver designs are discussed next. However, each has a set of limitations that prevent
the design from having useful application to optical clock distribution.
Woodward et al. [5] present a simple single ended solution based on inverters. The
transimpedance amplier is an inverter with a MOSFET used as a feedback resistor.
The voltage amplication stage uses a string of inverters.
Tanabe et al. [6] use a dierential structure whose transimpedance amplier is
a common source amplier. This design diers from the more conventional common
source followed by a source follower stage. By doing this, gain is sacriced while
making the circuit more independent to Vth variations.
Ingels et al. [7] return to the inverter based transimpedance amplier. Its post
amplier consists of a string of inverters whose biasing is set through a complex replica
biasing network. This circuit is the basis of Sam's thesis [3].
The receiver designs presented by Woodward [5], Tanabe [6], and Ingels [7] do not
consider the eect of variation. Each of their transimpedance ampliers are based on
transistors simulating resistors. This raises the tolerance issue that will be covered
in Chapter 2. The voltage amplication stages in these circuits are also highly prone
to power supply variation. Because these receivers were not designed specically for
a clock distribution application, skew induced by process or operational variation is
not a substantial concern. The designs are just concerned that the absolute speed
of the receiver is not adversely aected with variation and do not consider matching
signal arrival times. In the case of on-chip optical clock distribution, however, skew
is a fundamental concern and the receiver presented in this thesis has been designed
with variation in mind.
Two recent publications have examined the feasibility of on-chip optical waveguides rather than focusing on the receiver. Verma et al. [8] attempt to demonstrate
20
an integrated, all silicon based, optical interconnect system working in the GHz range.
However, these claims are not supported in the paper. The design is performed using
discrete components rather than integrated circuits, consumes high power, and is only
shown to work up to 100kHz. Finally, Verma et al. [8] suggests that \the receiver
circuit is not expected to cause any problems for the nal development of integrated
on-chip optical interconnects." The diculty in achieving robust, high performance
optical receivers has been demonstrated by Sam [3].
Mule et al. [9] consider issues in the design of an on-chip optical waveguide
network. The system uses a board level vertical cavity surface emitting laser (VCSEL)
to feed a clock distribution network. This network is made up of a high fanout,
single split junction that connects to an optical waveguide single-split H-tree. Mule
demonstrates less than 9ps of maximum skew for a fanout of 256 and a die area of
817mm . The receiver designed in this thesis would perform well at each node of this
single-split balanced optical distribution network.
A previous thesis at MIT, written by Shiou Lin Sam [3], seeks to demonstrate a
functional optical clock receiver. Sam's design faces a variety of problems. First, Sam
uses a TSMC 0.35 process whose analog properties are very poor at 1GHz. High
gains at 1GHz are impossible to attain and are crucial in typical receiver designs. In
addition, Sam's design attempts to use silicon PIN diodes as photodetectors. Silicon
photodetectors highly attenuate and distort the clock signal in the light to current
conversion. The goal of the second generation receiver proposed in this thesis is to
overcome many of the limitations identied by Sam's Work.
2
1.3 Summary
Optical clock distribution is a possible alternative to traditional balanced electrical
distribution networks. To prove the feasibility of an optical network, a receiver must
be designed to have low skew at high clock frequencies with minimal variation dependence. The following chapters present the design and analysis of such a design.
21
22
Chapter 2
Design Strategy to Minimize Skew
and Eects of Variation
Current optical receiver designs share similar functional blocks. However, traditional
implementation of the photodetector, transimpedance amplier, and voltage amplication stage have limitations when applied to optical clock distribution. This chapter
will present these limitations along with an overview of the total receiver topology
used in this thesis.
2.1 Generalized Topology
The optical clock signal is distributed through the chip to each receiver. The receiver
must take the optical signal and convert it into a corresponding CMOS compatible
rail to rail voltage signal. A standard receiver topology has three main functional
parts, as illustrated in Figure 2-1. First, a photodetector is used to convert light
into a current signal. Next, this current must be changed into a voltage through a
transimpedance conversion. Lastly, the voltage signal must be amplied to a rail to
rail square wave in order to be used in a standard digital system.
23
Photodetector
Transimpedance
Amplifier
Voltage
Amplifier
Optical Clock
from Waveguide
I in
Full Swing
Clock
Power Supply
Independent
Voltage Gain
High
Gain
R
Figure 2-1: Typical Overall Block Diagram
2.2 Variation vs. Low Skew
The receiver is designed to be part of a global clock distribution network. Because
this network distributes a clock signal, skew between receivers must be minimized.
Skew is the time measurement between misaligned clock signals, considered at the
output of each copy of the receiver.
One approach to minimizing skew is to accurately predict and reproduce delay
in all copies of this circuit. This approach is impossible due to random process and
environmental variations across the die. Another approach is to design the circuit to
reject most sources of variation. If this is done, skew will remain constant and can
be minimized. This is the approach taken in this thesis.
2.3 Design Implications/Challenges
The key issue that signicantly constrains the performance of the receiver is the
integration with a standard CMOS digital process. The TSMC 0.18 MOSIS logic
process is chosen for the test chip. The receiver must transform an optical clock signal
to an electrical equivalent while running side by side with other digital logic. This
imposes two key restrictions. First, the photodetector must either be made of silicon
24
or be made on a process that can be integrated or bonded to a silicon die. On the
electrical side, the maximum speed that the receiver can run at is inherently limited
by the speed of the MOSFETs. For example, a proof of concept for the receiver
was rst designed using ideal opamps. Replacing these ideal elements with realistic
opamps revealed a host of serious issues. These problems are at the beginning of a list
of challenges addressed in the receiver design. The photodetector, transimpedance
amplier, and voltage amplier will now be examined.
2.3.1 Photodetector
The photodetector serves as the interface between the optical and electrical domains.
Photodiodes are used in this application as detectors. On a basic level, a photodiode
is a PN junction that is reverse biased and then exposed to light. The reverse bias
causes an electric eld to form across the depletion region of the diode. Exposure to
light will create free electron-hole pairs in the depletion region. These mobile carriers
will be swept to the diode contacts by the electric eld. The total carrier movement
translates to an electrical current.
In the ideal case, a single photon will be enough for a single electron/hole pair
to be generated. These mobile carriers should also instantaneously exit the depletion
region and contribute to current. This implies that a square wave of light input will
result in a square wave of current output. This is not the case in reality.
Photoemitters require a minimum light wavelength to modulate an optical signal
at 1GHz. At this given wavelength, silicon has a very low absorbtion coecient, and
a silicon photodiode must be very thick to absorb all exposed light. Because of this
transparency eect, silicon's conversion of light to current is very inecient.
Ideally, all light exposed to the photodiode is absorbed in the depletion region.
However, in any actual implementation of the photodiode, the substrate sits underneath the device. Light shines onto the photodiode, but not all photons are absorbed
in the depletion region. A number of them penetrate into the substrate and create
electron-hole pairs there (Figure 2-2). Due to the absence of an electric eld in the
substrate, the carriers take a long time to migrate back up to the depletion region.
25
This results in low frequency gain where a square wave of light is converted into a
highly distorted square wave.
Light From
Waveguide
metal 1
Mobile carriers
generated in depletion
region are swept to
contacts by high
electric field
metal 1
Vdd
n+
n well
Mobile carriers
generated in substrate
take longer to reach
depletion region
Depletion
Region
p substate
(biased lower than Vdd)
Figure 2-2: Eect of Light Absorbed in Substrate
Rooman et al. [10] presented a receiver with a novel photodetector based on spatial
modulation. The photodetector consists of a row of photodiode strips. Every other
photodiode is covered with metal so that it will not be exposed to light. When light
shines on this photodetector, some photons are absorbed in the depletion regions of
the uncovered photodiodes. The rest penetrates into the substrate and creates mobile
carriers there. These slow carriers now have equal probablity of reaching a covered
photodiode as an uncovered photodiode. Therefore, the source of distortion will split
evenly between the covered and uncovered devices. Each photodiode creates a current
which is then converted to a voltage. The dierence between the voltages produced
will be an undistorted square wave because the distortion is common mode and thus
cancels out. The spatial modulation technique was not used in this thesis; instead,
our focus is on the receiver circuit.
In the design in this thesis, the test chip will contain both silicon and GaAs
photodiodes. The silicon diodes are diusion to substrate PN junctions. GaAs has a
much higher absorption coecient than silicon. These photodiodes will be fabricated
on a separate process and then later bonded to the CMOS chip. Many copies of each
type are on the test chip to account for defects and fabrication diculties.
26
2.3.2 Transimpedance Amplier
The transimpedance amplier (TIA) converts current into a proportional voltage.
Intuitively (through Ohm's law) this current to voltage relationship will be highly
dependent on a resistance. Therefore, any changes in resistance will alter the transimpedance relationship and will ultimately alter skew.
The most basic of transimpedance ampliers is a simple resistor. Input current
enters and creates a proportional voltage across the resistor. However, to use this
voltage, the non-grounded resistor node must be read. This will introduce some
degree of resistive loading and will disturb the transimpedance relationship.
Current From
Photodetector
High
Gain
To Voltage
Amplification
Stage
R
Figure 2-3: Traditional Transimpedance Amplier
The method that is most frequently used in building transimpedance ampliers
is based on negative feedback (Figure 2-3). The idea relies on an amplier with
a high negative gain and high input impedance. A feedback resistor connects the
input and output nodes. This conguration results in the following transimpedance
ARf . If the gain (A) of the amplier is much greater than 1,
relationship: VIout
A
in =
then Vout=Iin will be equal to Rf . In a MOS implementation, the amplier gain is
based on a gm Rload product. Therefore, if the transconductance is high and Rload
changes, the transimpedance relationship will be preserved.
There are several problems associated with this negative feedback transimpedance
conversion approach. The rst is that it requires a high amplier gain at signal
frequency (1GHz). Using a 0.18 process, the highest gain that can be attained is
about 10. In most cases, higher gain can be achieved by cascading multiple stages.
However, this is impossible here because each stage adds another dominant pole and
with it, 90 of negative phase. When a feedback loop is closed around this amplier,
(1+ )
27
the phase margin will be severely degraded and instability will occur.
Aside from the gain issue, the negative feedback TIA approach has a serious
problem because it is still dependent on a distinct resistance. In a CMOS process,
resistor values commonly may vary up to 20%. This will result in an unpredictable
transimpedance relationship. Also, in order to achieve a high transimpedance gain,
a very large resistor must be used. Using a eld eect transistor (FET) as a resistor
overcomes this last problem.
The receiver design in this thesis uses a transimpedance amplier that has no
feedback. It therefore does not require a single stage high gain amplier. Furthermore,
the TIA relies on a MOSFET small signal output impedance as its principle resistance.
This allows for a large transimpedance gain with less susceptibility to variation than
a passive resistor.
2.3.3 Voltage Amplication
An output stage is required in a typical receiver. This stage will, at the very least,
be a rail to rail voltage buer. More often, the stage will also need to provide voltage
gain.
Sam [3] uses a topology based on CMOS inverters. Although this method fullls
the above criteria for an output stage, it introduces large skew in the presence of
power supply variation. When Vdd changes, the switching thresholds of the inverters
also change. Sam found that a 10% variation in power supply caused 100ps of skew
over the overall amplifer.
The voltage amplication stage in this thesis is split into two parts. First, high
bandwidth cascode ampliers are used to amplify small voltage signals. The signals
are amplied to give ample noise margin in the subsequent inverter amplier stages.
To account for power supply variation, a linear voltage regulator is constructed to
x Vdd at 1.8V (Figure 2-4). This method requires a separate supply higher than Vdd
and a voltage reference.
Power supply variation skew tests are performed on the inverter with and without
power supply regulation. A skew test measures the time dierence between the output
28
Vdd High (3V)
vddref
+
−
Vddreg (1.8V)
10nF
Figure 2-4: Linear Power Supply Regulator
from a 90% Vdd amplier and a 110% Vdd amplier. A normal inverter has 15ps of
skew while one with a simple regulated power supply has 2.5ps skew. Power supply
regulation therefore provides more than an 80% reduction in skew.
1
2.4 Receiver Topology Overview
The overall receiver topology can be seen in Figure 2-5. The optical signal is converted
to a current through the backbiased photodiode. Since the photodiode is a single
element, it is grouped with the next stage. The current is changed to a small voltage
through transimpedance conversion.
From this point forward in the circuit, the output voltage from each stage is biased
at VDD =2. This ensures proper input signal biasing of the individual stages and helps
prevent skew. The method used is feedback biasing, which uses a high gain negative
feedback loop to keep a constant DC level while preserving the gain of the amplier
at 1GHz. After the transimpedance conversion, the voltage is amplied through a
high bandwidth voltage amplier with feedback biasing.
Up until this point in the circuit, linear system analysis can be used since the
voltage signals are small. Gain and bandwidth are primary concerns in the linear
stages. However, this changes when the voltage signal becomes rail to rail after
1
Amplier used in test is a single stage dierential pair.
29
passing through the inverter output stage. Now, the system becomes a digital system
where fast transition square waves are the primary goal.
O the signal path are a collection of circuits that support receiver operation.
First, a linear voltage regulator rejects power supply ripple and provides a consistent
Vdd to every other circuit in the receiver. This circuit is critical since the output of
every stage is biased at VDD =2. Next, a biasing network provides various voltage
references and current sources. The main current reference is constructed with a
bandgap reference feeding a MOSFET. Bias stability is a primary concern for maintaining low skew. The bandgap reference proved to be very independent of Vth, L,
and temperature variation.
Linear Voltage
Regulator (Vdd)
Light from
Waveguides
Transimpedance
Amplifier (TIA)
High Bandwidth
Voltage Amplifiers
Inverter
Amplifiers
To Local
Clock Distribution
Circuit
Figure 2-5: Receiver Block Diagram
2.5 Summary
The challenges of building a high speed optical clock receiver have been discussed
in this chapter. Existing architectures of the photodetector, transimpedance amplier, and voltage amplication stage have limitations that make it dicult to meet
the requirements of this application. Instead, a design overview for a new receiver
architecture is proposed. The following chapter will detail this receiver's design and
operation.
30
Chapter 3
Circuit Design and Operation
A complete design documentation is presented in this chapter. First, the two styles
of operational ampliers (opamps) are discussed. These opamps will be used in the
construction of larger functional blocks. Next, the discussion focuses on the three
blocks directly in the signal path (transimpedance amplier, high bandwidth voltage
amplication, and output stage). Finally, the linear voltage regulator and the biasing
network are described in detail.
3.1 Operation Amplier Designs
The opamps described in this section are needed as building blocks in other sections
of the receiver. Six opamps are needed in the complete receiver design. Two main
opamp topologies are chosen and each has two variants.
3.1.1 Two-Stage Opamp
The rst opamp topology chosen is the standard two-stage architecture (Figure 3-1).
This opamp consists of a current mirror loaded dierential pair followed by an actively
loaded common source amplier. The dierential pair bias current is supplied by a
current mirror to ensure high common mode rejection.
The two-stage opamp has a system function of H (s) = s ADC s with two
( 1 +1)( 2 +1)
31
Vdd
Vout
Vin-
Ccomp
Rcomp
Vin-+
Figure 3-1: Two-Stage Opamp
dominant poles. One pole is caused by the high impedance node at the output of
the dierential pair stage. The second pole is caused by the high load capacitance
at the output of the second gain stage. In the frequency domain, each of these poles
contributes 90 of negative phase. Because of this, the total phase margin at unity
gain crossover is very small. If not corrected, this will contribute to instability when
a feedback loop around the opamp is connected.
First, a Miller capacitor is inserted across the gate-drain junction. This has the
eect of signicantly lowering the dominant pole of the system through the Miller
eect while pushing the second pole up in frequecy. However, the addition of this
capacitor also brings a right half plane zero into the frequency range of interest. This
zero degrades phase margin by providing a magnitude boost while adding negative
phase. To compensate for this, a resistor (Rcomp) is added in series with the capacitor
(Ccomp) to move the right half plane zero into the left half plane.
The receiver uses three two-stage opamps. The rst two are used in the high
bandwidth amplier stages as voltage buers. After compensation, these opamps
have a gain of 20.8, bandwidth of 12.1MHz, and a phase margin of 90. This opamp
is an ideal choice for a buer because its unity feedback closed loop response is
at past 1GHz. The last two-stage opamp is used in the bandgap circuit. Its DC
characteristics are adjusted to the values relevant to the bandgap reference.
32
3.1.2 Folded Cascode Opamp
The folded cascode opamp (Figure 3-2) is chosen for use in the receiver because it
can achieve a higher gain and bandwidth than the two-stage opamp [11]. Its input
stage is a dierential stage whose current is supplied by a current mirror. The output
stage has a cascoded current mirror PMOS structure along with a biased cascode
NMOS structure. The cascode conguration on both sides gives the output node
very high output impedance. The input stage is coupled directly into the output
stage by steering current to the NMOS transistors.
Vdd
Vout
Vin+
VinVbias2
Vbias1
Figure 3-2: Folded Cascode Opamp
The system function for the folded cascode opamp is H (s) = sADC . There is only
one high impedance node in this circuit because all other nodes see 1=gm. It is located
at the output node of the opamp and is caused by the high output resistance of the
opamp and the load capacitance. The pole dominates the frequency characteristics
of the opamp. This gives the amplier a single dominant pole at the output node.
Using this feature, the folded cascode can be built to have a reasonable gain with high
bandwidth. Two of these high bandwidth opamps are used in the high bandwidth
amplier stages. Each has a limited gain of 5.86, but a bandwidth of 192MHz with
90 of phase margin. However, because of the higher order poles and zeros, the poor
unity gain closed loop response of this opamp makes it not t for a unity gain buer.
An alternative use for the single high impedance output node is to make an opamp
(
33
+1)
with very high gain and phase margin. The linear voltage regulator does not require
high bandwidth because it mainly deals with DC signals (Section 3.5). A special
folded cascode opamp is designed for this application, featuring a gain of 355, bandwidth of 21.8MHz, and phase margin of 90.
Table 3.1 compares all opamps used in the receiver in terms of gain and bandwidth.
Topology
Circuit Used In
Quantity Gain Bandwidth
Two Stage
High BW Amplier Stage
2
20.8 12.1MHz
Two Stage
Bandgap Reference
1
14.6 10.5MHz
Folded Cascode High BW Amplier Stage
2
5.86 192MHz
Folded Cascode Linear Voltage Regulator
1
355 21.8MHz
Table 3.1: Opamp Performance Comparison
3.2 Transimpedance Amplier
As discussed in Section 2.3.2, the transimpedance amplier of this receiver is not
the typical resistor feedback around a high gain amplier. Instead, the open-loop
topology of Figure 3-3 is chosen. Note that the transimpedance amplier shares the
rst cascode amplier with the high bandwidth voltage amplication stage.
Light is converted to current in the photodiode. The photodiode is reverse biased
with one end connected to Vdd and the other to a current mirror. The current mirror is
constantly biased to the on state using a PMOS device in parallel with the photodiode.
The bias current is 54uA and is purposely kept large compared to the photodiode
current so that the output impedance of the diode connected NMOS device remains
fairly constant. Therefore, the photodiode current rides on top of a larger DC current.
Current is converted through voltage as it passes through the diode connected
NMOS device. Its eects are amplied further in that the current mirror ratio is 1
to 6. This requires that the DC current be kept at a reasonable size such that the
mirrored current in the next stage is not too large. At 1GHz, the transimpedance
gain is 1:18kV=A.
The transistor level schematic of the TIA is seen in Figure 3-4.
34
Transimpedance
Input Stage
First Cascode
Amplifier Stage
Vdd
Vref1
Ibias
54uA
Iphoto
Photodiode
Feedback
Biasing
mpl2
2.28u/.18u
mpin
1u/.18u
Vref2
mnm1
1u/.18u
mnc2
3u/.18u
mnm2
6u/.18u
Figure 3-3: Transimpedance Amplier
3.3 High Bandwidth Voltage Ampliers
Once the signal is converted to voltage, its peak to peak voltage is only about 17mV.
This voltage must be amplied to the point when normal inverters can take over and
rail the signal. Two key architectures are used in this circuit.
Cascode
Two-Stage Opamp
Vdd
Vdd
Folded Cascode Opamp
Photodiode
Figure 3-4: Transimpedance Amplier Circuit
35
vref5
vref6
vref3
bf
bt
Vout
vref2
vref1
Low-Pass
Filter
Vdd
p1
+
+
Two Stage
Opamp
−
Folded
Cascode
Opamp
−
Vref
Vout
Vbias
Vin
n2
n1
Figure 3-5: High Bandwidth Voltage Amplier
3.3.1 Cascode Architecture
The actual voltage amplication is done through the cascode architecture (Figure 3-5).
MOS transistors n1 and p1 form a standard common-source voltage amplier. The
lower device, n2, exists to isolate the input node from the output node, thus killing
the eect of the Miller capacitance and extending the bandwidth of the amplier.
The output impedance of the amplier is also increased by n2, thus raising its gain.
The result is a conventional high gain, high bandwidth voltage amplier.
3.3.2 Feedback Biasing
The central strategy of this receiver design is to bias the outputs of each amplier
at VDD =2. This reduces skew by standardizing the bias points of each amplier and
preventing clipping before railing the signal at the inverter stages.
The output of the high bandwidth voltage ampliers is set to VDD =2 using a
feedback biasing technique. This technique is meant to hold a specic DC bias without
interfering with the small signal voltage amplication of the cascode stage.
To fully understand the subtleties of feedback biasing, linear analysis must be
36
-A
2
A
Vin
-A
R
1
3
out
Vout
Figure 3-6: Gain Block Representation for High Bandwidth Voltage Amplier
performed. The full high bandwidth voltage amplier (cascode stage with feedback
biasing) can be modeled with Figure 3-6. In this model the gain blocks A , A , and
A represent the transconductances of various sections of the amplier (Figure 3-7).
The output resistance block, Rout , is the parallel combination of small signal output
resistances:
1
2
3
Rout = ron jjrop
2
1
Vdd
- A2
p1
+
+
Two Stage
Opamp
−
Folded
Cascode
Opamp
−
A3
Vref
Vout
Vbias
Vin
n2
n1
- A1
Figure 3-7: Gain Block Grouping for High Bandwidth Voltage Amplier
A transfer function for each transconductance gain block must be found. First, the
small signal transconductance of the entire amplier is gmn . Because of the cascode
conguration, the dominant pole of A is across gate and source of n1.
1
1
37
A =
1
(
gmn1
a1 s+1)
A has a similar transfer function because it relates the change from the feedback
biasing loop to the output.
2
A =
2
(
gmp1
a2 s+1)
Next is the analysis of the feedback biasing loop itself (Figure 3-8). A is the
compilation of three smaller transfer functions.
3
Vdd
+
H 1(s)
+
R
Two Stage
Opamp
−
C
−
R
To next stage
H 2(s)
Folded
Cascode
Opamp
Vref
Figure 3-8: Feedback Biasing Circuit
H is the unity gain closed loop transfer function of the two-stage buer opamp
(Section 3.1.1). Since it has two stages, there are two dominant poles in the open
loop response.
1
H (s) =
1
s
1
s
( 1 +1)( 2 +1)
When the loop is closed in unity gain, a single high frequency dominant pole is
created.
H cl(s) =
1
s
1
s
( 1 + 1 +1)( 2 +1)
1
( 3 +1)
s
H is the open loop transfer function of the folded cascode opamp (Section 3.1.2).
This opamp has a single dominant pole around 200MHz.
2
H (s) =
2
38
2
s
( 4 +1)
H is the transfer function of the RC low pass lter. The small output resistance
of the two-stage opamp (rots ) does not aect the time constant here because the
resistors themselves are much larger.
3
H (s) = R
3
R
RCs
1+
rots + 1+RRCs
+
=
R
R R rots )+(R+rots )RCs
( + +
A = H cl(s)H H =
3
1
2
3
s
2
s
( 3 +1)( 4 +1)(2+
1
(2+
RCs)
RCs)
Now that all the blocks have been found, feedback analysis can proceed. The
feedback biasing circuit must do two things:
It must bias the DC output voltage at VDD =2.
It must not interfere with the high freqency voltage amplication of the cascode
amplier.
The following sections will discuss these specic tasks.
Biasing the DC Output Voltage at VDD =2
The main feature of feedback biasing is that it allows the output bias point to be
accurately set. At DC, the cascode amplier has no gain. It can therefore be thought
of as a constant current source with high output impedance. The rest of the loop
can be seen in Figure 3-9. The frequency components of all the blocks are removed
because this analysis is at DC. The forward path gain becomes the product of the
folded cascode opamp's DC gain, , and the non-linear square law component of
p1. The return feedback path gain is simply the resistor divider ratio, , because the
two-stage opamp is connected as a buer. The negative feedback forces the output
node to be twice Vref . It also forces the gate to source voltage of p1 to accomodate
this output voltage given the DC bias current set up by n1. Vref is set to 0.44V to
account for the non-innite forward loop gain. This circuit succeeds in biasing the
output voltage of the amplier at VDD =2.
2
1
2
39
-
H2
Vout
A2
v
H1
v
H3
v
v
Σ
v
+
Vref
Figure 3-9: Feedback Biasing Loop At DC
Non-Interference With High Frequency Voltage Amplication
The initial high frequency gain of the cascode amplier must be preserved. Figure
3-10 illustrates how feedback biasing aects the high frequency gain.
+
Σ
-
v
1
v
v
-A
R out
Vout
v
Vin
A2 A 3
Figure 3-10: High Frequency Feedback Biasing Loop Model
At high frequencies, the DC voltage reference is shorted to ground. The overall
transfer function from input to output is given by:
Vout
Vin
= ;A (
1
1 1+
2
A A3
)Rout = ;agmn
s
1
1 +1
1
gmp
1 2
1+ ( s+1)( s+1)( s+1)(2+RCs)
2
3
4
(ron jjrop )
2
1
Notice the dierence between this overall transfer function and that of a normal
cascode amplier. The middle term represents the eect of feedback biasing on the
gain of the amplier. In order for the gain to be unaected by feedback biasing,
the open loop gain term must be much less than unity at the frequencies of interest
(1GHz). Therefore, the feedback biasing open loop response must be designed such
that its unity gain crossover occurs before 1GHz.
The other serious design issue is loop stability. The feedback loop must be designed
to have a very stable (high phase margin) open loop response. If not, a magnitude
spike will develop in the frequency response which will give low frequency gain. If this
gain spike is high enough, the transient response will oscillate at the spike's frequency.
40
Pole Frequency Location
20MHz
1GHz
200MHz
1.5MHz
RC
Table 3.2: Feedback Biasing Loop Poles
1
2
2
2
1
1
2
2
3
4
2
Stabilizing this feedback loop is very dicult. Table 3.2 shows the frequencies of
the amplier poles. Two main requirements have to be met. First, the open loop
frequency response of the feedback biasing has to drop below unity gain before 1GHz.
Second, this unity gain crossover has to occur at a point with enough phase margin
or the amplier will oscillate. To obtain the required phase margin, dominant pole
compensation is used. The obvious choice for a dominant pole is the one used to
set the low pass lter. Since the next dominant pole in the loop is at 20MHz, the
dominant pole needs to be placed below 1.5MHz to maintain stability. However, this
pole is set by an RC time constant. It cannot be set arbitrarily low or else the capacitor
and resistor sizes will make silicon fabrication impractical. A pair of 100k
resistors
and a 2pF capacitor are used in this design to set the time constant. The result is
a feedback biasing circuit that does not interfere with the high gain of the cascode
amplier. Figure 3-11 shows the frequency response of the two high bandwidth voltage
ampliers. Note that the rst one is integrated with the transimpedance amplier
(Section 3.2).
3.4 Output Stage
After the signal is amplied to 700mV peak to peak, it is put through a series of
inverters (Figure 3-12). This method provides additional amplication to the rails,
thus turning the signal into a square wave with fast rise and fall times.
Each inverter is sized such that its switching threshold (VM ), is exactly at Vdd=2.
This helps to preserve the duty ratio of the signal. This fact also makes these inverters
41
Figure 3-11: High Bandwidth Voltage Amplier Frequency Response
Vdd
mpi1
2u/.18u
mpi2
2u/.18u
mpi3
4u/.18u
mpi4
7u/.18u
mpi5
16u/.18u
mni1
.5u/.18u
mni2
.5u/.18u
mni3
1u/.18u
mni4
2u/.18u
mni5
4u/.18u
Figure 3-12: Output Stage
very sensitive to power supply variation. That is the main justication for using the
regulated power supply.
The inverter sizes progressively increase as they get closer to the output. This
prevents excessive loading from large capacitive loads placed on the output.
The number of these inverters may vary in the actual use of the receiver, and
will depend primarily on the local clock distribution network that takes the electrical
clock signal from the receiver. The end user can customize the size and number of
inverters to a specic application.
42
3.5 Linear Voltage Regulator
Power supply regulation is needed to provide a constant Vdd supply to the receiver.
Across a digital chip, the power supply voltage can easily vary by 10% due to IR drops
and have signicant ripple from the swiching digital logic. A linear voltage regulator
topology (Figure 2-4) is chosen because of its simple concept and the availability of
a good opamp as presented in Section 3.1.2.
The performance of the voltage regulator is based on four factors. First is the
presence of a solid Vdd (1.8V) reference which must remain constant despite the presence of variation. The bandgap reference, discussed later in Section 3.6.1, provides a
very solid voltage source from which the VDD reference can be derived.
Once a good reference is obtained, the opamp is the next thing to consider. The
regulator topology relies entirely on negative feedback. A single large NMOS device
controls the ow of power. It is connected in a follower conguration with a voltage
drop between its gate and source. The negative feedback forces the source of the
transistor to the reference voltage in order to minimize the error between the two
opamp terminals. A customized folded cascode opamp (Section 3.1.2) is constructed
for this application. This opamp has a high DC gain with a low bandwidth. Figure
3-13 is a transistor level circuit diagram of the voltage regulator.
Vdd High (3V)
Vdd Reg (1.8V)
Power FET
10nF
vref5
vref6
vddref
breg
Folded Cascode Opamp
Figure 3-13: Voltage Regulator
43
Because the opamp has a low bandwidth, its gain at signal frequencies (i.e., 1GHz)
is very low. To compensate for this, a large decoupling capacitor is needed. The
capacitor creates a very low cuto low pass lter on the regulated voltage node.
However, because the value of the capacitor is so large, it is more feasible to run it
o chip instead of trying to fabricate it using silicon.
high power
The largest drawback of this circuit is that it requires a separate VDD
supply. This contributes to added overall power dissipation. The power required by
this circuit is equal to the power draw of the opamp (< 1mA) plus the product of
high and
the total current draw of the receiver and the voltage dierence between VDD
regulated .
VDD
high for proper functionality. The NMOS power
Constraints must be placed on VDD
high must be kept larger
FET is a maximum sized device so its VDsat is minimized. VDD
regulated or else the power FET will come out of saturation. V high
than VDsat plus VDD
SS
must also be kept low enough such that the maximum VDS , specied at 1.8V, is not
exceeded.
3.6 Biasing
The next step after designing the funtional blocks of the receiver is to construct a
stable biasing system. The biasing circuits must provide reliable voltage references
and current sources across all variation sources. In a sense, robustness to variation
begins with stable biasing. There are three parts to the biasing scheme: the bandgap
reference, current sources, and voltage references.
3.6.1 Bandgap Reference
In order to construct the voltage references and current sources of the biasing network, a single, stable current source is needed. Since every other voltage and current
used in the receiver is derived from this source, performance will be severely aected
if a drastic change occurs with variation. That is why the bandgap topology is chosen;
the bandgap method is known to be an eective strategy for designing against tem44
perature dependence. The circuit is based on the bandgap of silicon and is designed
to output the a constant voltage (1.24V) around a specic temperature (300 K).
The bandgap's temperature independence is based on adding two voltages with
opposite dependencies on temperature. The voltage drop across the base-emitter (PN)
junction of a bipolar transistor has a negative temperature dependence (;2mV=C ).
However, subtracting the base-emitter drops of two bipolar transistors generates a
dierence that is proportional to absolute temperature (PTAT):
Vth = kTq
VBE = Vth ln IICS
VBE = Vth ln IICS
VBE = VBE ; VBE = Vth ln IICC
1
1
2
2
1
2
1
2
After adding the two voltages, there exists a specic temperature where the two
have equal magnitude and opposite sign. At this point, their temperature dependencies cancel each other out and virtual temperature independence is achieved for a
wide range of temperatures (Figure 3-14).
Figure 3-14: Bandgap Temperature Independence Example
Figure 3-15 shows the functional implementation of the bandgap reference. The
negative feedback forces the opamp input nodes to be at equal potential, and the ratio
of R to R sets the ratio of currents through m and m . Because of the dierence
in current, the base-emitter drops of m and m will not be equal. Their dierence
1
2
1
1
2
45
2
R1
R2
+
(bgp)
Vbg
−
(bgn)
R3
m1
m2
Figure 3-15: Bandgap Reference
(PTAT) will be reected in the voltage drop across R . The PTAT voltage across R
is summed with the base-emitter drop of m and the collector currents are set such
that the desired reference voltage (1.24V) is formed at the output of the opamp.
3
3
2
VBE :75V
VR = Vbg ; VBE = :49V
R = VIR = : AV = 61k
R = R II = 6:1k
k = :: V ;: V = 8:248
R = Rk = 7:0k
1
1
49
8
3
3
2
1
2
3
1 24
0258
2
1
75
ln 10
3
The transistor level circuit diagram of the bandgap is shown in Figure 3-16. The
bipolar PNP transistors are made from parasitic diusion-well-substrate PNP transistors (Figure 3-17). Although these transistors have very poor current gains ( 3),
they are adequate for use in this circuit. The opamp has a two-stage architecture and
is customized to the appropriate DC levels (Section 3.1.1).
Besides showing independence to temperature variation, the bandgap also rejects
the other major variation sources. The voltage reference itself is not based on any
MOSFETS so channel length and threshold voltage variation will only aect the
bandgap circuit through the opamp. The same argument applies to power supply
46
Vdd
R1
6.1k
R3
61k
(bgp)
Vbg
Ccomp
Rcomp
(bgn)
R2
7.1k
m1
m2
Figure 3-16: Bandgap Voltage Reference Circuit
E
C
B
P+
N+
B
E
P+ diff
C
B
C
N+
P+
N−Well
P−Substrate
Figure 3-17: Parasitic PNP Bipolar Transistor
because the only connection to Vdd comes from the opamp. In addition, the negative
feedback of the circuit only requires the gain of the opamp to be large; it need
not be constant. Table 3.3 shows how well the bandgap performs with variation of
temperature, power supply, channel length, threshold voltage, and resistance. Note
that in the resistor test, all three resistors were changed in the same direction; the
worst case combination is not represented.
Once the bandgap reference is established, it can be connected across the gate and
source of a MOSFET to create the single current source that the rest of the biasing
scheme is based on.
47
Variation Source % Variation Change % Output Change
l
+10%
0.25%
Vth
+10%
0.27%
VDD
+10%
1.02%
Temperature
+100%
0.54%
Resistance
+10%
0.016%
Table 3.3: Bandgap Variation Analysis
Vdd
mpv2
10u/.45u
mpv1
10u/.45u
mpb1
10u/.8u
mpb2
10u/.8u
mpb5
20u/.8u
mpb6
15u/.8u
mpb7
15u/.8u
mpb3
10u/.8u
mpb4
9.15u/1.2u
b1
ref3
(.44V)
ref2
(1.56V)
b2
mnb5
20u/.8u
ref1
(.8V)
Vbandgap
mnv2
1u/1.5u
mnv1
1.45u/.9u
mibiasa
1.55u/1.1u
mnb4
2.7u/.8u
ref4
(1.1V)
mnb3
2.7u/.8u
ref5
(.9V)
breg
(200uA)
ref6
(.7V)
mnb6
3.8u/.8u
mnb7
11u/.8u
mnb1
10u/.8u
mnb2
13.3u/.8u
mnb8
20u/.8u
b1t
(100uA)
mnb9
10u/.8u
b1f
(200uA)
mnb10
20u/.8u
b2t
(100uA)
mnb11
10u/.8u
b2f
(200uA)
mnb12
20u/.8u
bg1
(100uA)
mnb13
10u/.8u
Figure 3-18: Current Source and Voltage Reference Biasing Circuits
3.6.2 Current Sources and Voltage References
The remaining current sources and voltage references (Figure 3-18) are based on the
bandgap reference. Current mirrors reect and scale the current to provide multiple
current sources. The voltage references are created by injecting the reected current
through diode connected MOSFETS. By adjusting the size of these transistors, the
VDS (equal to VGS ) can be changed. The voltage reference is then taken directly from
this.
Transimpedance
Amplifier (TIA)
Linear Voltage
Regulator (Vdd)
High Bandwidth
Voltage Amplifiers
breg
Inverter
Amplifiers
b2t
b2f
ref4
ref3
ref5
ref6
Light from
Waveguides
Bandgap
Reference
ref1
b1t
b1f
ref2
ref3
ref5
ref6
bg1
Figure 3-19: Receiver Block Biasing
48
To Local
Clock Distribution
Circuit
Figure 3-19 shows where in the receiver the various current sources and voltage
references are used. Nodes bg1, b1t, and b2t connect to 100A current sources for
two-stage opamps. Nodes breg, b2t, and b2t connect to 200A current sources for
folded cascode opamps. Finally, the various ref nodes are voltage references used in
various parts of the receiver.
3.6.3 Passive Elements
The receiver design uses many passive elements in addition to transistors. These
resistors and capacitors must be fabricated in silicon along side the active elements.
A total of ten resistors are needed in this receiver. They are made using the
resistance of n-well's (Figure 3-20). To implement the very large (100k
) resistors,
multiple smaller resistors are placed in series. Special care must be taken to ensure
that the substrate around the well resistor is kept at ground potential. This ensures
that the parasitic diode formed by the PN junction remains reverse biased.
M1
Oxide
M1
Oxide
N+
Oxide
N+
N−Well
P−Substrate
Figure 3-20: N-Well Resistor
Two types of capacitors are used in this design. Smaller capacitances (< 25fF )
are obtained with M2-M3 parallel plate capacitors. Any capacitance larger than
this is made with a MOS capacitor. Here, the capacitance non-linearly varies with
the voltage across the capacitor. In this design, the DC voltage across each MOS
capacitor is xed to a known voltage.
Several decoupling parallel plate and MOS capacitors are included in the layout
to reduce power supply noise.
49
3.7 Summary
This chapter has presented the full design of the optical clock receiver. Individual modules were considered in detail and their interaction with one another was
discussed. The next chapter will summarize the more subtle design issues of this
project.
50
Chapter 4
Special Design Considerations and
Tradeos
A variety of additional special issues have been considered during the design process.
Many of them require subtle design decisions that might otherwise be overlooked.
This chapter is dedicated to discussing certain key issues and design tradeos.
In Section 4.1, the power dissipation of the receiver is analyzed. Section 4.2, the
concerns regarding duty cycle variation due to asymmetric clipping are addressed.
An automatic gain control approach has been developed, and is described in Section
4.3. Convergence related issues are discussed in Section 4.4. The importance of
having balancing switching thresholds is emphasized in Section 4.5. Finally, Section
4.6 presents a comparison between the bandgap reference used in this receiver design
and an alternative self bias approach.
4.1 Power Consumption Analysis
The receiver consumes a total of 19.27mW of power during steady state operation.
Figure 4-1 explains the power breakdown throughout the individual components.
Power reduction is not a top priorityin this design; rather, functionality at 1GHz and
variation independence are the primary goals.
There are two key reasons that this cirucit consumes so much power. First, note
51
Full Optical Clock Receiver
19.27mW
Bandgap Reference
0.4785mW
Transimpedance Amplifier
w/ First Voltage
Amplification Stage
2.953mW
Cascode Amplifier
w/ Input Stage
0.7282mW
High Bandwidth
Voltage Amplifier
2.518mW
Output Stage
0.4955mW
Cascode Amplifier
0.2932mW
Two Stage Opamp
1.388mW
Two Stage Opamp
1.388mW
Folded Cascode Opamp
0.8368mW
Folded Cascode Opamp
0.8368mW
Linear Voltage
Regulator
8.5114mW
Biasing Network
4.3136mW
Folded Cascode Opamp
1.339mW
Power FET
7.1724mW
Figure 4-1: Power Consumption Tree
that until the output stage, this circuit is fully analog. It contains many linear
ampliers and opamps which dissipate power statically in their biasing currents. The
circuit must be mostly analog in order to obtain the transimpedance conversion and
high bandwidth voltage amplication functions.
The other major reason that this circuit consumes so much power is the linear
voltage regulator. This component gives the receiver full power supply independence
but consumes 44% of the total power. The vast majority of this power loss appears
across the power FET.
The biasing network consumes 22% of the total power. By monitoring the current
through each path of the biasing network, it can be optimized to pull less current
and dissipate less power. Also, each opamp has redundant current mirrors in their
biasing. This provides modularity but adds extra current paths and therefore more
power loss.
The receiver would consume much less power if the voltage regulator was removed.
However, power supply rejection would greatly be aected. Instead, chip area can
be traded o with power to reduce consumption. The main power loss is across the
power FET and is equal to the voltage dierence of the regulated and unregulated
supplies times the current draw of the receiver. Thus, the goal should be to reduce the
unregulated supply. The unregulated supply has been chosen to have a value of 3V.
52
It needs to be higher than the regulated voltage plus the VGS drop of the power FET
to ensure that the opamp will be able to keep the regulated voltage equal to VDDref
through negative feedback. One possible x to this problem is to provide a third
power supply line with a value in between the unregulated and regulated voltages.
This will be attached to the source of the power FET and will proportionally reduce
the power loss. Only the opamp really needs to have a high power supply. Another
possible option is to add more power FET's in parallel. This adds more current
source capability but more importantly, reduces VGS in the power FET. Therefore, the
unregulated power supply can be reduced and with it, power dissipation is reduced.
4.2 Asymmetric Clipping
One of the largest sources of skew and duty cycle variation is asymmetric clipping in
the high bandwidth voltage ampliers. The core cascode amplier architecture makes
the amplier saturate on the ground rail before it saturates on the power rail. This is
due to the amplier requiring two VDsat drops from the output node to ground. Once
clipped, nonlinearities will be introduced to the signal and will be passed through to
later stages. This will ultimately lead to skew and duty cycle variation at the receiver
output node.
There are a number of techniques that can be used to prevent asymmetric clipping.
The rst was to reduce the number of cascode amplier stages from three to two.
Once the signal is large enough to pass the inverter thresholds, additional linear
amplication is unnecessary. Next, the input signal intensity (Section 5.1.4) must be
limited to ensure duty cycle integrity. Finally, automatic gain control can be used
to equalize the signal magnitude before passing through the high bandwidth cascode
ampliers. While the ultimate decision is to not include automatic gain control in
the present receiver, a design is presented in the next section for potential future use.
53
4.3 Automatic Gain Control
Automatic gain control was considered in the receiver design. Implementation proved
to be dicult so the idea was not used in the nal receiver design.
The purpose of the automatic gain control (AGC) stage is to account for amplitude
variations. The largest source of amplitude variation comes from the photodiode;
however, this stage would also account for gain variations in the cascode stages and
prevent asymmetric clipping. Finally, any amplitude variation should be corrected
before railing the signal with the inverter ampliers.
The AGC consists of three parts: the variable gain amplier (VGA), peak detector,
and feedback biased (FBB) load (Figure 4-3). The peak detector stores the peak at
the AGC's output. The VGA uses the stored peak value to alter its gain in the input
signal. The FBB load, as explained earlier, biases the output signal around a known
voltage.
Linear Voltage
Regulator (Vdd)
Light from
Waveguides
Transimpedance
Amplifier (TIA)
Automatic Gain
Control (AGC)
High Bandwidth
Voltage Amplifiers
Inverter
Amplifiers
To Local
Clock Distribution
Circuit
Figure 4-2: Block Diagram With AGC
4.3.1 Variable Gain Amplier
The VGA (Figure 4-3) uses a feedback loop to keep the input transistor, mn1, in its
linear triode region of operation [12]. The negative feedback attempts to keep the
two inputs to the opamp, node a and node c, at the same voltage. The opamp sets
the gate voltage of mn2 (node b ) such that the VDS of mn1 is xed to the output
voltage of the peak detector.
Assuming now that mn1 is kept in its triode region, its drain current and transconductance can be expressed by:
ID = ( WL )nCox (VGS ; VTn ; VDS )VDS
2
54
Vdd
mp1
(d)
Feedback
Biasing
Vout
mn2
−
(a)
Vin
mn1
(b)
+
(c)
Peak
Detector
Figure 4-3: Variable Gain Amplier for AGC
D = ( W ) C V
gm = dVdIGS
L n ox DS
Therefore, as long as mn1 is kept in its triode region, its transconductance will
be proportional to its VDS . Since mn2 acts as a common gate amplier and has no
aect on the ID , the overall gain of the VGA is ;gm (ron jjrop ).
2
1
4.3.2 Peak Detector
The peak detector controls the gain of the AGC. An exclusively CMOS topology [13]
is chosen to avoid diode non-idealities. If the output voltage amplitude is too high,
its sampled peak signal to the VGA must lower. The opposite applies to an output
voltage amplitude that is too low. Note the inverse relationship. The output signal
is biased at a known positive DC voltage. The peak detector in Figure 4-4 records
the low peaks of this signal.
The peak detector stores information of the output signal peak on Cstore. The voltage on Cstore is buered once to prevent loading and then again to give the necessary
level shift for proper VGA operation.
Figure 4-5 shows the ideal operation of the peak detector. Assume rst that the
value stored on Cstore is higher than the lower peak of the output signal, so that the
55
Vdd
mp1
Cstore
(b)
(c)
Vin
(d)
Vpeak
(a)
mn1
Biasing
Differential Pair
Biasing
for mp1
mn2
Current Mirror
plus Capacitive Storage
Buffer 1
Buffer2
Biasing
Figure 4-4: Peak Detector Circuit
voltage at Vin is higher than the voltage at node d. Node a is at the inverting output
of the dierential pair. In this case, the dierential pair pulls node a down as low as
it can go until its current mirror saturates. Because node a is very low, the current
mirror in the next stage does not turn on. However, node a also feeds a follower
amplier which biases mp1 in the on state. This current leaks down through mn2
and the voltage on Cstore remains unchanged.
Assume now that the voltage at Vin is lower than the voltage at node d. Then
node a will be forced to a high potential, thus turning on the current mirror at mn1
and biasing mp1 o. The current that ows through mn2 will discharge Cstore to
the point where node d is equal to the low peak value. This phase is known as the
tracking mode.
After the peak is found, the peak detector remains in the hold mode in which
the voltage on Cstore remains relatively unchanged. This voltage can change through
leakage discharge or a change in the output voltage amplitude.
56
Output Stored Peak
Input Signal
1
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
|
|
|
−1
Hold
0
1
2
3
Track
4
|
Hold
5
6
7
Figure 4-5: Sample Peak Detector Waveform
4.4 Convergence Issues
During the course of this thesis, many Hspice convergence issues were encountered.
Convergence is needed to obtain valid circuit simulation results.
The models used in the receiver simulation are the TSMC 0.18 analog/mixed
signal models. These include complete modeling of parasitic components. Because of
their detail, Hspice often does not converge if the models are used at high frequencies
(1GHz). This problem was never xed; a simple move to the TSMC 0.18 digital
models was made. These models do not include the complex parasitic modeling and
converged while maintaining enough accuracy for this thesis.
The other reoccurring issue with convergence is observed when complex feedback
loops are used. Techniques such as feedback biasing cause Hspice to lose DC convergence and fail at transient simulation. After researching through the Avant! Hspice
Manual [14], methods for xing this problem were found. The rst and more ideal
way is to use initial conditions for any node that might oat on startup. The other
is to add conductance ( 0:5u0) and capacitance ( 1fF ) from every node in the
circuit to ground. This helps stabilize the circuit during transient simulation. However, this method could cause problems if the conductance and capacitance interferes
with normal circuit operation. The nal receiver design Hspice simulation uses initial
57
conditions and 1fF of capacitance at all nodes to ground.
4.5 Balanced Switching Thresholds
Careful sizing of transistors is required to ensure balanced switching thresholds. Balanced switching thresholds are crucial to the design methodology of biasing every
amplier's output at VDD =2. Figure 4-6 shows a comparison between balanced and
unbalanced swithing thresholds. The rst example has an input signal biased at 0.9V
and an amplier with a balanced threshold at 0.9V. The second has the same input
signal passing through an amplier with a switching threshold at 0.8V. The DC voltage dierence between the input signal bias and the switching threshold is amplied.
The output signal ceases to be centered at 0.9V.
Amplification of 3 With Balanced Switching Thresholds
Input
Output
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
90
100
Amplification of 3 With Unbalanced Switching Thresholds
1.5
1
0.5
0
Input
Output
0
10
20
30
40
50
60
70
80
90
100
Figure 4-6: Balanced and Unbalanced Switching Threshold Comparison
There are two crucial circuit blocks that require balanced switching thresholds.
In the high bandwidth cascode voltage ampliers, the sizing of the transistors in the
58
signal path is crucial to keeping them in saturation. This must also be done with each
inverter amplier to ensure equal switching between the PMOS and NMOS devices.
In both these cases, unbalanced switching thresholds result in duty cycle variation
and, in extreme cases, a complete loss of functionality. For these reasons, special
emphasis is put on the sizing of transistors.
4.6 Voltage Reference Comparison - Bandgap vs.
Self Bias
One of the keys to variation independence is having a solid central voltage reference
(Section 3.6). Originally, the bandgap circuit used in this thesis was seen as impractical because of the bipolar transistors needed to make it work. Instead, a self biasing
circuit (Figure 4-7) was used as the central voltage reference for the receiver.
Vdd
Vdd High (3V)
mp1
30u/.45u
reset
mp2
30u/.45u
mrb
1u/.18u
mrc
1u/.18u
Ibias
mn2
30u/.45u
mn1
30u/.45u
mibias
19.5u/.45u
3k
Figure 4-7: Self Biasing Voltage Reference
This circuit relies on current mirror PMOS devices to equalize the current in both
legs. The voltage drop across the resistor will be balanced with the gate to source
voltage of mn1. The current owing through each leg will be that voltage divided by
the resistance.
59
This circuit has two stable operating points. One is when the voltage on both
sides of the resistor is at ground and there is no drain to source voltage across mp1.
At that point, no current ows through either leg and a useful voltage cannot be
extracted. The other operating point occurs when the voltage across the resistor is
larger than the threshold voltage of mn1. That voltage can be fed into the gate of
another NMOS device to create a useful current reference. To make sure the circuit
is in this operating point, mrb and mrc are added as reset devices.
One of the largest advantages of using this circuit is its power supply independence.
If VDD changes, the voltage across the resistor will remain nearly constant because
of the high output impedance of the transistors. However, because this circuit relies
on matching a VGS with a resistance, it performs poorly when faced with threshold
voltage, channel length, and resistance variation.
Variation % Var. Change % Bandgap Change % Self Biasing Change
l
+10%
0.25%
4%
Vth
+10%
0.27%
5%
VDD
+10%
1.02%
0.2%
Temperature
+100%
0.54%
1%
Resistance
+10%
0.016%
7%
Table 4.1: Comparison Between Bandgap and Self Biasing References
Table 4.1 compares the performance of the bandgap and self biasing references
under variation. The bandgap reference is clearly far superior with respect to all these
variations except power supply deviations. This weakness of the bandgap approach
is corrected with the addition of the voltage regulator described in Section 3.6.1.
4.7 Summary
This chapter has covered the special considerations and decisions that were made in
the design of the optical clock receiver. Previous to this, Chapter 3 discussed its full
design and operation. Next, in Chapter 5, the performance of the receiver design will
be analyzed with respect to variation dependencies.
60
Chapter 5
Variation Analysis
If all process and environmental parameters were kept constant over every receiver
in the chip, skew between recovered clock signals would not exist. In reality, however, variation in these parameters creates non-zero skew. Variation analysis for the
purposes of this thesis focuses on intra (within) die variation and will not include
analysis of the waveguides and photoemitters.
The rst section will describe how functionality is aected by realistic input signal
changes. Sensitivity analysis has been performed on the receiver circuit. Next, the
eects of various process and environmental variation is observed. In each, the eects
of perturbing the variation source are compared to a nominal, variation free, output.
5.1 Functionality Due to Input Signal Variation
The nominal input signal is a 1GHz, 10A peak-to-peak square wave. The photodiode is modeled as an ideal current source in parallel with a 100fF capacitor. Tests
on input frequency, photodiode capacitance, realistic photodiode input waveform, realistic photodiode model, and input signal intensity are performed to analyze the
non-idealities of the input waveform and photodiode model to ensure functionality.
61
5.1.1 Input Frequency and Photodiode Capacitance
The rst test is to determine if the circuit will still function at lower frequencies and
larger photodiode capacitance. The circuit must function at lower frequencies in case
the test equipment itself cannot operate at 1GHz. Figure 3-11 shows that in the
100MHz band, the linear portion of the circuit actually has more gain. Therefore,
when simulated at 100MHz, the receiver circuit will not only function, but the output
waveform will have faster rise and fall times. Running the circuit at a slower clock
speed might also be a valid application to reduce power consumption across the total
chip.
Also, the full implementation of this circuit must operate with either Si or GaAs
photodiodes. The silicon photodiodes have large amounts of capacitance (1pF) associated with them. The input photodiode capacitance is a limiting factor in the speed
of the entire receiver design. This capacitance creates a large dominant pole at the
front of the receiver, resulting in an immediate reduction in bandwidth. This will
ultimately cause the receiver to not function properly at 1GHz.
Figure 5-1: 100MHz Output Waveform With Input Capacitance Variation
The circuit is successfully simulated with a 100MHz input signal and the assumed
100fF input capacitance (generally achievable with GaAs photodiodes). The circuit
also functions when the photodiode capacitance is increased to 1pF (Figure 5-1),
62
which is a typical capacitance with Si photodiodes.
5.1.2 Realistic Photodiode Input Waveform
Section 2.3.1 covered the non-idealities of a real photodiode. Because of the slow
carrier low frequency gain, the nominal square wave input current waveform will
be distorted to the waveform in Figure 5-2, using the extended equivalent model of
Section 2.3.1.
15
current (uA)
10
5
0
−5
0
0.5
1
1.5
time (ns)
2
2.5
3
Figure 5-2: Realistic Photodiode Input Waveform
Figure 5-3: Output Waveform Due To Realistic Photodiode Input Waveform
63
When simulated with the more realistic input current waveform at 1GHz, the
receiver circuit can still recover a square wave clock (Figure 5-3). The time delay
between the waveforms is due to the fact that the realistic current waveform has
diminished non-fundamental harmonics. This contributes to non-zero rise and fall
times as the input waveform is amplied.
5.1.3 Detailed Photodiode Model
The nominal receiver simulation does not include a complete photodiode. Two additional resistances are added in this section to reveal a more detailed photodiode
model (Figure 5-4). The Rdark resistor appears in parallel with the current source
and capacitor. It represents the non-zero dark current that ows when the photodiode is reverse biased in the absence of light. This is represented by a small signal
resistance of 100k
. The Rcontact resistor is represents the series resistance of the n+
and p+ highly doped regions and the resistance of the metal-silicon junctions. This
resistor is represented with a 50
series resistor.
Rcontact
Iphoto
Cdiode
Rdark
To Receiver
Figure 5-4: Detailed Photodiode Model
Figure 5-5 shows the output waveform that results from the detailed photodiode
model. No signicant dierence is present when this waveform is compared to the
nominal output waveform.
5.1.4 Input Signal Intensity
Variation is likely to exist in the intensity of the signal that the waveguide feeds to
the photodiode. This type of variation is a serious concern for this receiver circuit,
as it causes both skew and change in duty cycle (Figure 5-6). Because of the change
64
Figure 5-5: Output Waveform Using Detailed Photodiode Model
of duty cycle, an accurate measurement for skew cannot be made. Instead, Table 5.1
displays the change in duty cycle when the input waveform is changed.
Figure 5-6: Output Waveform Due to Input Signal Intensity Variation
Certain trends can be observed here. First, the receiver will fail to output a clock
signal at 1GHz if the input current is smaller than 3A peak-to-peak. If the input
current is too low, the linear ampliers will not be able to raise the peak to peak
voltage levels above the inverter noise margins (thresholds). This leads to loss of
cycles and an inconsistent output waveform.
Second, as the input current is raised, the duty cycle is diminished. There are
65
IinP ;P (uA) Duty Cycle % High
3
48%
10
48%
20
44%
30
40%
40
37%
50
34%
Table 5.1: Duty Cycle Changes Due to Input Signal Intensity
two reasons for this. The input stage bias current is only 54A. If the input current
becomes too high, it will become a signicant fraction of the input current and the
small signal approximation will be violated. This will change the operating point and
cause non-linearities. To design against this problem, the input stage bias current
would need to be increased. However, this will either lead to added power dissipation
or lower gain due to the current mirror amplication of the transimpedance amplier
(Section 2.3.2).
The second reason for the duty cycle change is the cascode architecture of the
high bandwidth voltage ampliers. The cascode architecture allows for asymmetric
clipping. This will also contribute to non-linearity before the signal is railed in the
inverter output stage.
5.2 Process Variation
In the previous section, the eects of realistic operating conditions with relation to
input signal and photodiode variation have been discussed. In this section, the two
dominant variation sources from the processing of the silicon are analyzed. Because
it is dicult to design against these variation sources, they are the dominant sources
of skew in this receiver design.
66
5.2.1 Channel Length Variation
The MOSFET channel length is typically the smallest manufactured dimension on
the chip. Because of this, it is especially prone to lithography and etch errors during
fabrication. In this test, all devices (both PMOS and NMOS) changed together.
Figure 5-7 and Table 5.2 summarize the skew generated from channel length variation.
Note that only positive percentages are tested; simulations for -5% and -10% failed
because the models are not dened below the minimum device sizes.
Figure 5-7: Output Waveform Due To Channel Length Variation
% Variation From Nominal Skew
+5%
+20ps
+10%
+80ps
Table 5.2: Skew Due to Channel Length Variation
There are two ways to design against channel length variation. The rst is to
make the performance of the circuit dependent on the ratios of channel lengths instead of their absolute values, to take advantage of beter local matching of channel
lengths (compared to global or within chip channel length variation). This is done in
areas such as current mirrors. However, this design practice has limited application.
Another approach is to scale the ( WL ) ratio of sensitive transistors. To rst order, this
67
should have no eect on normal circuit operation while reducing the sensitivity to
channel length variation. This design practice has limitations also in that increasing
the ratios adds signicant capacitance to adjacent nodes. This leads to a degraded
frequency response and in some cases, instability. Both these design methodologies
are used as much as possible in the receiver design.
5.2.2 Threshold Voltage Variation
Threshold voltage variation is caused by a variety of factors. The most dominant
cause of Vth variation is ion implantation and doping level variation. Figure 5-8 and
Table 5.3 summarize the skew generated from threshold voltage variation.
Figure 5-8: Output Waveform Due To Threshold Voltage Variation
% Variation From Nominal Skew
+5%
-20ps
+10%
-55ps
-5%
+20ps
-10%
+70ps
Table 5.3: Skew Due to Threshold Voltage Variation
Overall, this is the most dicult variation source to design against. However, there
are methods to somewhat reduce its eect on circuit performance. First, nothing in
68
the circuit should be dependent on a DC VGS drop. This eliminates the use of typical
source follower buers. Next, in common source type ampliers, the input VGS should
be kept much larger than Vth. This will ensure that the transistor is strongly inverted
and will reduce the sensitivity to threshold voltage variation. Both of these design
methodologies are used, where applicable, in the receiver design, resulting in the sekw
results shown in Table 5.3.
5.3 Environmental Variation
After the circuit is fabricated in silicon, its performance is aected by certain environmental factors, particularly power supply and temperature variations. However,
additional design techniques are used in the receiver design to minimize skew in their
presence.
5.3.1 Power Supply Variation
Across the chip, the power supply can easily vary up to 10% in either direction. Ripple
is often caused by switching logic and IR drops can cause DC shifts in VDD . Sam's
variation analysis [3] showed that power supply was the largest form of variation
for her particular design. The new proposed receiver design uses a linear voltage
regulator to control the power supply that the signal path sees (Section 3.5). Table
5.4 shows that the current receiver design performs remarkably well with respect to
VDD variation.
% Variation From Nominal Skew
+5%
-3ps
+10%
-20ps
-5%
+0.5ps
-10%
+24ps
Table 5.4: Skew Due to Power Supply Variation
69
Figure 5-9: Output Waveform Due To Power Supply Variation
5.3.2 Temperature Variation
It is dicult to predict how much temperature will vary without knowing the surrounding circuitry. Across a chip, hot spots may force certain receivers to perform
at temperatures much higher than nominal room temperature. The addition of the
bandgap reference signicantly reduces ths receiver design sensitivity to temperature.
Table 5.5 demonstrates insensitivity to temperatures up to 200% higher than ambient
temperature (25 C ).
% Temperature (C) Skew
0 (-100%)
-5ps
50 (+100%)
+18ps
75 (+200%)
+36ps
Table 5.5: Skew Due to Temperature Variation
5.4 Summary
The newly proposed receiver design performs well under realistic operating conditions
and environmental variation. It is still sensitive to process variations such as channel
70
Figure 5-10: Output Waveform Due To Temperature Variation
length and threshold voltage; however, these dependencies produce skew within the
acceptable limits. The conceptual design of the optical clock receiver has been completed. In the next chapter, the actual layout implementation of the circuit will be
discussed.
71
72
Chapter 6
Silicon Layout
This chapter presents an overview of the optical receiver circuit layout in silicon. The
process of converting the circuit from netlist to a practical layout will also be covered.
Hierarchical construction and analysis is used to reduce the overall circuit into several
managable blocks. Finally, the circuit blocks are pieced together to form the total
layout of the circuit. This layout is extracted and simulated to verify functionality.
6.1 Implementation Overview
The inital design and functionality verication is done using Hspice, as described in
Chapters 3 and 4. The layout is constructed in Cadence. Several steps need to be
taken to convert the Spice deck into a Cadence layout.
First, a Cadence schematic representation of the receiver circuit is needed. The
Spice netlist must be manually entered into a new schematic view in Cadence. This
schematic should then be simulated in the analog environment of Cadence. However,
this step was skipped and as a result, simple connectivity problems were later found.
Once the schematic is entered into Cadence, a primitive layout can be generated
from the schematic source. This layout contains the transistors and passive devices
of proper size and shows connectivity between nodes. The next step is to place and
route all elements in the circuit.
After the layout is completed, the design rule checker must be run to catch viola73
tions. Next, the layout vs. schematic checker can be run to check node connections.
This last step was skipped also due to problems with certain parameterized transistor
denitions. This will be discussed in Section 6.2.
The circuit layout is then extracted with parasitics. The Analog Artist tool is
used to generate a partial, but sucient, netlist, and this netlist is then taken and
formatted to be compatible with Hspice. A full Hspice simulation can then be run to
verify layout functionality.
6.2 Cadence Technology Library
The receiver layout complies with the TSMC 0:18 MOSIS design rules. However,
the library les obtained from MOSIS for this work were not complete and needed
to be altered. The cmosp18 and analoglib (generic analog components) were the
main libraries available. The cmosp18 library contained the symbol and simulation
information for all devices (active and passive). The layout for each device needed
to be copied from the analoglib library and linked to the symbol through a new
schematic. After this was done, the device was ready to be used in Cadence.
Two additional modications have been made to complete the cmosp18 library.
First, the layouts for capacitors and resistors have been altered. The capacitor layout
view has been changed into an M 2 ; M 3 structure to allow for stacking above active
devices and therefore, area reduction. The resistor has been changed from a poly
resistor into an N-well resistor to yield larger resistors.
In addition to altering the passive devices, the active devices have also been
changed to accommodate transistor ngering. The ngering of MOSFET's is a technique used to break large devices into smaller ones. The smaller devices are placed
side by side and share sources and drains in an attempt to reduce parasitic capacitance. However, Cadence will not support a simple placement of transistors directly
next to each other. Therefore, a special parameterized layout cell is needed to allow
transistor ngering. Fixed nger, four gate, NMOS and PMOS devices have been
constructed. Although these devices performed properly after extraction, Cadence
74
still views each as four devices. Because of this, the layout vs. schematic check fails.
Instead of xing this immediate problem, a simulation of the layout extraction was
used to verify circuit connectivity and functionality (Section 6.3.9).
The nal addition to the cmosp18 library is a parasitic bipolar PNP transistor.
No layout view exists within either library. A new layout for the PNP has been
constructed using the design rules as a guide.
6.3 Layout Hierarchy
The layout design has been performed in a hierarchical fashion. First, the small
opamp blocks are laid out. Next are the larger sub-blocks (transimpedance amplier,
high bandwidth voltage amplier, output stage, bandgap reference, and linear voltage
regulator). Finally, each sub-block is connected globally and the biasing transistors
are added.
6.3.1 Folded Cascode Opamp Layout
The folded cascode opamp (Section 3.1.2) layout uses all ngered devices. Its layout
is simple and corresponds directly to schematic placement. Figure 6-1 presents a
guide to the layout (Figure 6-2).
Biasing
Biasing
Active
Cascode
Load
Input
Differential
Pair
Folded
NMOS
Cascode
Devices
Figure 6-1: Guide to Folded Cascode Opamp Layout
75
Figure 6-2: Folded Cascode Opamp Layout
6.3.2 Two-Stage Opamp Layout
Biasing
Compensation
Resistor
Compensation
Capacitor
Biasing
Active Load
Input
Differential
Pair
Current Mirror
Load
Second
Gain
Stage
Figure 6-3: Guide to Two-Stage Opamp Layout
The two-stage opamp (Section 3.1.1) layout is again very simple and similar to
schematic placement. This circuit requires a resistor and capacitor that are constructed next to the active devices (Figure 6-3). Figure 6-4 shows the layout for the
two-stage opamp used as buers in the feedback biasing stages. Figure 6-5 presents
the layout for the opamp used in the bandgap reference.
76
Figure 6-4: Two-Stage Opamp Layout
Figure 6-5: Two-Stage Opamp (within Bandgap Reference) Layout
77
6.3.3 Transimpedance Amplier Layout
The transimpedance amplier (Section 2.3.2) layout includes the rst voltage amplication stage and consists of the input bias transistor, mirror input transistor,
cascode amplier, two-stage opamp buer, low pass lter, and folded cascode opamp
(Figure 6-6). The low pass lter requires large resistors and capacitors so the layout
area is dominated by the passive components. The resistors are laid out adjacent
to each other to promote matching. Figure 6-7 shows the complete layout for the
transimpedance amplier.
100k Ohm N−Well Resistor
100k Ohm N−Well Resistor
2nF MOS Capacitor
Two−Stage
Opamp
TIA
Folded
Cascode
Opamp
Figure 6-6: Guide to Transimpedance Amplier Layout
6.3.4 High Bandwidth Voltage Amplier Layout
As stated earlier, the transimpedance amplier contains the rst voltage amplication
stage. Therefore, the second high bandwidth voltage amplier (Section 3.3) layout,
as seen in Figure 6-8 looks almost exactly like the rst. The only dierence is the
lack of input bias and mirrored input device.
6.3.5 Output Stage Layout
The output stage (Section 3.4) is simply a chain of progressively sized inverters. The
rst four are small enough to construct with single gate devices but the last inverter
is large enough to use ngering. The layout for the output stage is seen in Figure 6-9.
78
Figure 6-7: Transimpedance Amplier Layout
6.3.6 Linear Voltage Regulator Layout
The voltage regulator (Section 3.5) layout, shown in Figure 6-10, is simply an opamp
connected to a very large power FET (top-right of the circuit). The FET is ngered
but still dominates the area of the sub-circuit. This circuit, with the appropriate
biasing transistors, is the only circuit that sees the VDDhigh power line.
6.3.7 Bandgap Voltage Reference Layout
The bandgap sub-circuit layout is the most diverse: in addition to using an opamp, it
uses three resistors and two parasitic PNP bipolar transistors. The resistors are laid
out directly next to each other to promote matching in the face of process variation.
Figure 6-11 presents a guide to the layout (Figure 6-12).
6.3.8 Full Layout with Biasing
After all the sub-circuit layouts have been constructed, the nal layout of the full
receiver is completed. Figure 6-13 describes the placement of the sub-circuits. After
79
Figure 6-8: Voltage Amplication Stage Layout
Figure 6-9: Output Stage Layout
Figure 6-10: Linear Voltage Regulator Layout
80
Two−Stage
Opamp
7.1k Resistor
6.1k Resistor
61k Resistor
PNP
PNP
Figure 6-11: Guide to Bandgap Reference Layout
Figure 6-12: Bandgap Reference Layout
81
the sub-blocks are laid out, the biasing transistors are added. Each transistor of
the biasing network is placed in a row to ensure proper matching. The biasing row
is placed in the middle of the full receiver so that certain references have a central
distribution point.
Bypass capacitors are added on the power supply and at noise sensitive nodes.
The capacitors are a combination of MOS capacitors and stacked M 1 ; M 2 ; M 3
capacitors. They ll the empty space within the layout. Note that the voltage
regulator does require an external bypass capacitor on the power supply line.
The nal receiver design, without the photodiode, is 205:5m 170:0m or
0:035105mm (Figure 6-14).
2
Transimpedance
Amplifier
High Bandwidth
Voltage Amplifier
Output
Stage
Biasing Transistors
Voltage
Regulator
Bandgap Voltage
Reference
Biasing
Figure 6-13: Guide to Full Receiver Layout
6.3.9 Design Verication, Extraction, and Layout Simulation
Once the entire circuit has been laid out, the design rule checker is run. The nal
design is DRC clean except for one pair of warnings. These warnings apply to the
N-wells of the parasitic PNP bipolar devices. Normally, the N-well is tied to the
most positive potential to ensure that the PN junctions formed with the diusion
and substrate do not forward bias. However, the bandgap circuit relies on the PN
junction between the emitter and base turning on. Therefore, this feature is desired
82
Figure 6-14: Full Receiver Layout
83
and the warning is ignored.
Next, the circuit is extracted, including the extraction of parasitic capacitances.
The Analog Artist tool of Cadence is used to generate a netlist from the extracted
view. The netlist only contains resistor nodes; it does not contain resistance values.
The resistance values, however, are present in the extracted view. In addition, the
bipolar devices are completely absent from the netlist. These problems are the result
of an incomplete set of library les. Both the resistor and PNP libraries have been
altered during this project because of their lack of cell views. To complete the netlist,
these elements are entered in manually, in order to create an accurate netlist.
The netlist is put into Hspice format and simulated. The output waveform that
results from the layout extraction simulation is seen in Figure 6-15. In this gure,
the waveform is compared to the original Hspice simulation. The overall shape of the
extracted waveform matches the Spice simulation but there are minor dierences in
duty cycle and time delay. These deviations are caused by sizing dierences between
the original simulation and the layout implementation. Because the two waveforms
of Figure 6-15 match, the layout of the optical clock receiver is veried.
Figure 6-15: Layout Extraction Simulation Output Waveform
84
Chapter 7
Testing Strategy
This chapter is devoted to the strategy for testing the optical receiver circuit. The
actual fabrication and testing of the chip has not been completed as part of this thesis,
and is expected to be accomplished in future work in parallel with on-chip optical
data receiver research [15]. The testing strategy for the optical clock receiver circuit
in this thesis is catered to demonstrating full functionality rather than measuring
actual skew.
7.1 Functionality and Skew Testing
Special issues must be considered because the circuit receives and processes a clock
signal at 1 GHz. A 1 GHz signal is very dicult to measure using conventional methods because of the parasitic capacitance in the pads and probes. Special non-intrusive
or ultra-low capacitance equipment can be used to measure the high frequency signal.
This method is very costly and not available for this project. Alternatively, a special circuit can be built to process the receiver output signal. This circuit can be as
simple as a frequency divider that outputs a frequency at a lower, more measureable,
clock speed. A more sophisticated circuit can be built that actually compares two
receiver outputs to determine skew [16]. Such a circuit can then output the skew data
at a much slower rate. When adding circuits to the outputs of the receiver, special
attention must be taken to ensure that the post-receiver circuits themselves do not
85
add skew.
To test the receiver in this thesis, a simple frequency divider should be built.
After frequency division, a progressively sized inverter chain should be added to drive
each pad. These circuits should allow the receiver to be tested with conventional
non-specialized equipment.
Skew measurement should be the main focus on the second run of the chip. This
chip should contain multiple identical copies of the circuit to test the eects of variation across the chip.
7.2 Circuit Layout Variants
On the current test chip, several replicate copies of the receiver should be used to
test functionality. Ideally, each sub-block of the receiver design should be tested
to ensure individual functionality. After that, any diculties can be attributed to
biasing or interfacing. Since this approach is not practical, an alternative strategy is
to use external stimulus to simulate various sub-blocks of the receiver. The following
variants should be used in the nal chip layout.
7.2.1 Normal Receiver
Since the voltage regulator dissipates a lot of power and requires an external bypass
capacitor, a single voltage regulator should supply the power supply line to multiple
receivers. A pair of receivers should be built to share a single voltage regulator.
7.2.2 Normal Receiver With Isolated Power Supply
One copy of the receiver should have an exclusive voltage regulator. This will reduce
loading on the regulator signicantly.
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7.2.3 External Power Supply
On one of the variants, the voltage regulator should be entirely removed and an
external 1.8V power supply line should power this receiver. This will test for voltage
regulator defects.
7.2.4 External Voltage Reference
The bandgap reference should be bypassed and an external 1.243V reference should
be added to this variant. This will test for defects in the bandgap reference.
7.2.5 Current Input Signal Injection
A single receiver should be added with its input node connected to a pad instead of a
photodiode. A pulse train of current can be used to test receiver operation. This will
test for photodiode defects. However, because of parasitic capacitance in the pad, the
speed that the receiver can be tested at will be limited.
7.2.6 Voltage Input Signal Injection
Instead of using a current pulse train to test the receiver, a voltage input can be
used in place of the photodiode. To enable this feature, however, the input biasing
transistor and the rst input mirror transistor need to be removed. The voltage
should be inserted into the gate of the rst cascode input transistor, and it should be
a small voltage pulse train with an appropriate DC bias.
7.2.7 Photodiode Variants
Both silicon and GaAs photodiodes will be used in the test chip. Multiple copies
of each photodiode-receiver set should be built to account for photodiode defects.
Depending on the space constraints on the chip, one of each photodiode could be
used for each of the above variants.
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7.3 Overall Chip Layout Summary
As discussed in Section 5.1.1, the circuit should also operate at a clock speed of
100MHz. Therefore, in addition to testing at 1GHz, a 100MHz signal may also be
used to verify functionality of the receiver.
The nal chip should include as many variants as the chip area permits. Each
variant should have a frequency divider and inverter buer pad driver. If there are
more variants than can be supported with pads, an analog multiplexing scheme can
be used before the pad drivers. This testing strategy will be capable of demonstrating
functionality of the receiver in the fabricated chip.
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Chapter 8
Conclusion
This thesis has presented a design for a fully functional optical clock receiver operating
at 1GHz. A layout has been constructed in Cadence and its extraction has been
successfully simulated with Hspice. The result is a circuit that converts an optical
signal into a rail to rail voltage clock signal. The receiver awaits fabrication.
8.1 Evaluation of Variation Performance
Sensitivity analysis of receiver variation dependencies reveals that process variations
including threshold voltage and channel length have the greatest impact on skew. The
receiver performs remarkably well through environmental variations in power supply
voltage and temperature. Performance is not aected signicantly when non-idealities
in the photodiode and input signal are added to the model.
8.2 Alternative Techniques Not Used
Several ideas were generated during this thesis but were not included because of implementation problems or time constraints. These ideas present alternative approaches
that may be used in future designs.
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8.2.1 Adaptive Biasing
This technique uses a oating bias for an NMOS input single stage analog amplier.
The bias tracks the power supply so that the VGS of the load remains constant.
Ideally, a voltage source would connect the power supply to the load transistor's
gate. Instead, a diode with a DC path to ground can be used as a voltage source.
By keeping the load transistor's VGS constant, the gain of the amplier will become
less sensitive to power supply variation. This technique can be used in the voltage
amplication stage instead of using feedback biasing (Section 3.3.2).
8.2.2 Amplifying and Hard Limiting
Another method that was considered for reducing skew was to use a stage with tremendous gain to amplify the small voltage signal o of the transimpedance amplier. That
signal would then be hard limited at the rail voltage. If the input signal were centered
around a constant DC voltage, skew would reduce with increasing gain. As long as
the gain is large, the actual magnitude of the gain is not of concern.
8.2.3 Resoanant Tank Ampliers
Many existing discrete optical ampliers use resonant tanks [4]. This concept can be
applied to a single chip design using the spiral coil inductors found on newer processes.
Resonant tanks allow an extension in a normal linear amplier's bandwidth. This
provides higher gain at a higher frequency. However, it is non-trivial to use these
ampliers within a feedback loop as the inductance causes many adverse phase eects.
8.2.4 Phase Locked Loops
One of the largest challenges for this design and future optical clock receivers is the
high frequency of the signal. As demands for faster and faster clock speed increase,
the traditional strategies will fail to provide useful designs. One technique that can
be used is to optically distribute a slower multiple of the high speed clock, convert
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the signal to a rail to rail voltage, and then use a phase lock loop (PLL) to frequency
multiply the signal to the desired frequency. In this case, the skew of the receiver will
be multiplied and the PLL itself may add skew. However, the bandwidth demands
on the receiver will be signicantly lower and low skew architectures may be used.
8.3 Future Improvements
Although this thesis presents a fully functional design, several aspects may be pursued
to build on this work.
The receiver was designed using a 0:18 process. A move to a smaller process
would increase the speed of operation for the receiver by allowing higher bandwidth
ampliers.
This design was focused on achieving functionality at 1 GHz. Therefore, it may
easily be optimized for power consumption and area. Additional work may also be
done to decrease its sensitivity to process variation.
Finally, the frequency of the optical distribution network will not be limited by
the receiver design; rather it will rst be limited by the photodiode. One option is to
use special layout techniques such as ngering or spatial modulation [10]. However,
these techniques will eventually be limited. Instead, integration of CMOS circuits
with alternative materials to silicon need to be investigated in order to achieve a fast
photodiode design.
8.4 Summary of Contributions
The fundamental goal of this thesis research has been to explore a robust, high performance, standard CMOS circuit design for potential use in on-chip optical clock
distribution. The key challenges are high speed and low skew. Previous work by
Sam [3] indicated that process and operating environment variations can induce large
skew in a baseline optical receiver design. In this work, we have contributed a new
design that features a balanced DC biased signal path using the feedback biasing
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technique. The design also includes power supply regulation and a variation independent bandgap voltage reference. Given integrated high performance photodiodes
(requiring SiGe or GaAs), the proposed circuit is expected to achieve robust and low
skew operation at 1GHz. Future fabrication and testing of the circuit will evaluate
this performance. Additional investigation of methods to further reduce the eects
of process variation induced skew is also needed to achieve even higher optical clock
receiver frequencies.
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