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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
The Path to the Software-Defined Radio Receiver
Asad A. Abidi, Fellow, IEEE
Abstract—After being the subject of speculation for many years,
a software-defined radio receiver concept has emerged that is suitable for mobile handsets. A key step forward is the realization that
in mobile handsets, it is enough to receive one channel with any
bandwidth, situated in any band. Thus, the front-end can be tuned
electronically. Taking a cue from a digital front-end, the receiver’s
flexible analog baseband samples the channel of interest at zero IF,
and is followed by clock-programmable downsampling with embedded filtering. This gives a tunable selectivity that exceeds that
of an RF prefilter, and a conversion rate that is low enough for
A/D conversion at only milliwatts. The front-end consists of a wideband low noise amplifier and a mixer tunable by a wideband LO. A
90-nm CMOS prototype tunes 200 kHz to 20-MHz-wide channels
located anywhere from 800 MHz to 6 GHz.
Index Terms—Analog decimator, analog FIR filter, anti-aliasing,
bandpass signal processing, boxcar integrator, cognitive radio,
decimation, digital AGC, direct conversion receiver, multi-mode
receiver, multi-rate signal processing, receiver dynamic range,
sampling, Software Defined Radio (SDR), switched capacitor
circuit, wideband receiver, wideband sampling, wide tuning local
oscillator, zero IF.
I. INTRODUCTION
T
HE PRESENT way of adding new bands, modes and services to mobile wireless handsets does not scale. Each
new mode requires its own radio and baseband chipset, which
is stuffed into handsets using ingenious packaging so that the
physical volume of every generation either remains constant,
or even shrinks. The rate at which new services are introduced
will soon outstrip the rate of miniaturization in packaging. What
is needed is a flexible, universal radio platform for receive and
transmit, which can be programmed to steer to any band, tune
to a channel of any bandwidth, and receive any modulation—all
within reasonable constraints. It is time to consider a softwaredefined radio (SDR) seriously.
Practical SDR fit for handheld operation has so far remained
elusive. Indeed, weighed down by historical baggage, in the
RF/analog circuit community the concept had become an object
of derision. As first envisaged by Mitola [1], all RF and baseband receive signal processing is digital, enabled by an A/D converter (ADC) at the antenna (Fig. 1). It is soon apparent that the
ADC in the SDR receiver (SDR RX) must fulfill extraordinary
specifications. For example, to digitize the frequency band from
800 MHz to 5.5 GHz, where all of today’s cellular and WLAN
channels lie, will require a 12 bit, 11 GS/s ADC. Not only is
this ADC impossible today, it will remain so in the foreseeable
future because ADC dynamic range and conversion are known
to progress at a rate much slower than Moore’s law [2]. Even
Manuscript received November 12, 2006; revised January 29, 2007.
The author is with the Electrical Engineering Department, University of California, Los Angeles, CA 90095-1594 USA (e-mail: abidi@icsl.ucla.edu).
Digital Object Identifier 10.1109/JSSC.2007.894307
Fig. 1. Software-defined radio, as envisioned by Mitola [1]. This would be the
ultimately flexible device for wireless communication.
if we knew how to build an ADC with these specifications, its
power dissipation might be hundreds of watts. To find a way out
of this impasse, we must question Mitola’s paradigm.
The flexibility and programmability that digital signal processing (DSP) brings to the radio front-end and baseband,
Mitola believes, is essential for it to adapt to any modulation,
channel bandwidth, or carrier frequency. What is not evident
is that Mitola’s SDR receiver is capable of much more. With a
sufficiently large number of digital downconverters operating
in parallel, a single SDR RX can receive, concurrently, every
channel that the ADC digitizes. To do so, all it needs is a
powerful DSP and enough memory, both of which will improve
at a rate that tracks Moore’s law. The military might be interested in massively concurrent reception, but the typical mobile
civilian is content to receive one channel at a time, sometimes
two, while three may be the upper limit—for example, as an
incoming cellular call is relayed to a headset by Bluetooth, the
user browses the web on the handset or, in the background,
downloads a large file via WLAN.
Let us set our sights, then, on this modest goal: that it is sufficient for a software-defined receiver to receive any one channel,
but at an arbitrary carrier frequency up to, say, 6 GHz, with
any modulation. This receiver should be less power hungry than
Mitola’s, indeed it may even be realizable in current IC technology. One flexible receiver can even receive multiple independent channels, if they transmit in non-overlapped time slots.
Otherwise each concurrent channel will need its own receiver,
with possibly some shared circuits across the array. In the sense
that multiple receivers will be built on a common platform, the
SDR is a step forward compared to traditional circuits that are
individually customized.
The subject of this paper is how to construct this flexible
receiver. We survey the steps that have been taken in recent
the years towards this direction—some very hesitantly—culminating in the recent realization of a software-defined RF receiver
front-end. But we do not cover the digital front-end which follows the ADC, because others do it better [3]; nor do we touch
on the software-defined baseband—both, incidentally, essential
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(a)
(b)
Fig. 2. (a) HF receiver [4] block diagram, styled after Mitola. With powerful enough DSP, it can receive all HF channels concurrently. (b) Details of the HF receiver,
in particular of the digital downconverter which defines the digital front-end. The digital downconverter consists of the complex mixer and number-controlled
oscillator (NCO). The cascaded integrator comb (CIC) filter downsamples the wanted channel at zero IF to its symbol rate, with filtering interleaved. The number
of stages and taps in the digital front-end are programmable.
for a working receiver. Ultimately the receiver itself is only half
of a radio communication device, which is not complete without
an efficient software-defined transmitter. At this point the SDR
TX is still in the research phase, and there is so little similarity
between the two that the TX warrants a detailed description of
its own in a future publication.
II. PROTO-SDR RECEIVERS AND METHODS
A. HF SDR Receiver, Mitola Style
The UK DERA has developed a prototype SDR receiver [4]
for the HF band (3–30 MHz) used by the military in long-distance communication. This is the only receiver that we know of
Mitola’s type (Fig. 2(a)). A discussion of its strengths and limitations will help to put later developments into perspective.
The 30 MHz low-pass filter following the antenna suppresses
signals that are out of the HF band. This filter’s usual role is to
limit the total dynamic range incident on the receiver’s frontend, but here it is also an anti-aliasing filter for the waveform
sampling that takes place immediately afterwards. A digitally
controlled attenuator aligns the levels of the amplified input
spectrum with the available dynamic range of a 12 bit, 75 MHz
A/D converter, which then digitizes the entire HF band.1 A powerful DSP can receive any number of channels concurrently. It
is instructive to follow the signal processing flow through the
digital front-end, not only for readers from the analog circuit
community, but because it has inspired the RF/analog front-end
of our SDR receiver.
DSP channelizers [5] operate on the complex analytic
signal [6] representing information in the desired channel.
The channelizer Fig. 2(b) consists of a complex (quadrature)
number-controlled digital oscillator tuned to the channel of
interest, driving a complex digital mixer to produce a stream
noise that
of output samples. Problems such as offset or
plague zero IF signal processing in analog simply do not exist
in the digital domain.
The channelizer’s output samples are at the same high rate as
the ADC. They represent the desired (narrow) channel at zero
IF, but also unwanted channels that populate the rest of the HF
band. Assume that the symbol rate of the wanted narrow channel
is some small rational fraction of the ADC sample rate. Equalization and demodulation of the wanted channel most naturally
1This ADC was state-of-the-art for the time, developed for IF conversion with
high spur-free dynamic range (SFDR) in wireless basestations. Wireless basestations always use SDRs (in a more restricted sense than Mitola’s) to receive
and transmit all channels in the band simultaneously. Radio power dissipation
is, however, not of primary concern in basestations.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
Fig. 3. Proto-SDR receiver from Toshiba [8] which uses front-end downconversion to decouple sample rate from carrier frequency. Flexibility of the digital
front-end enables receiver to tune individual PCS or DCS channels.
take place at this symbol rate. Therefore, the main task of the
digital front-end is to decimate the sample rate by this large
non-integer factor, and suppress the unwanted channels so that
the signal of interest is captured with the shortest wordlength
[3], [7] to lower the complexity of later computation.
After decimation, portions of the wideband input spectrum
will alias into the now shrunken Nyquist band. The comb filter is
commonly used to protect a narrow frequency band surrounding
DC from aliasing [6]. This low-pass filter’s characteristic is
function up to
defined by a discrete approximation to a
the (wide) input Nyquist rate, with nulls at the (lower) output
Nyquist rate and its multiples. The filter stopband around the
nulls [7] must be wide enough to guard against corruption of
the wanted signal’s spectral tails by aliased spectrum from elsewhere. Unwanted spectrum in the filter sidelobes between nulls
will alias into the main lobe, but away from DC.
The input sample stream is downsampled in a sequence of
stages, and then interpolated to realize conversion by a fractional sample rate. Some appropriate amount of filtering is usually merged into each stage.
This HF software-defined receiver prototype performs almost
as well as a conventional analog tuned triple-conversion superheterodyne. Its main advantage is greater programmability, and
the relative ease with which any number of DSP channelizers
can be added to receive greater numbers of channels concurrently. Its main limitation stems from the sample rate and dynamic range of practical ADCs. If the highest receive frequency
is limited to half the sample rate, then today’s state-of-the-art
ADCs limit use of the SDR to no higher than the UHF band
(30–300 MHz). Yet most of the interesting wireless bands use
carrier frequencies well above UHF. This limitation prompts us
to look farther afield.
B. Role of Tuning and Downconversion
To break the link between carrier frequency and ADC sample
rate, the band of interest can be first downconverted to within the
ADC’s Nyquist band. In choosing the LO frequency for downconversion we sacrifice some of Mitola’s flexibility, but this,
it turns out, is a small price to pay for the gains. Although by
convention we associate the Nyquist band with what is, more
precisely, the (low-pass) first Nyquist band, equally well it can
be a higher Nyquist band that the ADC undersamples. In either
case, the spectrum of interest should be limited to less than the
Nyquist bandwidth; otherwise aliasing will cause part of the
spectrum to fold over.
The obligatory RF prefilter at the antenna is an obvious way
to bandlimit the receiver. Toshiba uses RF prefilters for antialiasing to realize a mainly digital, flexible receiver for PDC and
DCS (Fig. 3) [8]. Switch selectable RF filters at 1.5 and 1.9 GHz
pass 27-MHz-wide bands which are digitized.
The preselected bands capture all PCS or DCS channels.
Quadrature (complex) analog mixers with fixed LO frequency
downconvert the entire band to DC. A complex ADC (two
12 bit, 64 MHz ADCs, one in each of the two quadrature
branches) digitizes the entire band, and a number-controlled
complex digital oscillator translates the channel of interest to
DC. Decimation and channelization follow in DSP. Although
the fullband digitization will consume more power than in a
single-channel ADC, the resulting flexibility justifies it.
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In this example the sampler substitutes for the customary
mixer, but with the property that a single sampling action produces two different incommensurate frequency translations. For
this to work, the RF filter after the LNA must block all other
bands as well as wideband noise. The fixed preselect filters are
necessary, but once again they limit the receiver’s flexibility.
D. Analog Decimation
Fig. 4. A use of impulse sampling to effect two unrelated frequency translations
at once. This enables the concurrent reception of GPS and GLONASS [10].
Corresponding points on the triangles identify portions of the input frequency
spectrum that will coincide after aliasing.
To overcome the limited image rejection of the complex
analog downconverter, the 27-MHz-wide band is translated to
one side of DC so that the stopband of the RF filter attenuates
images that will now lie on the other side of DC. With these
measures, the image is actually suppressed by 70 dB.
This receiver is one step in the right direction, but as we will
see, there is farther to go: we must find a way to overcome the
constraints imposed by fixed prefilters. First let us take a small
detour to explore subsampling and its possible use in concurrent
reception.
C. Subsampling or Undersampling
The bandpass sampling theorem says that a conventional
ADC can, in principle, digitize a signal with an information
band situated compactly within any integer translation in
frequency of the first Nyquist band [6]. This process, called
undersampling or sampling translation, exploits the translation
of a compact spectrum situated within any one Nyquist band by
convolution with an infinite train of impulses separated on the
to every Nyquist band; [9] gives another
frequency axis by
possible use of this effect. Owing to finite aperture time, that is,
the non-zero transition time from on to off, practical samplers
are inefficient in realizing large translations.
Now consider two bandlimited spectra, each on carrier frequencies located within different multiples of a hypothetical
Nyquist band that is wider than the sum of the two bandwidths.
After undersampling at the Nyquist rate, both information bands
will translate into the first and higher Nyquist bands; what is
more, with the right sample rate they will situate side-by-side
with no spectral overlap. A low-pass ADC can now digitize both
bands, and after DSP channelization the two signals can be received concurrently.
This idea underlies the front-end of a positioning receiver that
takes concurrent fixes from GPS (1575 MHz) and GLONASS
(1602 MHz) satellites (Fig. 4) [10]. Two prefilters after the
LNA select these bands but attenuate all out-of-band signals
and wideband LNA noise that would otherwise, after sampling,
translate and accumulate in the first Nyquist band. A simple
calculation shows that sampling at 24.2 MHz translates the two
bands to the range DC to 12 MHz and locates them side-by-side.
In most cases the passband of available RF filters is far wider
than the wanted channel’s bandwidth (Fig. 5(a)). If this filter
also anti-aliases, the wanted channel will be sampled at a much
higher rate than minimum. A/D conversion at a surplus rate
wastes precious power, especially when the later channelizer
suppresses much of the digitized spectrum. Power dissipated by
a receiver ADC usually falls off sharply when sample rate is
lowered, because the dynamic range also goes down. This suggests that the samples should first be decimated to the lowest
reasonable rate that captures what is wanted, and then digitized.
Much like DSP-based decimation, analog downsampling narrows in on the desired band while protecting it from aliasing.
Decimation can also be merged with frequency translation by
choosing an initial (high) sample rate, some multiple of which
is centered on the band of interest. This translates the band to
DC or to an IF, and downsampling can follow in a discretetime (D-T) analog decimation filter. A 2.4 GHz CMOS receiver
based on this principle has been published [11]. A cascade of
decimation stages also lowers the IF by the decimation factor, a
property that has been used in another early receiver [12]; obviously this property is of no use if the signal of interest is already
at zero IF.
How does an analog decimation filter work? The simplest
realization is to load successive samples of the discrete-time
waveform into
capacitors, and then sum their charges
(Fig. 5(b)) [13]. This forms an -tap FIR filter with equal tap
with nulls at
weights whose transfer function resembles a
all integer multiples of the decimated-by- (lower) sample rate
(Fig. 5(c)). The nulls protect wanted spectrum at and near DC
from suffering aliasing distortion, as well as wideband noise
from accumulating in the input Nyquist band.
E. Sampling With Built-In Anti-Aliasing
So far all the sampling schemes we have described need an
anti-aliasing prefilter somewhere; it may be the RF prefilter, or
it may be another filter downstream. This fixed filter restricts
the receiver from tuning to arbitrary carrier frequencies, and
from receiving channels of widely different bandwidths. Continuous-time analog filters are tunable by limited amounts, but
the bandwidth of today’s wireless channels can span 100:1. For
flexibility we must find a way to eliminate a standalone anti-alias
filter.
Classic impulse sampling, which has become synonymous
with “sampling”, is inherently wideband. This is why it can
be used for frequency translation. However, impulse sampling
captures, with equal fidelity, the narrow wanted spectrum and
unlimited spectrum that is unwanted. This is why it needs an
anti-aliasing prefilter.
Is there a way, then, to sample wireless channels with built-in
anti-aliasing that is good enough to protect, say, one narrow-
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
Fig. 5. (a) The available anti-alias filter (here an RF filter) may force a narrowband channel to be sampled at an unrealistically high intial rate. To save power in
later hardware, the analog samples should be decimated. (b) A switched capacitor decimator, or downsampler, with built-in comb filter [13]. (c) Illustrating aliasing
associated with downsampling, and how the comb decimation filter protects a narrowband around DC from aliasing.
Fig. 6. One way to sample a narrowband channel with built-in anti-aliasing
[14] after it is downconverted to zero IF. The waveshaping built into mixing,
followed by integration, realizes a programmable filter. WFG is a weight function generator; MX is a mixer.
band channel? In some early work on software-defined receivers
[14], [15], the Poberezhskiys ask this very question. They propose to construct a programmable filter using the mixer as part
of a sampler and weighted integrator (Fig. 6). The LO waveform
is a discrete approximation to the desired convolution kernel.
The output is a stream of anti-aliased, filtered samples. However, the many functions merged into a mixer soon become unwieldy for a practical circuit realization.
Yuan [16] gives a simpler answer to the same question: a sampler using what is known to physicists as the boxcar integrator.2
This is a special case of the Poberezhskiy proposal. It entails,
first, a translation of the input spectrum, assumed to be of unlimited extent, so that the wanted channel is at zero IF. This
2Physicists detect single events with the boxcar integrator, whereas we look
to it to sample bandpass continuous-time waveforms. The boxcar integrating
sampler has also been published in the analog circuits literature, but not as a
solution to our problem [30].
Fig. 7. (a) A simpler method to sample a narrowband channel at zero IF, based
on an integrate-and-dump or windowed integration [16]. Filtering can follow
later, often embedded with decimation. (b) The transfer function of this sampler
showing protection from aliasing at DC.
is followed by integrating the composite waveform over a time
window of width
(Fig. 7). The result of a windowed integration comprises an output sample. After readout the integrator is
later it is ready with the next sample.
reset, or dumped, and
This process can continue without interruption by, for instance,
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Fig. 8. IF receiver based on windowed integration sampling [18]. To simplify clock generation, the integration window is formed by dividing down some number
of cycles of the mixer LO. We point out that this is non-optimal. The IF carrier frequency sets the mixer LO, but protection of the wanted channel at zero IF
from aliasing by unwanted channels should set the integration window.
N
time-interleaving two identical circuits that alternate between
integration and readout/reset.
This windowed integration sampler takes continuous-time
. It
input and produces D-T analog samples at rate
is a linear, periodically switched circuit. Its transfer function on
the continuous input frequency scale is
(1)
This defines a low-pass filter with a main lobe, and a nonmonotonic transfer function consisting of a series of sidelobes
that decay at 20 dB/decade, with zeros at
The operation filters the continuous-time input before sampling, with
full anti-aliasing at DC. This anti-aliasing extends to wideband
input noise; that is, noise at the output of the preceding wideband stages is also nulled at aliasing frequencies, and does not
accumulate at DC [17]. Windowed integration, we can say, is
well suited to sampling a narrow channel at DC immersed in an
infinite band of unwanted signals.
Karvonen et al. [18] report an IF receiver that uses this
of
sampler (Fig. 8). The input IF sets the frequency
mixer switching, and a simple division determines the output
, where
is programmable. This circuit
sample rate
merges mixing to zero IF with windowed integrator sampling. It
consists of a transconductance amplifier with IF input, tri-level
switches that commutate the transconductor output current, and
an opamp-based current integrator whose output is read and
cycles of commutation. Mixing and intereset after every
gration together can be interpreted as “RF (or IF) sampling”,
particularly when the mixer is built with passive FET switches
that can also be thought of as sampling switches. However,
we caution against going too far down this line of thinking,
because mixing is determined by the carrier frequency, while,
as we will show, sampling rate is set by the wanted information
bandwidth and strength of unwanted channels.
Indeed, it is for the last reason that this receiver is unable to
exploit the possibilities latent in integrate-and-dump sampling.
filters’ sideIn most cases the 20 dB/decade rolloff of the
lobes is not good enough to suppress strong adjacent channels.
Therefore, the receiver must rely on a fixed RF preselect filter,
function alone
which immediately limits tunability. The
is not selective enough to displace the preselect filter; we must
continue the search for a powerful but tunable filter to replace it.
F. Sample Rate, Downsampling, and Filtering
When the wanted channel’s bandwidth is much less than
the sample rate, the
filter can protect it from aliasing.
It strongly attenuates unwanted signals occupying an equal
bandwidth at each null. Unwanted channels between nulls
lie in the filter sidelobes, but after sampling these will alias
into the first half of the main lobe away from DC. Aliasing
from all sidelobes accumulates in the main lobe [Fig. 7(b)].
As long as this accumulation—after any analog filtering that
follows—does not overload the ADC, it will be eliminated by
a digital filter in DSP.
at the th filter null as
We define the stopband loss
the minimum attenuation relative to DC across the bandwidth
surrounding
. For the
function, this is
(2)
We use this relation to find the baseline initial sample rate
if no other filter were present. Suppose the desired channel occupies the bandwidth . First we must construct a specification
on stopband loss. We calculate the relative energy of adjacent
channels in the same band and in nearby bands picked up in a
window of width that moves from DC to arbitrarily large frequencies. Then, assuming that this window can alias to DC as a
co-channel interferer, we calculate by how much it must be attenuated at every frequency if the wanted channel is to reach the
target SNR. From (2), the lowest sample rate is found to satisfy
the specification on stopband loss at the first few nulls; usually
this sample rate will give more than enough attenuation at the
higher order nulls.
Depending on the unwanted signal profile, this initial sample
rate may be very high, reaching into the GHz. A/D conversion
at this rate will consume disproportionate power, or might even
be impossible. To alleviate this situation, we might add more
filtering, or downsample the output. Both, as we will show, are
necessary; both are employed.
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
Fig. 9. Bluetooth receiver using windowed integration at carrier frequency, followed by decimation stages [19]. This is not yet a software-defined receiver.
We learn from multi-rate digital signal processing that downsampling by a certain composite integer is most efficiently realized with a cascade of stages, each stage downsampling by
reasonable factors of that integer and interleaved with anti-alias
filtering [7]. In our use, a not widely appreciated outcome is that
the embedded filtering cumulatively across a few stages suppresses adjacent channels by huge amounts. This will turn out
to be the most important filtering action in suppressing all unwanted channels.
Just as in DSP implementations, a compact analog comb
filter protects a narrow band at DC from aliasing that results
from decimation. A passive switched capacitor circuit realizes
decimation and downsampling simultaneously. Samples of
the incoming analog discrete-time waveform are distributed to
an array of either equal or weighted capacitors—the relative
weights will determine the taps of an equivalent FIR filter—and
after input samples are loaded, all capacitors are shorted
st discharged capacitor.
to share their charge with an
This corresponds to downsampling by , with embedded FIR
anti-aliasing.
If we can tolerate the signal loss associated with each
stage of passive charge redistribution, more than one stage
of downsampling and filtering are cascaded very simply as
pure charge-transfer circuits with no inter-stage buffers. The
st capacitor referred to above could itself be one of
equal, or weighted, capacitors in an array, which downwith built-in anti-aliasing. The cascaded filtering
sample by
progressively deepens the stopband, while all the passbands
coincide at DC. The filter passband narrows along the cascade.
This, then, is the filtering that will enable the sampling
function to finally displace the RF preselect filter.
Fig. 10. Range of variable gain in the receiver required to capture a GSM input,
from the point of view of a delta-sigma ADC with 14 bit resolution. This A/Dcentric approach seeks to lighten the burden on analog circuits, and push as
much as possible to DSP.
In the Bluetooth receiver (Fig. 9), the stage following the
LNA merges downconversion, integration and decimation filtering in the paradigm of “RF sampling”. The initial sample
is equal to the wanted channel’s carrier frequency in
rate
the 2.4 GHz band. This positions the first aliasing channel at
4.8 GHz, well in the RF prefilter’s stopband. Decimation by 8
through a
filter similar to [11] and [13] follows, and a capacitor continuously connected to the mixer transconductance
filter
realizes a D-T pole. Then follow a first-order D-T
filter that decthat decimates by 4 and a third-order D-T
imates by 2 . Finally the output discrete-time waveform is digitized.
At the final output rate of 37.5 MHz, some other channel
in the receiver’s 80-MHz-wide passband could alias on to the
wanted channel—but by this point the cumulative filtering will
have suppressed it to a very low level. We note also that as the
first LO tunes to different channels, the conversion to symbol
rate will need different non-integer interpolations, but this is
readily managed in today’s DSP.
G. RF Sampling: The Texas Instruments Receivers
III. UCLA SDR RECEIVE ARCHITECTURE
The Bluetooth [19] and GSM receivers [20] from Texas
Instruments use integrate-and-dump sampling, followed by
analog downsampling and filtering [21]. They are excellent
examples of all that has been described so far. A large amount
of programmable filtering and decimation gives them more
flexibility than traditional receivers. Furthermore, the very
simple realizations of the RF/analog circuits enable the radio to
be integrated on the same chip as the DSP in deep-submicron
CMOS. However, both use preselect filters and tuned front-ends
for the respective bands, and therefore are not, in our sense,
software-defined receivers.
A. Baseband Circuits
We call a receiver SDR if it: (a) tunes to any band (from
800 MHz to 6 GHz is good enough today); (b) tolerates blockers
in its tuning range without a prefilter at the antenna; (c) uses a
low-power ADC to digitize the wanted channel and remaining
adjacent channels; and (d) exploits the conversion dynamic
range of the ADC to relax filtering and programmable gain in
the RF and analog front-end.
A receiver based on direct conversion to zero IF with a wide
tuning LO simplifies later signal processing. We describe, step
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Fig. 11. Software-defined radio receiver, tunable from 800 MHz to 6 GHz and configurable, mainly by choice of sampling clock, to receive channels as wide as
kHz to tens of MHz. The analog front-end following the mixer bears strong resemblance to the digital front-end following the ADC [see Fig. 2(b)].
by step, the development of this receiver’s architecture and
circuit blocks [23]. Contrary to the usual receiver design flow
which proceeds downstream from the antenna through the RF
sections to baseband, in this case we start with the ADC, then
proceed upstream.
Let us first examine feature (d) in the context of GSM reception (Fig. 10). The 200-kHz-wide wanted channel can be received at any strength ranging from 102 to 15 dBm, a dynamic range of 87 dB. What, then, is the minimum range of
analog variable gain before the ADC that will capture this dynamic range, while delegating as much as possible of the remaining automatic gain control (AGC) function to the DSP?
It is relatively easy in today’s technology to realize a deltasigma ADC that dissipates about 10 mW, and yields 14 bit resolution (86 dB SNDR) across 100 kHz. A GSM channel must be
detected with a minimum SNR of 9 dB for acceptable bit error
rate. Suppose the ADC quantization noise limits this SNR. If the
ADC full-scale is 1 dBm, it follows that the quantization floor
lies at 82 dBm across a 100 kHz bandwidth. The receiver need
amplify the minimum GSM signal at the antenna by only 43 dB,
that is, to 22 dB above the quantization noise floor, for the cumulative SNR to reach 9.2 dB: this is good enough.
Now consider the largest allowable GSM signal at the receiver input: this will overload the ADC unless the gain is lowered. What is the minimum by which the gain must be lowered? Allowing for 4 dB peak-to-average variation if the signal
is EDGE modulated, the gain must be lowered to 12 dB for
the waveform’s peaks to just reach the ADC’s full scale. This
means that with only 31 dB of variable gain in the RF/analog
front-end, the receiver can make use of surplus dynamic range
in the ADC to capture an input signal whose RMS strength
changes by 87 dB (Fig. 10) [22]. Of course, this underestimates
the real-life situation where strong adjacent channels are also
incident on the ADC, but that is the filter’s job.
Therefore, let us turn to this filter. With no RF prefilter, the
desired channel at zero IF is surrounded by other, possibly very
strong, channels in its own band as well as in all other bands.
Like the variable gain function just described, the on-chip filter
should, within reason, burden analog circuits only lightly, while
pushing as much as possible to DSP. Its job is mainly to prevent the composite waveform of unwanted channels from overloading a low power ADC. By lowering the total dynamic range,
filtering relaxes the linearity and power consumption of the cir-
cuits that follow. The receiver benefits most if the filter appears
immediately after the mixer.
To recapitulate, a windowed integration sampler is also
a filter that attenuates every aliasing channel that is a potential co-channel interferer for the wanted channel at DC.
Between nulls, the sidelobes in its frequency response roll off
at 20 dB/decade and attenuate, but do not suppress, adjacent
channels. Analog circuits following the sampler must operate
in discrete time. This is good, because switched circuits can be
tuned by a clock over orders of magnitude in frequency.
The initial sample rate that protects against aliasing will almost always be too high: it should be lowered by additional
filtering before sampling, and by decimation afterwards. This
begs the question, though, that to suppress aliases if the first
stage must sample at a high rate, then how can the second stage,
which operates at a lower rate, adequately suppress the new set
of co-channel interferers that pass through the first stage’s sidelobes?
The answer is that it cannot, unless the stopband of the second
decimation filter is deeper. This may need a decimation filter of
frequency response where
.
higher-order, with a
Then the stopband loss is
(3)
We have found one filter cascade—there may be others—that
works well for the two extreme cases of GSM and 802.11g
WLAN channels. We believe that by changing clock frequency,
it can be configured as well to work for most other cases when
the channel bandwidth is somewhere in between these two extremes. Although we arrive at this cascade by trial-and-error, in
future it should be possible to synthesize the optimal filter cascade by computer. In our SDR receiver (Fig. 11), the filter is a
poles at the mixer load, windowed integracascade of two
tion with an embedded D-T pole, followed by a second-order
filter that decimates by 4 , and finally a first-order sinc
filter that decimates by 2 or 3 .
Next we describe how to configure this filter to receive 802.
11g, which will also help the reader to understand how it works.
The channel of interest occupies 20 MHz in the 2.4 GHz ISM
band. To keep things simple let us assume that other channels
in the same ISM band are comparable in power and will not
overload the ADC. The CDMA band 200 MHz away is the
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
closest region of concern, because it contains channels at much
higher powers used for cellular communication. If we assume as
a worst case that every CDMA channel transmits at peak power,
then the filter must attenuate by 50 dB across the entire band
merely to prevent ADC overload [Fig. 12(a)].
If the initial sampling frequency also falls in this band, then
the attenuation must rise by another 30 dB in the 20 MHz-wide
interval around this frequency so that aliasing CDMA channels
located there do not overwhelm the wanted 802.11g channel.
Similar considerations lead to notches of various depths in the
filter specification at multiples of the sampling frequency.
It is hard to realize a continuous-time filter whose stopband
is deep enough to encompass these notches. An FIR filter, with
periodic nulls in its transfer function, is better suited to the job.
The windowed integration sampler is exactly such an FIR filter.
Suppose we choose an initial sample rate of 480 MHz. This
means that notches must be added to the filter specification at
480 MHz and its multiples, each notch 20 MHz wide; and the
first notch, because it lies in the CDMA band, must be 80 dB
deep [Fig. 12(a)].
Now let us develop the filter. To start with, we realize that
filter response is not seat 480 MHz, the sampler’s own
lective enough to fulfill the filter spec anywhere. However two
real poles preceding the sampler at frequencies just beyond the
wanted channel’s band edge, say at 15 and 20 MHz, add another 50 dB to the cascade loss at 480 MHz. This is now enough
to meet the spec at the first null [Fig. 12(b)]. The poles can be
realized with switch-selectable capacitors shunting the mixer’s
resistor loads. It is important that a linear passive RC circuit is
used, because it must filter amplified unwanted signals without
distortion. Once suppressed, they are relatively benign.
With these added poles, the filter specification is met everywhere except around 240 MHz, which is, coincidentally, half the
sample rate. There is a simple way using only one extra capacitor to add loss at this frequency. It makes use of the D-T pole
arising from a capacitor
at the sampler’s transconductor
output, in parallel with the periodically reset integration capacwhich forms a discrete-time resistor [Fig. 12(c)] [19].
itor
At sample rate the pole frequency is
4 , followed by 3 . The stopband specification evolves at each
step, in that the number of notches goes up by the decimation
factor. For every decimation the specification determines the
order of that filter. In the case of the first decimation by 4 we
filter is needed [Fig. 12(d)];
find by trial-and-error that a
filter is good enough
but for the next decimation by 3 , a
[Fig. 12(e)]. The latter filter is simpler because it benefits from
cumulative attenuation in the preceding cascade.
After two stages of decimation, notches appear in the filter
specification every 40 MHz apart. The cascade of decimation
filters produces the very sharp transition required by the first
notch [Fig. 12(e)], and it suppresses all unwanted channels so
well that a 40 MHz Nyquist ADC can capture the filter output
with a dynamic range of only 8 bits.
The cascade filter looks complex, but it is easy to implement
as a charge transfer circuit (Fig. 13). A transconductor after the
mixer integrates the input waveform on the sampling capacitor
that is selected sequentially from one of 8 parallel channels.
This capacitor, in turn, comprises four equal unit capacitors in
parallel. After sampling, charge from any number from one to
four of these unit capacitors is transferred to the next stage to
realize the tap weights of an FIR filter.
filter? This is the equivalent to
How to synthesize the
the cascade of two
filters, whose impulse response, therefilter’s unit rectangle
fore, must be the convolution of the
impulse response with itself; this is an isosceles triangle spanning two sample periods. After decimation by 4 each output
sample is formed by summing seven successive input samples
weighted by 1-2-3-4-3-2-1; and for uninterrupted throughput,
the next summation starts when the first sum is only half formed.
With 4 unit capacitors and 8 channels, time interleaving is
seamless. As 3, 2, and 1 unit capacitors in three channels share
their charges to convolve input samples with the falling edge
of the triangle, the other 1, 2, and 3 unit capacitors in the same
channels convolve the same input samples with the rising edge
of the next triangle. Thus, every unit capacitor is fully employed.
Summation entails connecting all weighted capacitors across
a discharged capacitor in the next stage. Four or three channels
filtering
of equal unit capacitors in the second stage realize
and decimation by either 3 or 2 .
For the capacitances actually used in the circuit, the cascade
DC gain presented to the wanted channel is [31]
(4)
As this is a discrete-time pole, its transfer function on the axis
of continuous input frequency is the superposition of images of
a single-pole rolloff around the sample frequency and its multiples. This leads to a periodically repeating frequency response,
with minima at half the sampling frequency, exactly where help
is needed, and its odd multiples. A D-T pole located at 25 MHz
gives 20 dB of additional loss at 240 MHz. Now the cascade
filter response meets the specifications everywhere.
But A/D conversion at 480 MHz wastes power when the spectrum of interest is only 10 MHz wide. The only remedy is
downsampling.
Let us say that our target sample rate is 40 MHz, a comfortable clock rate for a Nyquist ADC with modest resolution that
might dissipate 10 mW. We factor downsampling into two steps:
(5)
Therefore, the passive portions of this baseband circuit attenuate the integrating sampler’s own gain (1) by only 16/17, that
is, by slightly less than 1. Furthermore, we can show that if the
overall gain given by (5) is, say, 3 or more, the input-referred
, completely overvoltage noise density at zero IF is 4
noise involved in the charge transfers.
whelming any
is the noise factor of the transconductor circuit.
or
At a given sample rate, this gain can be varied with
with the sampling capacitance
. The transconductor is built
cells selectable with a 2 bit word, and
up of a set of four unit
a unit sampling capacitor consists of a fixed capacitor in parallel
with a 3 bit switch-selectable binary-weighted array. Thus, the
ABIDI: THE PATH TO THE SOFTWARE-DEFINED RADIO RECEIVER
963
Fig. 12. (a)–(e). Evolution of the sampler, baseband filter, and decimation stages to capture 20-MHz-wide 802.11g channel at zero IF in the absence of RF band
preselection.
DC gain through the sampler and filter cascade can be changed
with a digital word in 6 dB steps by a total of 30 dB.
Sampling of the continuous-time input waveform is not sensitive to the duty cycle of the clock waveform; only the repetition
964
Fig. 13. Circuit of entire analog baseband section, including sampler, two
stages of decimation, and filters. The use of only a single active element is
notable. Inset at upper right shows time-interleaved operation of FIR filter
associated with first decimation.
rate matters. All that is required is that switches should be on
for long enough to complete the charge transfer from a capacitor on one side to the other. When the current sampling switch
is off, the input current waveform continues to integrate on
and then redistributes the integrated charge with
all at once.
In this way the input waveform is sampled without interruption.
This circuit now embodies all functions of the analog baseband: sampling, decimation and associated filters, and variable
gain. The input transconductor is the only active circuit; the rest
of the circuit consists of passive switched capacitors, which are
very linear and scale well with shrinking CMOS technology.
This baseband filter in the SDR receiver assumes the role of
the RF passive prefilter (Fig. 14). Whereas an RF prefilter’s
characteristics are fixed,3 this filter circuit’s cutoff frequency
is clock programmable over decades. We must not overlook,
though, the fact that programmability relates to chip area: (5)
over a range of clock
tells us that to maintain constant
must scale by the same range. This imfrequencies,
plies a corresponding spread in component values. The measured on-chip selectivity is impressive [23] (Fig. 14), outstripping most other types of on-chip filter.
B. RF Circuits
Much innovation at the transistor level lies behind the RF
circuits in the SDR receiver, especially in the wideband LNA
and mixer. A detailed discussion of circuits here will cause us to
stray from our main theme, which deals with the evolution of a
new receiver architecture. Ref. [23] and antecedent publications
describe, in detail, the RF circuits at the transistor level. Here we
will discuss circuit imperfections because they limit how well
the receiver performs in wideband operation, as it is used here.
The price of filtering after the LNA and mixer is that large
unwanted signals can drive these circuits into nonlinearity, distorting the wanted channel. The two most important distortions
are cross-modulation due to third-order nonlinearity in either
the LNA or mixer, and AM detection by the second-order nonlinearity at the mixer’s output. Cross-modulation is best understood in terms of gain compression. It is well-known that a large
3This is the case today. Tunable MEMs-based filters are in the research phase.
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
Fig. 14. Filter configured for two different receive conditions: 802.11g, where
unwanted CDMA channels band pose greatest threat; and GSM, where the filter
must suppress 0 dBm blockers anywhere outside the band. Measured filter response meets specifications to very large offsets.
unwanted signal at any frequency applied to an amplifier with
compressive nonlinearity causes the small-signal gain to drop
by an amount dependent on the square of its amplitude [24].
It follows that modulation of this amplitude also modulates the
small-signal gain. In this way the unwanted signal imposes itself
by subjecting a small wanted signal to modulated gain. AM detection in direct conversion receivers is better understood. The
SDR receiver is vulnerable all the time to distortion due to AM
detection and cross-modulation arising from an unwanted signal
anywhere. This is why in a wideband zero IF receiver these two
forms of distortion are more insidious than others.
As the signal at the output of the non-selective wideband LNA
has been amplified, it will cause greater distortion in the mixer
that follows. Of course the mixer amplifies still further but its
output is filtered, and even a mild amount of filtering (as long
as the filter attenuation is greater than the mixer gain) is enough
to sharply lower distortion in the following circuits. In general,
we may say that distortion is a problem in the receiver only up
to the point that there is no filtering. In our receiver, this means
that it is a problem up to the mixer output.
Thus, mixer linearity is paramount. The mixer must be based
on a sound circuit topology. The best topology we have found
is the double-balanced, passive FET mixer driven by a large
square-wave-like LO voltage to commutate signal current [25].
This suppresses both flicker noise in the mixer core as well as
second-order intermodulation distortion. There is a simple way
to understand that the two are related. Offset between cross-coupled mixer FETs can be modeled as a non-zero voltage source
in series with the gate of one FET. It is offset, usually, which
causes imbalance and mismatch that leads to second-order intermodulation effects. By thinking of the offset as slowly varying
, noise. Then it
and random, we may also model flicker, or
follows that methods to mitigate the offset from inducing intermodulation, such as driving the gate with square wave-like LO,
noise at the mixer output [26].
also suppress
There is also the problem of harmonic mixing, unique to
a wideband receiver. If the mixer is driven by an LO, say, at
900 MHz, the square-wave commutation also contains smaller
amounts of third and fifth harmonic at 2700 MHz and 4500 MHz
ABIDI: THE PATH TO THE SOFTWARE-DEFINED RADIO RECEIVER
Fig. 15. Frequency synthesis plan using three stagger-tuned LC oscillators and
dividers to cover the SDR receiver’s full tuning range. Each oscillator tunes only
by 15%.
6
that will downconvert unwanted signals at these frequencies to
zero IF, superimposing them upon, and possibly overwhelming
the wanted signal at 900 MHz that has been mixed to zero IF.
Bagheri et al. [23] discuss this in depth, and describe a way to
lessen unwanted harmonic mixing.
Last, the complete receiver needs a frequency synthesizer
with wide tuning range. A single oscillator that tunes from
800 MHz to 6 GHz must be of the relaxation or ring type,
but it will consume exorbitant power [27] to satisfy the very
oscillator takes much
low phase noise for, say, GSM. An
less power, but its tuning range is by comparison very limited.
Switched capacitor banks help to expand tuning range, but
only up to the point that spectral purity enters into the tradeoff.
oscillators centered at staggered
We have found that three
frequencies, each with 15% tuning range, and followed by
a bank of dividers and a multiplexer, can cover the band from
800 MHz to 6 GHz (Fig. 15). Only one oscillator is active at a
time. It is not wise here to synthesize frequencies by addition
or subtraction with single-sideband (SSB) mixers, because
residual spurs at unwanted sidebands are sure to lie in this
receiver’s wide passband. With realistic mismatches, spurs can
be as high as 40 dBc [28].
Preceded by a low-noise wideband amplifier [29], the elements described so far comprise the first single-chip CMOS
software-defined receiver (Fig. 11) [23]. To receive GSM at
900 MHz, it uses a 9 MHz (decimated from an initial
72 MHz) sigma-delta ADC resolving 14 bit in 100 kHz; and
to receive 802.11g at 2.4 GHz, it uses an 8 bit, 40 MHz (deci480 MHz) Nyquist ADC. In today’s
mated from an initial
state-of-the-art, each ADC consumes about 10 mW. The receiver’s cascade IIP3 of 6 dBm and IIP2 of 65 dBm, limited
by the LNA and mixer circuits, are good enough to enable it to
demodulate a minimum GSM signal in the presence of an unwanted 20 dBm CDMA (amplitude-modulated) channel.
IV. DISCUSSION AND OPEN PROBLEMS
Over the 10 years since software-defined radio was first proposed, developments following a somewhat erratic course have
finally led to a practical prototype. Success has depended on architectural innovation, but also on a new generation of front-end
circuits, such as the wideband low-noise amplifier and mixer.
The architectural innovations stem from a deconstruction of
Mitola’s original proposal, which reveals that SDR based on
a “giant” ADC and powerful enough DSP can receive every
channel concurrently. This is far more than what mobile telephones need, where it is good enough to be able to receive two
or three channels concurrently from different bands. In this context, we can re-define SDR as being able to tune to one channel
965
of any bandwidth, in any band from 800 MHz to 6 GHz. This
would make it a universal receiver for almost all mobile communication today.
Tuning the channel of interest to zero IF greatly simplifies the
receive RF/analog signal processing. The low-pass windowed
integration sampler, also known as the integrate-and-dump or
boxcar integrator, takes on new life as a device to sample a narrowband channel at zero IF, while protecting it from aliasing an
unlimited band of other signals. When these other signals are
larger than the wanted one, as is usually the case, a high initial
sampling frequency gives sufficient protection. Almost always
this is too high to enable A/D conversion at low power. Yet the
wanted narrowband channel alone can be digitized at a low rate.
Decimating the analog samples closes this gap in rates.
However, decimation itself needs an anti-aliasing filter, which
is usually embedded in the decimator circuit. By distributing
the usually large decimation factor over two or more stages, the
cascaded anti-alias filters greatly suppress unwanted channels
that otherwise would accumulate near the wanted channel by
aliasing. This lowers dynamic range, and power, in the A/D converter that follows.
In contrast to the elements used in conventional receivers, the
circuits described so far are all very flexible. For example, the
LO generator is widely tunable; sampling rate depends on an
arbitrarily chosen clock frequency; decimation factor, as well as
the number of stages, can be selected by the user. The remaining
RF and analog signal processing should stay true to this spirit.
An RF low-noise amplifier can be called flexible if it presents
uniform gain and noise figure in every communication band. We
have developed such a 90-nm CMOS wideband amplifier up to
6 GHz. The mixer input stage offers uniform transconductance
to inputs up to 6 GHz and beyond. Analog AGC must also be
kept to a minimum, and like filtering, should be pushed into
the DSP as much as possible. In fact, the functions of sampler,
multi-stage decimator, and AGC function can all be combined
into a single passive charge-transfer circuit.
Although the on-chip filter is programmable and its selectivity surpasses a fixed RF prefilter, the front-end LNA
and mixer are exposed to all signals, wanted or not. The two
circuits must be very linear to protect the wanted channel from
corruption caused through cross-modulation or AM detection
due to large, unwanted signals in any band.
So far we have shown that the new receiver architecture is feasible for SDR. However, many open problems remain, and are
worthy of future research. Wireless standards such as CDMA
operate in full duplex, that is, the transmitter and receiver operate simultaneously through a common antenna. Although the
transmitter uses its own frequency band, the transmit signal level
is so high that it will saturate the receiver through the common
antenna terminal. CDMA handsets today use an RF duplexer
filter at the receiver input to attenuate the transmit band. But
our SDR philosophy forbids the use of fixed filters. Some other
solution must be found.
The flexible receiver platform described so far receives any
one channel at a time. It can also receive two or more arbitrarily spaced channels concurrently, if the received frames fall
in non-overlapping time slots, by simply hopping the frequencies of the LO and sampling clock. However, we have not yet
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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 5, MAY 2007
found a hardware-efficient way to concurrently receive multiple
continuously transmitted channels.
The software-defined radio is a work in progress. It promises
to keep researchers in circuits and systems busy for a while.
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Asad A. Abidi (S’75–M’80–SM’95–F’96) received
the B.Sc. (with honors) degree from the Imperial College, London, U.K., in 1976, and the M.S. and Ph.D.
degrees in electrical engineering from the University
of California, Berkeley, CA, in 1978 and 1981, respectively.
From 1981 to 1984, he was with Bell Laboratories,
Murray Hill, NJ, as a Member of Technical Staff at
the Advanced LSI Development Laboratory. Since
1985, he has been with the Electrical Engineering
Department, University of California, Los Angeles
(UCLA), where he is a Professor. He was a Visiting Faculty Researcher at
Hewlett Packard Laboratories in 1989. His research interests are in CMOS RF
design, high speed analog integrated circuit design, data conversion, and other
techniques of analog signal processing.
Dr. Abidi was the Program Secretary for the IEEE International Solid-State
Circuits Conference (ISSCC) from 1984 to 1990, and the General Chairman of
the Symposium on VLSI Circuits in 1992. He was the Secretary of the IEEE
Solid-State Circuits Council from 1990 to 1991. From 1992 to 1995, he was the
Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received an IEEE
Millennium Medal, the 1988 TRW Award for Innovative Teaching, and the 1997
IEEE Donald G. Fink Award, and is co-recipient of the Best Paper Award at the
1995 European Solid-State Circuits Conference, the Jack Kilby Best Student
Paper Award at the 1996 ISSCC, the Jack Raper Award for Outstanding Technology Directions Paper at the 1997 ISSCC, the Design Contest Award at the
1998 Design Automation Conference, an Honorable Mention at the 2000 Design Automation Conference, and the 2001 ISLPED Low Power Design Contest
Award. He is a Fellow of the IEEE, a member of the National Academy of Engineering, and he was named one of the top ten contributors to the ISSCC.