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QIE10: a new front-end custom integrated circuit for high-rate experiments
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2014 JINST 9 C01062
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P UBLISHED BY IOP P UBLISHING FOR S ISSA M EDIALAB
R ECEIVED: November 14, 2013
ACCEPTED: December 17, 2013
P UBLISHED: January 31, 2014
TOPICAL W ORKSHOP ON E LECTRONICS
23–27 S EPTEMBER 2013,
P ERUGIA , I TALY
FOR
PARTICLE P HYSICS 2013,
A. Baumbaugh,a L. Dal Monte,a G. Drake,b,1 J. Freeman,a D. Hare,a
H. Hernandez Rojas,c E. Hughes,d,1 S. Los,a D. Mendez Mendez,e J. Proudfoot,b
T. Shaw,a C. Tully, f R. Vidal,a J. Whitmorea and T. Zimmermana,2
a Fermi
National Accelerator Laboratory,
Box 500, Batavia, IL 60510, U.S.A.
b Argonne National Laboratory,
9700 S. Cass Ave., Lemont, IL 60439, U.S.A.
c Florida Institute of Technology Physics and Space Sciences,
150 W. University Blvd., Melbourne, FL 32901, U.S.A.
d Department of Physics, Rutgers University,
136 Frelinghuysen Rd., Piscataway, NJ 08854, U.S.A.
e Facultad de Ciencias, Universidad Nacional Autonóma de México,
Av University 3000, Circuito Exterior S/N, Coyoacán, CP 04510, México
f Department of Physics, Princeton University,
Jadwin Hall, Princeton, NJ 08544, U.S.A.
E-mail: drake@anl.gov, tote@physics.rutgers.edu, tzimmer@fnal.gov
A BSTRACT: We present results on a new version of the QIE (Charge Integrator and Encoder), a
custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from photo-detectors in high-rate environments, this most
recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal
charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for
calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration
studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades.
K EYWORDS : VLSI circuits; Front-end electronics for detector readout; Radiation-hard electronics
1 Corresponding
2 Chip
author.
designer.
c 2014 IOP Publishing Ltd and Sissa Medialab srl
doi:10.1088/1748-0221/9/01/C01062
2014 JINST 9 C01062
QIE10: a new front-end custom integrated circuit for
high-rate experiments
Contents
Introduction
1
2
Principles of operation
2
3
Bench test results
5
4
Radiation test results
9
5
Outlook and plans
11
6
Summary
11
1
Introduction
The QIE10 is the newest version in the family of devices designed at Fermilab for use in measuring signals from photo-detectors. The QIE (Charge Integrator and Encoder) integrates input
charge pulses (or current) in 25 nS periods, and digitizes at 40 MHz using 4 phases of operation in
pipelined fashion. It has 17 bits of dynamic range, which are encoded into 6 bits of mantissa and
2 range bits, or 256 codes. This scheme provides a floating point digitization of the input charge
at 40 MHz, and is dead-timeless. The device has approximately logarithmic response, with approximately constant resolution over the dynamic range. The device also has a 6 bit time-to-digital
converter (TDC), with ∼ 0.5 ns resolution for each time slice. The QIE10 is fabricated in a 350 nm
SiGe process, providing intrinsic hardness against ionizing radiation.
The latest version of the QIE comes from a relatively long and successful history of development and use in HEP experiments. The very first prototype was designed in 1989 for the Solenoidal
Detector Collaboration (SDC), a detector that was being designed for the Superconducting Super
Collider (SSC). In 1995, the first fully-functional QIE was designed for the KTeV experiment
at Fermilab [1], and fabricated in a 2 µm Bi-CMOS process from Orbit Semiconductor. The experiment consisted of 3,000 channels, and operated at 53 MHz, the fundamental frequency of the
Tevatron. In 1996, a version of the QIE was adapted for the upgrade of the calorimeter electronics
for the CDF experiment at Fermilab [2, 3], called QIE3. The detector required 10,000 channels,
and operated at 7.58 MHz. In 2002, another version of the chip, QIE7, was designed for the Near
Detector of the MINOS experiment at Fermilab [4], which operated at 53 MHz. This again used
the 2 µm Bi-CMOS process from Orbit Semiconductor, and the production run produced 20,000
chips. In 2003, a new version was designed for the hadronic calorimeters of the CMS experiment at CERN. This version, QIE8, used new design techniques that incorporated a differential
input, and a logarithmic transfer function. It also used a newer (and better) fabrication process, the
0.8 µm AMS process, which featured “real” BiCMOS technology. The chip operates at 40 MHz,
–1–
2014 JINST 9 C01062
1
Figure 1. Block diagram of the signal processing chain in the QIE.
2
Principles of operation
A simple block diagram of the chip is shown in figure 1. The device receives charge (or current,
positive convention) from a photo-detector (PMT), and splits the current into four logarithmicallyweighted ranges. Each range then integrates the resulting current fractions onto separate capacitors
using gated integrators, with the integration period, or “time slice”, set to 25 ns. After the integration period, subsequent circuitry selects the one range that is within the dynamic range of the
on-board flash analog-to-digital converter (FADC). The voltage on the selected range is then multiplexed to the FADC, which has a nonlinear transfer function, where it is digitized, producing 6
output bits or the “mantissa”. The ADC bits are then output from the chip, along with a 2 bit code
to indicate which of the four ranges was digitized.
As stated earlier, the QIE10 produces an approximately logarithmic response. This is accomplished in two parts. The first is the current splitter, which splits the charge into ranges weighted as
16/24, 4/24, 2/24, and 1/24, as shown in conceptually in figure 2. A fifth splitter stage consisting
of 1/24 of the input current is use for the time-to-digital convertor (TDC), which will be described
later. The second part of the logarithmic response is due to the nonlinear FADC, which has a
transfer function as shown in figure 3 (response of Range 0 is shown, but all ranges have the same
relative response). The combined response of the current splitter and the nonlinear FADC produces
a transfer function for the raw data as shown in figure 4. The response from each of the four ranges
can be seen. By using a calibration procedure, the overall transfer function of the device can be
obtained, as shown in figure 5. Note that response over five orders of magnitude is accomplished
with only 8 output bits (256 codes). All 256 codes are represented in figure 5.
–2–
2014 JINST 9 C01062
the fundamental frequency of the LHC. There were 10,000 channels produced and installed into the
detector. With each new version, the design techniques improved, and the fabrication techniques
and processes generally improved as well. The design of the QIE10 was based largely on the QIE8,
utilizing the differential input and logarithmic response, but also includes new features, including
a 6 bit TDC, and on-board charge injection. The device has several programmable features, which
are programmed by a serial interface using a shift register on the input, and then a shadow register
for storing the data. The shadow register has been designed to be SEU-tolerant. The 350 nm SiGe
fabrication process is also significantly superior to the previous fabrication processes in terms of
improved bipolar transistor performance, and better tolerance to ionizing radiation. The chip is
fairly low power, consuming 320 mW of power. The result is the best-performing device of the
family of chips to date, as will be described. It will be incorporated in the upgrade of the CMS
hadronic calorimeter upgrade, and is a candidate for the ATLAS TileCal upgrade.
Figure 3. Simulated FADC transfer function.
As mentioned earlier, the operations of the QIE are pipelined. The diagram of the splitter
circuit in figure 2 illustrates the stages. Each operation lasts for one clock cycle. The integrating
capacitors shown in figure 2 are first reset by closing the reset switches for one clock cycle, called
the reset cycle. Next, the integrate switches are closed for one clock cycle, called the integration
cycle. When the switches are opened, the voltages on the capacitors are the superposition of the
integrated currents from the bias current source and the PMT input, split into ranges as described
above. At the end of this cycle, the capacitor voltages are buffered and driven to a set of com-
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2014 JINST 9 C01062
Figure 2. Conceptual configuration of the current splitter.
Figure 5. Simulated overall transfer function after calibration.
parators, where they are compared against preset threshold voltages. This is called the comparison
cycle. The comparators determine which capacitor voltage will be multiplexed to the analog output
of the chip for digitization. Because of the configuration of the bias current and the current-split
ratios, one and only one voltage will lie within a predetermined range for digitization. The selected
capacitor voltage is then digitized on the digitization cycle. After digitization, the process then
repeats.
As described so far, the processing of a single time slice requires four clock periods. For the
chip to be dead-timeless, the QIE is arranged to have four sets of integrating capacitors on each
range, instead of one for each range, as shown in figure 6. There are also four sets of comparison
circuits. At any given time, one set of capacitors is being reset, another is integrating, another
is undergoing range comparison, and the other is being digitized. The operations are phased as
shown in the table. In addition to the mantissa and range bits, the QIE outputs two bits called
the CAPID, which indicate which set of capacitors was selected for a given digitization cycle.
The CAPID advances with every clock cycle, modulo 4. This provides the capability to uniquely
–4–
2014 JINST 9 C01062
Figure 4. Simulated transfer function of the raw data showing all 4 ranges.
identify the integration capacitor and analog processing stage associated with a given data word, so
that calibration constants can be applied to decode the data. In addition, there is a global reset that
can be used to reset all of the QIE CAPIDs across the system. Thus, for a given beam crossing,
the data acquisition system can check that all QIE data words have the same CAPID, providing
a method of checking data integrity. Thus, there are a total of 10 bits representing the charge
delivered (6 ADC, 2 RANGE, 2 CAPID), plus 6 bits of TDC for each data word, 16 bits total.
Note that the actual device is significantly more complex than that shown in figures 2–6, which
illustrate the basic operation only. The interested reader is referred to [5] for more details.
3
Bench test results
The goal of the bench testing is to verify that the various performance aspects of the QIE10 meet
expectations. This is needed to gain confidence before production. To do this, a series of detailed studies have been executed to determine that the chip meets or exceeds the performance
requirements. The bench tests are also valuable for reference later, when designing the production
checkout procedures to validate every packaged chip destined for a detector.
A first test is to read the pedestals, defined as the data obtained with no external input signal.
This will give an indication of the intrinsic noise of the device. Each CAPID will have its own
pedestal, so it is important to keep track of the CAPID. A pedestal measurement is shown in
figure 7. Note that for CapID0, the pedestal is almost entirely in one ADC bin, whereas for CapID2,
the pedestal is almost exactly split between two ADC bins. Given that a least count corresponds
to 3 fC, the intrinsic noise of the device is thus ∼ 1.5 fC RMS. Note that this is with no source
capacitance. The QIE10 also has a feature where the pedestal values of each CAPID can be adjusted
to give a uniform response if desired.
To test the ADC and encoding functionality of the QIE10, a precision current source is used.
The value of the current is increased in small steps to probe all codes of the dynamic range. This
process is controlled by a computer running test-specific algorithms to control the input current,
–5–
2014 JINST 9 C01062
Figure 6. Pipelined operation in the QIE using 4-phase processing.
Figure 8. Measured response on a single range for a single CAPID using DC current injection.
verify CAPID rotation, and organize the data into output files. For each setting, the mantissa and
range is recorded. A plot of the response of a single range is shown in figure 8. The four segments
of the FADC response can be seen (refer to the ideal response of figure 3). A plot of the raw data
for one CAPID is shown in figure 9. Again, it matches expectations.
All 64 bins of the 6-bit FADC were measured using DC current injection. A plot of the bin
widths versus ADC code is shown in figure 10. The bin width variation is less in the bottom two
–6–
2014 JINST 9 C01062
Figure 7. Distributions of pedestal measurements for each CAPID.
Figure 10. Measured bin widths vs. ADC code.
sections than in the top two by design. The quantization error, δ , is a measure of the uncertainty
associated with binning. Knowing the bin widths, it is defined for the ith charge bin as
1
Si
δ=√
12 qi
(3.1)
where Si is the bin’s sensitivity and qi is the central value of the bin, expressed in terms of charge.
Using the values from the above studies, the quantization errors can be calculated as shown in
figure 11.
In order to ensure that there are no missing codes or dead regions, the QIE10 was designed
so that every range should overlap with neighboring ranges by approximately 3 charge bins. The
QIE10 has a feature where the auto-range select function can be turned off, forcing a measurement
on a selected range. A representative measurement using this technique is plotted in figure 12,
–7–
2014 JINST 9 C01062
Figure 9. Measured response on all four ranges for a single CAPID using DC current injection.
Figure 12. Measurement of range overlap using manual range select feature.
showing a nice overlap between range 0 and range 1. This will be one of the criteria used in the
checkout of chips for production.
The previous measurements were done with precision DC currents. Turning now to dynamic
performance, one measurement of interest is sweeping a constant charge pulse through different
time slices, to see if there are dynamic effects or “charge-loss” at the clock boundaries. A measurement of this is plotted in figure 13, where the ADC values are added together for every two
consecutive clock cycles. The QIE codes must be calibrated and pedestal subtracted to do this
properly. As can be seen, the response is flat as a function of pulse delay to better than ±2%,
indicating good dynamic performance.
The TDC is a new function for the QIE. Using charge pulses with variable delay, the TDC
response was measured. The transfer function is shown in figure 14, and the distribution of bin
widths is plotted in figure 15. Except for one outlier at 12 ns, the bin widths are well behaved.
–8–
2014 JINST 9 C01062
Figure 11. Measured quantization error.
Figure 14. Plot of TDC transfer function.
Further tests are planned, although this performance is acceptable for measuring out-of-time hits,
where ∼ 1 ns resolution is required.
4
Radiation test results
We have performed two radiation studies to date on the full version of the QIE10. The first was
a study of the effect of ionizing radiation (TID) using a Cesium-137 source at Argonne National
laboratory that produced ∼ 1 KRad per hour. Two devices were irradiated. The test regimen read
and recorded the pedestals two times per hour, and read the shift registers and shadow registers
continuously to look for corruption. The test was run for 52 hours, acquiring 52 KRad of dose for
the device nearest to the source, and 35 KRad to the device farthest from the source (the difference
being due to 1/R2 effects). The results of the pedestal measurements are shown in figure 16. There
were effectively no changes in either the pedestal values or the noise during the dose period. The
–9–
2014 JINST 9 C01062
Figure 13. Measurement of dynamic performance by sweeping a charge pulse through time slices.
Figure 16. Measurements of pedestal values and pedestal noise as a function of ionizing dose.
chips remained functional throughout the test, and there were no data corruption errors detected
through the test period.
The second test was a study of the effect of proton bombardment on the device, looking primarily for single event upsets (SEUs) in the shift register and the shadow register. The measurements
were performed at CDH/Procure, a cancer treatment facility, in Warrenville, Illinois. The beam
energy was 230 MeV. Again, two boards were used in the test. The boards were irradiated to
6E12 p/cm2 . The result was that 2 SEU errors were recorded in the shift register readout, and 0
SEU errors recorded in the shadow register readout. This was expected, since the shadow register
uses SEU-tolerant design techniques, while the shift register does not. Since the chips will generally be configured at the start-up of a run, before beam collisions, the SEU tolerance of the shift
register is less important than the shadow register, which must hold the programming bits continuously through the run. Unfortunately, with proton bombardment, there is a significant ionizing
– 10 –
2014 JINST 9 C01062
Figure 15. Distribution of TDC bin widths.
dose that is received, approximately 330 KRad for this amount of protons. The analog readout of
both QIEs was not functional after this test. However, the digital read/write capability remained
functional through the end of the test.
We have not performed non-ionizing energy loss (NIEL) tests yet, to measure displacement
damage particularly in the NPN transistors. This remains one of the test programs ahead.
5
Outlook and plans
6
Summary
The design and performance of the QIE10 have met or exceeded expectations. The device has very
low intrinsic noise. The encoding of 17 bits of dynamic range using 8 bits makes efficient use of
bandwidth. The addition of the 6-bit TDC adds a powerful capability to the QIE, allowing the
measurement of out-of-time hits directly from the device. The indications to date are that this is the
– 11 –
2014 JINST 9 C01062
The performance of the QIE10 chip is significantly improved over the previous version, QIE8. The
performance tests to date have yielded excellent results. The addition of the TDC, and also the
added radiation tolerance offered by the 350 nm SiGe process, make it well-suited for use in the
LHC upgrades. The SEU and TID radiation tolerance tests to date show good performance, and
meet the requirements for both the CMS hadron calorimeters and the ATLAS hadron calorimeter. Additional tests are planned, including measurements in a test beam, and additional radiation
measurements, in particular non-ionizing radiation effects (displacement damage). Assuming that
all goes well, the plan is to use the QIE10 in CMS for the upgrade of the Forward Hadron (HF)
calorimeter. The HF is a Chereknov calorimeter with a narrow pulse width, fully contained within
25 ns, and therefore the TDC function of the QIE10 is particularly important for identifying out-oftime pulses. The detector has 1,728 4-anode PMTs, each of which are currently ganged together
into one readout channel. In the new electronics, the QIE10 will be used to readout 2 anodes
ganged together, requiring 3,456 channels total. This will be installed into the detector during the
2014/2015 winter shutdown. The production will be done as a small production run. Plans are
underway to develop a production checkout program using the robotic chip tester at Fermilab.
CMS will also be upgrading the Barrel Hadron calorimeter and the Endcap Hadron calorimeter. These detectors currently have Hybrid Photo Detectors (HPDs). The current plan is to replace
them with silicon photo-multipliers (SiPMs), and use a modified version of the QIE10 for the readout. The modification consists of adding a programmable shunt to the input, to provide capability
to retain dynamic range in the presence of higher quiescent current. This design modification will
be incorporated into QIE11, a first prototype of which is currently being fabricated. Assuming no
problems, the plan is to install them during the 2018 shutdown. Test beams to test both QIE10 and
QIE11 are planned for 2015–2016.
The ATLAS Hadronic calorimeter (TileCal) does not currently use QIEs. Work is in progress
to build a prototype “drawer” that contains the electronics for one detector module, as a step toward
a full upgrade for Phase 2 in 2022. The QIE10 is a candidate technology for this upgrade. The plan
is to build a full drawer with QIEs, and test in a test beam in ∼ 2015–2016. A decision on the
choice of technology for this upgrade would come after this evaluation.
best-performing device in the QIE family, and should perform well in the high-rate environment of
the LHC.
Acknowledgments
References
[1] R.J. Yarema, G.W. Foster, J. Hoff, M. Sarraj and T. Zimmerman, A fast, wide range charge integrator
and encoder ASIC for photomultiplier tubes, IEEE Trans. Nucl. Sci. 40 (1993) 750.
[2] CDF-II collaboration, R. Blair et al., The CDF-II detector: technical design report,
FERMILAB-PUB-96-390-E (1996).
[3] T. Zimmerman and M. Sarraj, A second generation charge integrator and encoder ASIC,
IEEE Trans. Nucl. Sci. 43 (1996) 1683.
[4] MINOS collaboration, The MINOS detector, technical design report, NUMI Note NuMI-L-337
(1998).
[5] T. Zimmerman, QIE10: a new charge-integrating floating-point ADC chip for high-rate experiments,
talk given at the IEEE Nuclear Science Symposium & Medical Imaging Conference, Seoul,
South Korea (2013).
– 12 –
2014 JINST 9 C01062
We thank the technical support personnel at Argonne National Laboratory and Fermi National
Accelerator Laboratory for assisting with the building of boards and test fixtures used in carrying
out these tests. We also thank Mark Pankuch of Central DuPage Hospital/ProCure for the help and
assistance with the proton tests. This work was supported by the U.S. Department of Energy, Office
of Science, Office of Basic Energy Sciences, under contract DE-AC02-06CH11357.