85nm Gate Length Enhancement and Depletion mode InSb Quantum Well Transistors
for Ultra High Speed and Very Low Power Digital Logic Applications
S. Datta, T. Ashley*, J. Brask, L. Buckle*, M. Doczy, M. Emeny*, D. Hayes*, K. Hilton*, R. Jefferies*, T.
Martin*, T. J. Phillips*, D. Wallis*, P. Wilding* and R. Chau
Components Research, Technology and Manufacturing Group, Intel Corporation, Hillsboro, USA
*QinetiQ, Malvern Technology Center, Malvern, UK
Email: robert.s.chau@intel.com
Carrier mobility [cm
We demonstrate for the first time 85nm gate length
enhancement and depletion mode InSb quantum well
transistors with unity gain cutoff frequency, fT, of 305 GHz and
256 GHz, respectively, at 0.5V VDS, suitable for high speed,
very low power logic applications. The InSb transistors
demonstrate 50% higher unity gain cutoff frequency, fT, than
silicon NMOS transistors while consuming 10 times less active
power.
2V-1 s-1]
Abstract
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30000
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0
Introduction
LSD
LG
LG
Gate
Gate
Drain
Source
AlxIn xSb barrier
InSb quantum well
Al xIn x Sb buffer
Source
AlyIn 1-ySb buffer
Semi-insulating GaAs substrate
a) Depletion Mode
Drain
Etch Stop
layer
M odulation
doping
0
5E+11
1E+12
1.5E+12
2E+12
Sheet carrier density [cm-2]
Indium antimonide (InSb) holds promise for ultra-fast, very
low power digital logic applications as it has the highest
electron mobility and saturation velocity of any known
semiconductor. This performance potential was demonstrated
before in a 200nm gate length (LG) depletion mode InSb
quantum well transistor (QWFET) with 150GHz fT at 0.5V
VDS [1] and subsequently a 100nm LG depletion mode device
with 210GHz fT [2]. In both cases, the transistors were
fabricated on a semi-insulating GaAs substrate using a relaxed
metamorphic buffer layer of AlyIn1-ySb to accommodate lattice
mismatch, a compressively strained InSb quantum well
confined between layers of AlxIn1-xSb and a Schottky barrier
metal gate. The quantum well transistor architecture employs
barrier layers with higher bandgap materials to mitigate the
effect of the narrow bandgap InSb on device leakage and
breakdown. For high speed direct coupled FET logic (DCFL)
applications, both enhancement (i.e. positive VT) and depletion
mode devices are required. In this paper, we report, for the first
time, on the fabrication and characterization of 85nm gate
LSD
Remote doped in
15% Al barriers
Remote doped in
20% Al barriers
Remote doped in
30% Al barriers
Bulk InSb (20nm
well)
InSb quantum well
AlxIn xSb buffer
Aly In1-ySb buffer
Semi-insulating GaAs substrate
b) Enhancement Mode
Fig. 1 Schematic of the depletion mode and enhancement mode InSb
quantum well transistors
Fig. 2 Hall Mobility data on modulation doped 20nm thick InSb quantum wells
with 15%, 20% and 30% Al in the AlxIn1-xSb barrier layer [1]
length enhancement (e-mode) and depletion mode (dmode)InSb QWFETs. An enhancement mode InSb QWFET is
demonstrated for the first time using a deep recess etch in the
gate region, which shows a peak fT of 305GHz at 0.5V VDS. A
depletion mode device is demonstrated at the same time
utilizing a shallow recess gate with a peak fT of 256GHz at
0.5V VDS. The demonstration of both high performance
depletion and enhancement mode InSb QWFETs makes the
technology a promising candidate for future high speed, low
power logic applications. Benchmarking with advanced silicon
MOSFETs indicates that the InSb QWFETs can provide 1.5×
faster switching speed with a simultaneous 6-10× reduced DC
power dissipation. Due to the small gate to channel separation,
the deep recess gate 85nm LG e-mode devices exhibit excellent
sub-threshold slope of 105 mV/dec and DIBL of 95mV/V,
with maximum ION-IOFF ratio of 330 limited by the gate leakage
current. To improve the ION-IOFF ratio, a promising high-k
dielectric on the AlInSb/InSb device layers is identified here
with moderate hysteresis, low frequency dispersion and four
orders of magnitude reduction in gate leakage.
Enhancement and Depletion Mode InSb Transistors
Both depletion and enhancement mode InSb QWFETs were
fabricated on semi-insulating GaAs substrates. The layers from
the bottom to top consist of an accommodation layer, a 3µm
AlyIn1-ySb buffer, a 20nm thick InSb quantum well, a 5nm
thick Al0.2In0.8Sb spacer, a single Te δ-doped donor layer (11.8×1012cm-2 and µ=18-25000cm2V-1s-1) and a 45nm thick
Al0.2In0.8Sb barrier layer with an optional etch-stop layer.
0-7803-9269-8/05/$20.00 (c) 2005 IEEE
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1.E-01
1.E-02
1.E-03
Depletion mode
Enha ncement mode
1.E-04
-0.5
-0.3
-0.1
0.1
0.3
150
LSD = 0.75 um
140
130
120
[mV/dec]
V D S =0.5, 0.05V
Sub-threshold Slope, S/S @ VDS=0.5V
Drain Current, ID [mA/um]
/um]
1.E+00
110
100
90
80
Enhancement mode
70
Depletion mode
60
50
100
0.5
150
200
250
Gate Length, LG [nm]
Gate Voltage, V G [V]
200
DIBL [mV/V]
160
0.15
0.05
100
150
200
250
-0.15
-0.35
120
100
80
60
40
Enhancement mode
20
Depletion mode
50
100
150
200
250
Gate Length, LG [nm]
Fig. 6 DIBL as a function of gate length for depletion and enhancement
mode InSb QWFETs
350
LG = 85nm
VDS = 0.5V
300
250
200
150
100
Depletion mode
50
0
-0.6 -0.4 -0.2
Enhancement mode
0
0.2
0.4
0.6
Gate Voltage, VG [V]
Fig. 7 Intrinsic (de-embedded) cut-off frequency, fT, for 85nm gate length
depletion and enhancement mode InSb QWFETs at 0.5V VDS
350
LSD = 0.75 um
-0.25
140
0
0.25
-0.05 50
LSD = 0.75 um
180
Enhancement mode
Depletion mode
Cutoff Frequency, fT [GHz]
Threshold Voltage, VT @ VDS=0.5V [V]
Increasing the Al percentage in the upper barrier to 30% would
increase the QW room temperature electron mobility to
30,000cm2V-1s-1 with a sheet carrier density of 1.3×1012 cm-2
further demonstrating the potential for improved high speed
performance (Fig. 2). For the e-mode devices, an increased δ
doping level is used to reduce the access resistance and a
highly selective etch chemistry to deep recess the gate. Fig. 3
compares the typical transfer characteristics of the 130nm LG
e- and d-mode devices with a threshold voltage, VT, shift of
250mV. Fig. 4 shows that the e-mode devices have improved
VT roll-off characteristics and, hence, better short channel
effects than the d-mode devices. This is further illustrated in
Figs. 5 and 6, where the deep recess gate e-mode devices show
much improved sub-threshold slope and DIBL characteristics
over the depletion mode devices due to shorter gate to channel
separation. This implies that small gate to channel separation is
a key component of LG scaling for future InSb based QWFETs.
Fig. 7 compares the intrinsic (de-embedded) cut-off frequency,
fT, of 85nm gate length depletion and enhancement mode
devices with a fixed source to drain separation, LSD, of 0.75µm.
The e-mode devices show higher performance due to lower
access resistance from the increased δ-doping level. The effect
of access resistance on fT resulting from the finite source to
drain separation is illustrated in Fig. 8 where the peak fT
decreases monotonically as a function of LSD for both depletion
and enhancement mode devices.. Figs. 9 and 10 show the DC
output and transfer characteristics of the enhancement mode
devices which show the ION-IOFF ratio limited by the reverse
Fig. 5 Sub-threshold slope as a function of gate length for depletion and
enhancement mode InSb QWFETs
Cut-off Frequency, fT [GHz]
Fig. 3 ID-VG transfer characteristics of 130nm LG depletion mode and
enhancement mode InSb QWFETs
LG = 85 nm
300
250
200
150
100
Enhancement mode
50
Depletion mode
0
0
Gate Length, LG [nm]
Fig. 4 Threshold voltage roll-off as a function of gate length for depletion
and enhancement mode InSb QWFETs
0.5
1
1.5
2
2.5
Source Drain Separation, LSD [nm]
Fig. 8 Peak fT as a function of source drain separation, LSD, for 85nm LG
depletion and enhancement mode InSb QWFETs at 0.5V VDS
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0.00
2.0E-06
0.25
-0.02
0.20
-0.03
0.15
0.10
-0.04
0.05
0.00
1.8E-06
0.1
0.2
0.3
0.4
Drain Voltage, VDS [V]
1.4E-06
1.2E-06
1.0E-06
0.5
1000
800
600
1.E-02
400
1.E-03
200
1.E-04
-0.2
0
0
0.2
C/A
(F) 1M
1 MHz
C/A
(F)kHz
500k
500
0.4
Gate Voltage, VG [V]
Fig. 10 Transfer characteristics of 85nm LG e-mode InSb QWFET with
LSD=0.75 µm (VDS=0.5 and 0.05V)
biased Schottky gate leakage. Scaled, high-performance InSb
QWFETs with reduced gate leakage are required for future low
power logic applications and could be achieved using an ultrathin metal gate/high-k dielectric stack [3].
-0.5
0
0.5
1
Gate Voltage, VG [V]
Fig. 11 Room temperature C-V characteristics of Al/Al2O3/AlInSb/InSb
MOSCAP with surface pre-treatment A
9.0E-07
1.0E-06
8.0E-07
Capacitance [F/cm²]
1200
DC Transconductance, Gm
(uS/um)
Drain and Gate Current (mA/um)
1.E-01
VDS=0.5, 0.05V
2 MHz
C/A
(F) 2M
-1
gate step (V) =0.13 fro m 0.5 to -0.41
Drain Current
Gate Current
Gm
C/A
(F) 5M
5 MHz
6.0E-07
2.0E-07
Fig. 9 Output characteristics of 85nm LG e-mode InSb QWFET with
LSD=0.75 µm (VGS=0.5V to -0.41V in 0.13V steps)
1.E+00
Pretreatment A
8.0E-07
4.0E-07
-0.05
0
1.6E-06
Capacitance [F/cm²]
0.30
-0.01
Capacitance [F/cm²]
Drain
Gate
0.35
Gate Current, IG (mA/um)
Drain Current, ID [mA/um]
0.40
9.0E-07
8.0E-07
7.0E-07
6.0E-07
5.0E-07
4.0E-07
3.0E-07
2.0E-07
7.0E-07
-1
-0.5
0
0.5
Gate Voltage, VG [V]
1
6.0E-07
5.0E-07
Pretreatment B
4.0E-07
5 MHz
C/A
(F) 5M
C/A
(F) 2M
2 MHz
3.0E-07
C/A
(F) 1M
1 MHz
500
kHz
C/A
(F)
500k
2.0E-07
-1
-0.5
0
0.5
Gate Voltage, VG [V]
1
Fig. 12 Room temperature C-V characteristics of Al/Al2O3/AlInSb/InSb
MOSCAP with surface pretreatment B
High-K Gate Dielectric on AlInSb/InSb
In the past 25 years of digital III-V technology, the lack of a
high quality native oxide coupled with the limited barrier
height of Schottky metal gate from surface Fermi level
pinning, has posed serious challenges for III-V based DCFL
implementation. We report, for the first time, promising results
on high-k dielectric development on AlInSb/InSb device
layers. Figs. 11 and 12 show the effect of two cases of AlInSb
surface pre-treatment on the room temperature C-V frequency
dispersion characteristics of high-k/metal gate stack on
AlInSb/InSb. The high-k dielectric, in this case, is Al2O3
(alumina) deposited using a low temperature atomic layer
deposition (ALD) process. XPS results indicate that the surface
pre-treatment A oxidizes the AlInSb surface forming indium
oxide, which results in a high density of interface states. The
surface pre-treatment B mitigates the oxidation process,
resulting in much reduced frequency dispersion in the
accumulation region. The frequency dispersion in the inversion
region is a combination of a) minority carrier generation in low
bandgap AlInSb/InSb material system and b) the
generation/recombination from the surface traps. The room
temperature C-V characteristics with the more optimized
process exhibits a moderate level of hysteresis, as shown in the
Fig. 13 Room temperature gate to channel leakage characteristics for ALD
Al2O3 high-k dielectric and Al metal gate stack on AlInSb/InSb device layers
showing four orders of magnitude reduction in leakage compared to Schottky
metal gate
inset of Fig. 12, which is believed to be from elemental
antimony acting as hole traps [4]. The high-k/metal gate stack
results in four orders of magnitude reduction in the gate
leakage current compared to the Schottky metal gate stack
(Fig. 13).
Summary
At this early stage of development, 85nm LG enhancement
mode InSb QWFETs show 50% higher intrinsic switching
frequency and a simultaneous 10× reduction in DC power
dissipation compared to the advanced Si MOSFETs (Fig 14).
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Fig. 15 plots the intrinsic gate delay (CV/I) vs. gate length
trend of InSb QWFETs benchmarked against the historical and
future Si nMOS transistor scaling trend. It shows that, for a
given physical gate length, the InSb devices offer 2.8×
reduction in gate delay. Fig. 16 shows that for a given physical
gate length, the InSb devices also offer more than an order of
magnitude improvement in the energy-delay product over the
Si transistors. For the first time, we have demonstrated high
performance enhancement and depletion mode InSb QWFETs
with record fT of 305 and 256 GHz, respectively, at VDS =
0.5V and scalability down to 85nm LG.
Cut-off Frequency, fT [GHz]
350
References
(1) T. Ashley et al,. Proc. 7th Intl. Solid State and Integrated Circuits Tech.
Conf., Beijing, China, pp. 2253-2256, 2004
(2) T. Ashley et al., Proc. 2005 International Conference on Compound
Semiconductor Manufacturing Technology, New Orleans, 2005
(3) R. Chau et al, IEEE Transactions on Nanotechnology, pp 153-158, 2005
(4) Z. Calahorra et al., J. Vac. Sc. Tech. B, pp 1195-1202, 1986
InSb E-mode QWFET (LG = 85nm)
VDS = 0.3V, 0.5V, 0.6V
300
250
200
150
100
Silicon MOSFET (LG = 60nm)
VDS = 0.5V, 0.7V, 0.9V, 1.2V
50
10
100
1000
DC Power Dissipation [µW/µm]
Fig. 14 Measured fT vs DC power dissipation (normalized to the transistor
width) for 85nm LG InSb QWFETs and 60nm LG silicon nMOS transistors
Intrinsic Gate Delay, CV/I [ps]
100
Si MOSFETs
Enhancement mode InSb
Depletion mode InSb
10
20
1
0.1
1
10
100
1000
10000
Gate Length, LG [nm]
Energy x Delay / Width [Js/m]
Fig. 15 Transistor Gate delay (CV/I) versus gate length for InSb QWFETs at
VDS = 0.5V benchmarked against state-of-the-art silicon nM OS transistors
1E-17
Si MOSFETs
1E-18
Depletion mode InSb
Enhancement InSb
1E-19
1E-20
1E-21
1E-22
1E-23
1
10
100
1000
10000
Gate Length LG [nm]
Fig. 16 Transistor Energy-Gate delay product (CV/I) versus gate length for
InSb QWFETs at VDS = 0.5V benchmarked against state-of-the-art silicon
nM OS transistors
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