DECENTRALIZED MULTI STRING PV SYSTEM WITH INTEGRATED ZVT CELL
RAFAEL C. BELTRAME, MATHEUS I. DESCONZI, HÉLIO L. HEY
Power Electronics and Control Research Group, Federal University of Santa Maria
97105-900, Santa Maria, RS, BRAZIL
E-mails: beltrame@mail.ufsm.br, matheusiensen@gmail.com, hey@smail.ufsm.br
MÁRIO L. DA SILVA MARTINS, HELDER T. CAMARA
Power Analysis and Processing Research Group, Federal University of Technology – Parana
85503-390, Pato Branco, PR, BRAZIL
E-mails: mlucio@utfpr.edu.br, contato@htc.eng.br
Abstract⎯ This paper exploits the advantages and limitations of using a cascaded connection of DC-DC step-up stages for a series string of PV panels, in a single-phase residential/commercial grid connected installation. It is demonstrated that when multistring PV systems are adopted in order to minimize shadowing problems, it is required to employ some approach to reduce the
switching losses (turn-on losses of MOSFETs and diode reverse recovery losses) of the DC-DC step-up stages. As a multi-string
PV system is normally comprised by several DC-DC step-up stages, integrated soft-switching topologies are attractive due to
their compactness, reliability and low cost. Thus, this work proposes the use of an integrated ZVT cell, which assists all the DCDC step-up stages and employs a very compact circuit, enabling to minimize the switching losses, improving the system efficiency. The proposed cell makes use of a magnetically-coupled auxiliary voltage source implemented by adding a secondary
winding on the input inductors. In order to validate the proposed topology, experimental results are presented.
Keywords⎯ Multi-string PV system, DC-DC step up converter, zero-voltage-transition.
1
Introduction
Recent advances in power electronics and semiconductor technology associated with favorable incentives, such as low-interest loans and tax incentives, has led to growth of the PV market mostly due
to the proliferation of grid connected PV systems,
Cory (2008). PV systems connected to the utility do
not require back-up system and charge regulator, i.e.,
they are commonly simpler, cheaper and more reliable when compared to a stand alone one.
Nonetheless, the wide utilization of PV is still
limited by the initial installation cost. Likewise other
intermittent renewable sources, to optimize the PV
array area and make the implantation of grid connected PV systems economically viable, it is essential to drain the maximum power produced by the PV
array. It can be done by means of a maximum power
point track algorithm, Femia (2005) and Yu (2002),
commonly applied to the front-end DC-DC stage.
Indeed, PV modules cannot produce identical
energy levels in a PV array for several reasons, including dissimilarities of panel production, different
temperatures and irradiations due to panel orientation, aging and, in some cases, shading, Carannante
(2009). As the PV panels in a series string are constrained to all conduct the same current, the least
efficient panel sets the string current. In long string
arrays, this situation results in the lost of the maximum power point of the array, which reduces the
overall efficiency of the array and, in extreme cases,
it can also cause the degeneration of the panels due
to the hot spot phenomenon. To overwhelm these
problems, and also ensure the maximum production
of electricity even when shading or other dissimilarities are present, decentralized PV systems have been
proposed in the literature. Some works presented
demonstrate that a gain of up to 16% of generated
energy could be achieved on decentralized PV systems, Imhoff (2008).
In general, decentralized PV systems split the
maximum power point tracker (MPPT) stage, which
can be dedicated exclusively to a single or a group of
PV panels. They can be grouped in three categories,
namely module integrated systems, Meinhardt (1999),
and string and multi-string systems, Meinhardt (2001).
The current, voltage and power ratings of DC-DC
step-up MPPT semiconductors, as well as their voltage
gains are quite different for each decentralized system.
Depending on the semiconductor technology and the
required voltage gain, the conduction and switching
losses can be particularly distinct from one decentralized system DC-DC step-up stage to another.
As a multi-string PV system can be comprised
by several DC-DC step-up stages, to reduce the turnon losses of MOSFETs and diode reverse recovery
losses of all DC-DC stage is a quite complex task
since the auxiliary circuitry may increase significantly
the converter size, weight and cost. Additionally, a
large semiconductor count could reduce the reliability
of the PV system.
This paper exploits the advantages and limitations
of using a cascaded connection of DC-DC step-up
stages for a series string of PV panels, in a singlephase residential/commercial grid connected installation with an integrated soft-switching topology,
Schuch (2009). The proposed Zero-Voltage Transition ACC which assists all the DC-DC step-up stages
and employs a very compact circuit, enabling to
Table 1. Parameters for the Hypothetical Standard Module.
minimize both the turn-on losses of MOSFETs and
diode reverse recovery losses. In order to validate the
proposed topology theoretical analysis and experimental results are presented.
2
Loss Analysis of Multi-string
Grid-Connected PV System
Multi-string PV system combines the advantage of
higher energy yield of a string PV system with the lower
costs of a central inverter PV system, as shown in Figure
1, allowing the use of individual MPPT algorithm for
each one, Myrzik (2003), reducing the possibility of
shadowing mismatches that may occur in a single long
string PV module configuration. From the efficiency
perspective, the series connection of the DC-DC stages
reduces their voltage gain and, consequently, related
conduction losses. In addition, the DC-DC stage outputs
connected in series may provide a DC bus voltage that
matches directly with those used to feed standard inverter
stages.
Figure 2 shows the efficiency comparison of
multi-string PV systems with one, two, three and four
input DC-DC step-up stages. It can be seen the efficiency is proportional to the number of input stages.
It occurs because the larger the number of stages is,
the lower the input DC-DC converter gain is for the
same DC bus voltage (defined as 250 V), reducing
the RMS current through the transistor and the related conduction losses. Additionally, the switching
losses (turn-on losses of MOSFET and diode reverse
recovery losses) are minimized because the voltage
applied on semiconductor devices is reduced. For the
theoretical curve, the efficiency was estimated by using the loss models presented in Appendix A. To simplify the analysis, the systems make use of the Hypothetical Standard Module (HSM) specified in Table 1.
The step-up stage parameters and components are defined in Table 2. It is also considered that the step-up
stage is operating in the maximum power point (MPP)
of the PV arrays. A MOSFET is employed in step-up
converter because it allows the increase of the converter switching frequency, and associated volume,
weight and, mainly, cost reduction of the entire system. The MOSFET utilized were the N-Channel Standard Power MOSFET IRFP460 (500V/20A). The di-
Parameter
Value
VOC (ISC)
21.9 V (8.02 A)
Peak power voltage (current)
17.6 V (7.39 A)
Peak power (No. of panels of the array)
130 W (3)
Table 2. Parameters for the input DC-DC step-up stages.
Parameter
Value
Switching frequency, fs
100 kHz
Input filter inductor, L (N of turns)
285 μH (22 turns)
Ferrite core
NEE – 65/26
Maximum flux density, BMax
0.2 T
Copper wire
3 x 63 x 37 AWG (Litz)
Output capacitor, C
470 μF
Main switch (MOSFET)
IRFP460
Main diode
8ETH06
ode utilized was the Ultrafast Switching Mode Power
Rectifier 8ETH06 (600V/8A).
Also in Figure 2 experimental data from a laboratory prototype is depicted, it can be seen by the
plotted curves that the estimated losses presents a
good agreement with the data measured from the
laboratory prototype.
The distribution of the losses in the DC-DC
step-up semiconductors for a multi-string PV system
composed by two stages (93.6%, vide Figure 2) is
shown in Figure 3. It can be concluded that in the
MOSFET based PV system, the transistor turn-on
and turn-off losses represents about 23% of the
semiconductor losses, and the diode switching losses
represents 35%, confirming the importance in reducing switching losses.
3
Proposed Multi-String Grid-Connected PV
System with Integrated ZVT Cell
As the switching frequency of the step-up stages
increases, the large reverse-recovery currents of the
diodes affect the system efficiency and also produce
electromagnetic interference (EMI) noise. To overcome
96
Efficiency (%)
95
94
93
92
Experimental
91
Estimated
90
Figure 1. Decentralized multi-string PV system with a cascaded
connection of DC-DC step-up stages.
1
2
3
Number of Input Stages
4
Figure 2. Efficiency comparison of hard switched multi-string PV
system.
27%
35%
Trans. Cond.
Diode Swit.
Trans. T-on
6%
Trans. T-off
Diode Cond.
17%
14%
Figure 3. Semiconductor power loss balance in the PV system.
those problems, various passive, Tseng (2007), Li
(2009), and active approaches have been proposed for
the DC-DC step-up converter, Jovanovic (2005), Martins (2005) and Wang (2005). Among these techniques,
the zero-voltage-transition (ZVT) technique is especially suitable to overcome the aforementioned drawbacks because it reduces the diode reverse recovery
losses by controlling the di/dt slope of the current during the turn-off of the diode. Furthermore, it effectively
minimizes the switching losses and also promotes the
absorption of the parasitic capacitances energy of semiconductor devices, Martins (2004), minimizing the
turn-on capacitive losses when majority carrier devices
such as MOSFETs are employed.
There are several ways to implement the ZVT auxiliary commutation circuit (ACC), depending on how
the auxiliary voltage source of the ACC is synthesized.
In converters that present a filter inductor, as the DCDC step-up converter, an auxiliary voltage source implemented by a magnetic coupling with the inductor
filter, as proposed by Lee (1994), is advantageous because the voltage source is implemented in the same
magnetic core as the filter inductor, and the auxiliary
inductor can be implemented by means of the leakage
inductance of these inductors, Russi (2008). This way,
these features result in a very compact topology in that
there are no extra magnetic components.
3.1 The Integration Concept
The inclusion of ACCs increases the number of additional components, and therefore the cost and the complexity of the overall system. It is a critical problem for
systems with several power conversion stages, such as
decentralized PV multi-string systems, as can be seen in
Figure 1. In these systems, it would be necessary to include an independent ACC for each power conversion
stage, decreasing the usefulness of these circuits.
Aiming to reduce the number of additional auxiliary devices, the integration concept of ACCs can
be employed, which is suitable to systems with several power conversion stages. This concept is based
on sharing an ACC among different converters or
stages, aiming to reduce the number of additional
auxiliary devices, Schuch (2009).
Therefore, it is proposed the use of the unpublished integrated ZVT cell shown in Figure 4, which
employs a very compact circuit and can assist all the
DC-DC step-up stages. The proposed ACC makes use
of a magnetically-coupled auxiliary voltage source
implemented by adding a secondary winding on the
input inductors. As the ACC is galvanic isolated from
the main power circuit, it can be shared by all the DCDC step-up converters with none short-circuit risk.
The ZVT cell presented in Figure 4 makes possible to minimize diode reverse recovery losses of D1
to Dn by controlling the di/dt slope of their currents
and to assist the turn-on of S1 to Sn simply by using a
phase difference of 360º n among their command
signals, where n is the number of DC-DC step-up
stages, or by synchronizing their turn-on instants.
3.2 Integrated ZVT Cell Operation
In order to explain the ACC operation, for simplicity it is considered only one DC-DC step-up converter, as presented in Figure 5, where the coupledinductor was replaced by its cantilever model, Maksimovic (2000). Furthermore, the input inductor (L1)
was approximated by a constant current source (IL1).
This approximation can be made if the magnetizing
inductance of the coupled-inductor (Lm) is much larger than the leakage inductance (Lx) and the ripple of
the current through L in a switching period is small.
Mode 1 ( t ≤ t0 ) : previous to the ACC operation,
S is turned off and D1 is conducting IL1, as presented
in Figure 5 (a) and in Figure 6 for t ≤ t0 . During this
mode, the voltage on Cs1 (vS1) and the current
through Lx (iLx) are Vo1 and zero, respectively.
Mode 2
( t0 < t ≤ t1 ) :
aiming to commutate IL1
from D1 to S1, the auxiliary switch Sx is turned on at
“t0”. The circuit configuration during this mode is
represented in Figure 5 (b) and the main theoretical
waveforms in Figure 6 for t0 < t ≤ t1 . The voltage on
Cs1 is Vo1 and the current though Lx increases linearly
with a slope given by N (Vo1 − Vi1 ) Lx . It is important to notice that the turns ratio (N) must be positive
in order to apply a positive voltage on Lx. This mode
ends at “t1”, when NiLx(t) reaches IL1 and D1 turns off
with a controlled di/dt slope. The time duration of this
mode, defined as Δt1 = t1 − t0 , can be calculated by (1).
PV string
Vin
Dxn
N
Lin
CSx N
Li1
Ci1
a1
S1
Dn
Csn Con
Sn
Vi1
Dx1
Sx
Cin
an
Von
VBUS
D1
Cs1 Co1
Vo1
Figure 4. Proposed multi-string PV system with integrated ZVT.
Δt1 =
Lx I L1
N (Vo1 − Vi1 )
Where
(1)
2
ωn =
Mode 3 ( t1 < t ≤ t2 ) : this mode begins at “t1”, when
D1 turns off, and both Cs1 and Lx go to a resonant process.
The circuit configuration during this mode is represented
in Figure 5 (c) and the main theoretical waveforms in
Figure 6 for t1 < t ≤ t2 . The voltage on Cs1 goes zero
during the resonant process. The current peak though Lx
can be calculated by (2).
Vo1 − Vi1 I L1
+
Z
N
iLx ( max ) =
(2)
Where
Z=
Lx
.
Cs1
(3)
(4)
This mode ends at “t2”, when vS1(t) reduces to
zero and is clamped by the antiparallel diode of S1.
Thus, the time duration of this stage, defined as
Δt2 = t2 − t1 , can be calculated by (5).
Δt2 =
⎛ Vi1 ⎞
arccos ⎜
⎟
ωn
⎝ Vi1 − Vo1 ⎠
1
Dx1
Lx
iLx
NvL1
CSx vSx
Sx
IL1
vL1
~ ~
Vo1 Vi1
Dx1
Nv
iLxL1
NiLx
CSx vSx
~
L1
iD1
Vo1 Vi1
~ ~
vL1
Cs1 vS1
S1
(e) Mode 5t ( tt3 < t ≤
t tt4 ) .t
0
1
2
3
4
~
a1
iS1I
~
D1
Lx
NvL1
NiLxIL1/N
a1
iL IL1
vL1
S1
IL1
Vo1 Vi1
7
Lx
Lx
iLx
IL1
vL1
CSx vSx
Sx
NiLx
D1
Cs1 vS1
S1
a1
Vo1 Vi1
IL1
vL1
D1
Cs1 vS1
S1
Vo1
(d) Mode 4 ( t2 < t ≤ t3 ) .
Dx1
CSx vSx
Sx
Lx
S1
iLx
NvL1
NiLx
a1
Vo1 Vi1
iLx
NvL1
NiLx
IL1
vL1
NvL1
D1
t
t
6
CSx vSx
Sx
(c) Mode 3 ( t1 < t ≤ t2 ) .
t
(f)t Mode
t t 6 ( t4 < t ≤ t5 ) .
5
iLx
Dx1
Cts1 vS1
(8)
Dx1
a1
Vo1
t
iLx2NS(xVo1-V
Ci1Sx) vSx
Lx
Vo1 − Vi1
I
sin (ωn Δt2 ) + L1 .
Z
N
suming gradually IL1, the circuit goes to the configuration represented in Figure 5 (e). The circuit operation
is similar to that in the previous mode. The main theoretical waveforms are presented in Figure 6 for
t3 < t ≤ t4 . This mode ends at “t4”, when iLx(t) reduces
to zero and Dx1 turns off under a controlled di/dt slope.
It is important to highlight that after the turn-off of Dx1,
Sx can be turned off under zero-current-switching
(ZCS). Thus, an IGBT can be employed as auxiliary
D1
Cs1 vS1
t
(7)
N 2 Vi1
Mode 5 ( t3 < t ≤ t4 ) : at “t3”, when S1 starts as-
NvL1
S1
Dx1
~
Sx
Vi1
iLx ( t2 ) =
(b) Mode 2 ( t0 < t ≤t t1 ) .
~
Mode 1 ( t ≤ t0 ) .
v(a)
S1
Lx ( N iLx ( t2 ) − I L1 )
Where
NiLx
a1
Cs1 vS1
S1
Lx vSxiLx
CSx vSx
D1
GS1IL1
GSx
Δt3 =
Dx1
Sx
NvL1
NiLx
vL1
iLx
Lx
(6)
“t2”, the antiparallel diode of S1 stars conducting, as
presented in Figure 5 (d). The voltage on Cs1 remains
clamped at zero volts and the current though Lx decreases linearly with a slope given by − NVi1 Lx . It
is important to notice that N must be positive in order
to apply a negative voltage over Lx. The main theoretical waveforms are presented in Figure 6 for
t2 < t ≤ t3 . This mode ends at “t3”, when NiLx(t) reduces under IL1 and S1 starts assuming gradually IL1.
The time duration of this mode, defined as
Δt3 = t3 − t2 , can be calculated by (7).
Dx1
a1
Vi1
(5)
.
Mode 4 ( t2 < t ≤ t3 ) : after vS1(t) reaching zero at
In order to achieve the zero-voltage-switching
(ZVS) condition to S1, it is mandatory that vS1(t) reduces to zero volts. It can be demonstrated that the
restriction (4) must be observed in order to satisfy
the aforementioned ZVS condition. The restriction
(4) implies that the converter gain must be always
higher than two.
Vo1
≥2
Vi1
N
Lx Cs1
NiLx
D1
Cs1 vS1
CSx vSx
Sx
a1
Vo1 Vi1
(g) Mode 7 ( t5 < t ≤ t6 ) .
Figure
Single DC-DC
step-up stage with ZVT cell operation modes.
Figure 6. Theoretical waveforms
of the5.proposed
topology.
IL1
vL1
S1
D1
Cs1 vS1
(h) Mode 8 ( t6 < t ≤ t7 ) .
Vo1
switch. The time duration of this mode, defined as
Δt4 = t4 − t3 , can be calculated by (9).
Δt4 =
Lx I L1
N 2 Vi1
turns to the configuration of Figure 5 (a) (mode 1). The
voltage over Sx at “t7” has the level expressed in (11).
vSx ( t7 ) = 2 N (Vo1 − Vi1 )
(9)
4
Mode 6 ( t4 < t ≤ t5 ) : after Dx1 turning off at “t4”,
S1 conducts IL1. Thus, vS1(t) and iLx(t) are both zero.
During this mode, represented in Figure 5 (f), the
PWM modulation is implemented. This mode ends at
“t5”, when S1 is turned off. The main theoretical
waveforms are presented in Figure 6 for t4 < t ≤ t5 .
Mode 7 ( t5 < t ≤ t6 ) : this mode begins at “t5”, when
S1 is turned off and IL1 is transferred to the snubber capacitor Cs1. This way, Cs1 is charged linearly with a slope
given by I L1 Cs1 . The circuit configuration during this
mode is represented in Figure 5 (g) and the main theoretical waveforms are presented in Figure 6 for
t5 < t ≤ t6 . This stage ends at “t6”, when vS 1 ( t ) = Vo1
and D1 starts conducting IL1, clamping vS1(t) at Vo1. Additionally, the time duration of this mode, defined as
Δt5 = t6 − t5 , can be calculated by (10)
C V
Δt5 = s1 o1
I L1
Design Methodology
The design methodology for the auxiliary ZVT
circuit is based on the selection of Lx and N in order
to satisfy the restrictions that guarantee the proper
ACC operation and also limit the voltage and current stresses in the DC-DC step-up stage semiconductor devices.
4.1 Selection of N
As mentioned during the analysis of the operation modes 2 and 4, N must be positive in order to
guarantee the magnetizing and demagnetizing conditions to Lx, as expressed in (12). Furthermore, in order to comply with the maximum voltages of Dx1
(vDx(max)) and Sx (vSx(max)), which occur during mode 1,
(13) and (14) must be satisfied.
N ( min )
(10)
N ( max )
Mode 8 ( t6 < t ≤ t7 ) : this mode only exists due to
the intrinsic capacitance of Sx (CSx). In the following
analysis, it is assumed that the linear charge of Cs1
(snubber commutation) was finished. Thus, the voltage
applied over L1 is Vi1 − Vo1 at “t6”. This voltage, reflected to the ACC side, turns Dx1 on and enables Lx
and CSx to start a resonant process. The circuit configuration during this mode is represented in Figure 5 (h)
and the main theoretical waveforms in Figure 6 for
t6 < t ≤ t7 . This mode ends at “t7”, when iLx(t) reduces
to zero and is Dx1 turned off. This way, the circuit re-
~ ~
GS1
t
~
GSx
Vo1
~
vS1
vSx
~
~
iLx
2N(Vo1-Vi1)
~ ~
iS1
IL1
t0 t 1
t 2 t3 t4
t5 t6 t 7
Figure 6. Theoretical waveforms of the proposed topology.
N ( max )
Mag
= N ( min )
vSx ( max )
=
>0
(12)
vSx ( max )
(13)
2 (Vo1 − Vi1 )
=
vDx ( max )
Des
vDx ( max )
(14)
(Vo1 − Vi1 )
4.2 Selection of Lx
The minimum value of Lx that comply with the
maximum di/dt slope during the turn off of D1
(di/dtD) can be calculated from (1), as expressed in
(15). In the same way, the minimum value of Lx that
comply with the di/dt slope of Dx1 (di/dtDx) can be
calculated by (16).
Furthermore, the minimum value of Lx that limits
iLx(max) to the levels of auxiliary semiconductor devices
(iACC(max)) can be calculated by (17). On the other hand,
the maximum value of Lx that guarantees that the magnetization time will not be larger than a fraction of the
switching time (∆t1(max)), offsetting the duty cycle of
the converter, can be calculated by (18).
Lx ( min )
t
didt D
Lx ( min )
t
=
N 2 (Vo1 − Vi1 )
didt Dx
(15)
didtD
=
N Vi1
didtDx
(16)
2
t
iL
~
iD1
IL1/N
t
(11)
t
t
Lx ( min )
iLx ( max )
Lx ( max )
⎛
⎞
Vo1 − Vi1
=⎜
⎟⎟ Cs1
⎜i
⎝ ACC ( max ) − I L1 N ⎠
Δt1( max )
=
N 2 (Vo1 − Vi1 ) Δt1( max )
I L1
(17)
(18)
4.3 Design Abacus
It is possible to find a set of N and Lx combinations that comply with the specifications of the con-
Table 3. Converter specification and semiconductor limitations.
Table 4. Semiconductor devices and ACC specifications.
Parameter
Value
Parameter
Value
Note
Input power (Pin)
390 W
Main switch (S1)
IRFP460
Discrete MOSFET
Main diode (D1)
8ETH06
Discrete Diode
Switching frequency (fs)
100 kHz
Input voltage (Vi1) / Output voltage (Vo1)
52.8 V / 250 V
Maximum voltage over Sx (vSx(max)) / Dx (vDx(max)) 480 V / 480 V
Auxiliary switch (Sx) IRG4BC20UD
Discrete IGBT
Auxiliary diode (Dx1)
Discrete Diode
8ETH06
Maximum current through the ACC (iACC(max))
13 A
Ferrite core
NEE – 65/26
–
Maximum di/dt though D (di/dtD) and Dx1 (di/dtDx)
100 A/μs
Cooper Wire
63 x 37 AWG
Litz
Snubber capacitor (Cs1) - COSS
480 pF
Input inductor (L1)
285μH
–
Auxiliary inductor (Lx)
7.1μH
Leakage
1.21
N (pri) = 22 x 3
N (sec) = 27 x 1
verter and the limitations (maximum voltages and currents) of the semiconductor devices. Thus, the restrictions (12) to (18) are plotted in Figure 7 using the
specifications summarized in Table 3. This way, from
Figure 7 was selected Lx = 7.1μH and N = 1.21 in
order to satisfy the restrictions defined in Table 3.
5
System Implementation and
Experimental Results
In order to verify the reliability of the proposed
system, an experimental analysis is carried out for a
single DC-DC step-up converter employing the integrated ZVT cell presented in Figure 4. The semiconductors employed in the prototype are summarized in
Table 4, as well as some additional ACC specifications.
For this analysis the PV panels were emulated by a
constant voltage source with a voltage level equal to the
MPP voltage, and the MPP current was drained from
the voltage source by adjusting the DC-DC step-up
converter duty-cycle.
Figure 8 presents the experimental waveforms of
the converter operating at nominal power. In Figure 8
(a)-(b) are presented the stead-state waveforms of the
command signals of both main (vGS1(t)) and auxiliary
switches (vGSx(t)), as well as their voltage (vS1(t) and
vSx1(t), respectively), and the current through the auxiliary inductor (iLx(t)). It is possible to see in Figure 8
(a)-(b) that the ACC intervention demands a small
portion of the switching period. It must be noted that
the linear rising of iLx(t) (with di/dt controlled by Lx)
corresponds to a linear falling of the current though
Auxiliary Inductor, Lx (μH)
15
Turns ratio (N)
D1, reducing its reverse recovery losses. It is possible
to see in Figure 8 (b) that Sx1 is turned off after iLx(t)
reaching zero, characterizing a ZCS commutation.
Furthermore, Figure 8 (c) presents the details of
the turn-on commutation of S1. As can be seen in Figure 8 (c), the main switch S1 is turned on after vs1(t)
vS1
1
iLx
3
Ch1: 100 V/div
Ch3: 5 A/div
vGSx
4
vSx
1
iLx
3
Ch1: 100 V/div
Ch3: 5 A/div
vGS1
Des
10
Time: 2 us/div
Ch4: 20 V/div
(b)
vSx(max)
Mag
Time: 2 us/div
Ch4: 20 V/div
(a)
Δt1(max)
12.5
vGS1
4
4
iACC(max)
di/dtD
ZVS
vS1
vDx(max)
7.5
Project
1
5
2.5
0
iLx
di/dtDx
0
0.5
1
1.5
2
Turns Ratio, N
Figure 7. Design abacus.
3
2.5
3
Ch1: 100 V/div
Ch3: 5 A/div
Time: 500 ns/div
Ch4: 20 V/div
(c)
Figure 8. Experimental results. (a) Main circuit in stead-state operation. (b) Auxiliary circuit in stead-state operation. (c) ZVS
commutation detail.
retical and experimentally. A design procedure to determine its auxiliary components have been presented
and discussed. The proposed topology was validated
by experimental results obtained from a single DCDC step-up converter operating at 390 W and 100
kHz. The experimental results proved the effectiveness of the converter.
94.5
Efficiency (%)
94
93.5
93
92.5
Soft-Switched
92
91.5
200
Appendix A
Hard-Switched
250
300
350
M PP Power (W)
400
Figure 9. Converter efficiency in function of solar irradiation. In a
range from 600 to 1000 W/m2.
reaches zero, characterizing a ZVS commutation.
Figure 9 shows the measured efficiency of the
DC-DC step-up prototypes evaluated experimentally
as a function of PV modules power for a set of irradiances defined a priori. It can be observed that the efficiencies are inversely proportional to the PV module
power, since the conduction losses increase with the
module current. In spite of it, the Integrated ZVT DCDC prototype presented higher efficiency for the entire
module power range. The real efficiency gain of the
ZVT DC-DC prototype can be seen in Figure 10.
6
Conclusions
This paper presented and analyses an integrated
ZVT ACC that uses a magnetically-coupled auxiliary
voltage source implemented by adding a secondary
winding on the input inductors. The proposed ACC
assists all the DC-DC step-up converters of a decentralized multi-string PV system employing a very compact circuit, reducing the cost and size of the overall
system, and improving its performance by reducing
the turn-on capacitive losses of the main switches and
the diode reverse recovery losses. Thus, the benefits of
using multi-string PV systems, such as reducing the
possibility of shadowing mismatches and increasing the
generated energy are kept without penalizing the
system reliability and cost.
The proposed integrated ZVT was analyzed theo-
The forward voltage drop on both main transistor
and main diode can be estimated by (19), where the coefficients A, B and C, summarized in Table 5, can be obtained using the data extracted from the device datasheet,
and idev is the instantaneous current through the device.
vdev ( idev ) = A idev B + C
This way, the transistor and diode conduction
losses can be calculated by (20), where Ts is the
switching period, Beltrame (2009).
Pcnd =
1
Ts
Ts
∫ v ( i ) i ( t ) dt
dev
dev
dev
(20)
0
The transistor switching losses can be divided in
turn-on and turn-off losses. The turn-on losses are composed by the overlap between the voltage and current
though the transistor, McMurray (1980), and by the turnon capacitive losses, Beltrame (2009). On the other
hand, the turn-off losses are mainly due to the overlap
between the voltage and current. Thus, the turn-on capacitive losses can be calculated by (21), where Vo is
the output voltage of the DC-DC step-up converter.
Additionally, the turn-off losses can be calculated by
(22). The parameters Coss, tf and tr are defined in Table
5.
Pon =
1
1
idevVo tr f s + CossVo 2 f s
2
2
(21)
1
idevVo t f f s
(22)
2
The switching losses of the diode are basically due
to the reverse recovery phenomenon. Then, the switching
losses of the diode can be estimated by (23), Schönberger
(2008), where Qrr is defined in Table 5.
Poff =
Prr = QrrVo
Efficiency Gain
0,4
0,35
0,3
0,25
0,2
0,15
0,1
0,05
0
(19)
(23)
Finally, the losses observed in the inductor can be
estimated by (24), where ILrms is the RMS current though
the inductor and RL is the DC resistance of the cooper
wire. It is important to notice that only the cooper losses
Table 5. Parameters employed to estimate the converter losses.
Device
600
700
800
900
1000
Irradiation
Figure 10. Integrated ZVT efficiency gain in function of the irradiation in W/m2.
Main switch
(IRGP460)
Parameter
Value
A; B; C
0.083; 1.380; 0.557
Coss
480 pF
tr; tf
81 ns; 65 ns
Main diode
(8ETH06)
A; B; C
0.969; 0.291; 0.235
Qrr
115 nC
Inductor
RL
39.61 mΩ
were take into account to calculate the inductor losses.
PL = I Lrms 2 RL
(24)
Acknowledgment
The authors would like to express their gratitude
to “Coordenação de Aperfeiçoamento de Pessoal de
Nível Superior – CAPES” and “Conselho Nacional de
Desenvolvimento Científico e Tecnológico – CNPQ”
(proc. nº 307798/2009-7 and proc. nº 478154/2009-7)
for financial support.
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