Development of the input circuit for
GOSSIP vertex detector
in 0.13 μm CMOS technology.
Vladimir Gromov,
Ruud Kluit, Harry van der Graaf.
NIKHEF, Amsterdam,
The Netherlands.
September 28, 2006.
1
Outline
ƒ GOSSIP detector: principles of operation and
features.
ƒ Inputs and requirements for the design of the
input circuit.
ƒ The prototype of the input circuit.
ƒ Conclusions and plans.
2
GOSSIP detector: principles of operation.
Gas On Slimmed Silicon Pixel (GOSSIP) is a vertex detector combining a
thin gas layer as signal generator with a CMOS readout pixel array.
Cathode (drift) plane
Cluster1
Cluster2
1 mm,
400 V
Cluster3
Integrated Grid (InGrid)
Z
50 μm,
400 V
Input pixel
Slimmed Silicon Readout chip
Y
X
50 μm
- projection of the track.
- 3D reconstruction of the track. .
3
GOSSIP detector: main features.
Hybrid pixel detector.
Silicon sensor.
Thickness is 250 μm .
GOSSIP detector.
Chip pixel unit cell
with bump bonding.
Cathode foil.
Thickness is 1 μm .
Integrated grid (InGrid)
Thickness is 1 um .
Chip pixel unit cell.
Readout chip.
CONTRA
- spark protection
Slimmed (polished) readout chip.
Thickness is 50 μm .
PRO
-can operate up to fluences of 1016 cm-2
-low material budget
-negligible detector leakage current
-low detector parasitic capacitance 4
Inputs and requirements for the design of the input circuit.
Single electron efficiency.
1
Gain = 8000
0.9
0.8
Gain = 4000
0.7
- the low-threshold operation
(THR < 400 e) is required.
0.6
Gain = 2000
0.5
0
500
1000
1500
2000
Threshold, electrons
Shape of the detector current.
i(t)
ion component
electron
component
- motion of ions mainly
determines the detector
current.
5 - 30 ns
5
Inputs and requirements for the design of the readout circuit.
Single electron drift time measurements
(simulations)
- time resolution
σtime walk = 2 ns (100 μm) .
Entries
Gain = 8000
Gain = 4000
Gain = 2000
0
2ns
4ns
6ns
8ns
Measured drift time
10ns
12ns
14ns
Power consumption.
Analog:
Total:
low power dissipation
2 μW / pixel.
100 mW / cm2 or 200 mW / chip.
reduction of the material budget .
6
Inputs and requirements for the design of the readout circuit.
-the high sensitive analog circuit must
be effectively isolated from the high
speed switching lines.
Analog-digital crosstalk.
Pixel pitch and the chip size.
25
μm
55
·
ls
ix e
p
6
4c
=1.
256
m
pix
els
·
- pixel pitch 55 μm x 55 μm .
55
μm
=1.
4c
m
- sensitive area a matrix of
256 x 256 pixels ( 1.98 cm2).
Readout chip
55
μm
7
The prototype of the input circuit.
Parasitic capacitance at the input of the front-end circuit .
Power
Consumption
Noise
Cdet
Speed
Cdet= Cpar = Cp-grid + Cp-p + Cp-sub
,
where
Cp-sub is pad-to-substrate capacitance
Cp-grid is pad-to-InGrid capacitance
Cp-p is pad-to-pad capacitance
InGrid
Cp-grid
Cp-p
Substrate
Input pad
Cp-grid
Cp-grid
Cp-p
Cp-sub
8
The prototype of the input circuit.
Evaluation of the input parasitic capacitances in 0.13 μm CMOS technology .
Pad-to-pad
capacitance (Cp-p).
Pad-to-InGrid
capacitance (Cp-grid).
2.5
2
2
1.5
1.5
Cp-p,fF
Cp-InGrid,fF
1
0.5
0.5
0
1
0
5
10
15
00
20
pad-to-pad distance, μm
10
20
30
40
50
size of the pad, μm
Pad-to-substrate capacitance (Cp-sub).
60
50
40
Cp-sub, fF
30
- input parasitic capacitance
≈ 10 fF.
20
10
0
0
10
20
30
40
size of the pad, μm
50
9
The prototype of the input circuit.
Gain in the charge-sensitive preamplifier with a very low parasitic
capacitance at the input (Cpar → 10 fF) .
Cfb
Charge-to-voltage gain ≈
Qin
Iin(t)
Rfb
Cpar
A
Output
Open loop voltage gain
of the OPAMP
F
0f
1
≈
1
Cfb
Cpar
Cfb >>
A ≈1
30
Coaxial-like layout of the input
interconnection.
Input pad
Cpar = 10 fF…50 fF
LM
M6
Ground plane
Cfb = 1fF ???
Ground
M3
Output
M2
Cfb=1 fF
- Stability ?
- Physical layout ?
M1
Substrate
Parasitic metal-to-metal
fringe capacitance.
10
The prototype of the input circuit.
Stability of the charge-sensitive preamplifier with a very low parasitic
capacitance at the input (Cpar → 10 fF).
- The scheme of F.Krummenacher
Silicon
sensor
no need for the leakage
current compensation
2Ip
Cfb
Cfb=1 fF
Output
Ileak > 1 μA
Output
Input
Cpar
Cpar
Iconst
Ileak + Ip
Cint
Ip
- This circuit becomes unstable when
Cpar → 10 fF
- This circuit demonstrates a safe phase margin
even when
Cpar → 10 fF
11
The prototype of the input circuit.
DC feedback in the charge-sensitive preamplifier.
Virtual resistor Rfb = 80 MΩ
Input
Output
Vdd=1.2 V
M3
M4
M2
M1
Vb1
- allows for discharging of the feedback capacitor.
Rfb = 1/gmM1 + 1/gmM2 = 80 MΩ
M5
Ib=1 nA
Cfb =1 fF
- biases the input of the circuit.
Output
Input
Statistical spread of the offset at the output
σ(δUoutDC) = 20 mV (170 e-).
Vb2
M8
M6
M9
M7
12
The prototype of the input circuit.
The operational amplifier.
Output
Input
OPAMP
Vdd=1.2V
M5
M6
M7
Output
M3
Transfer function
Uout / Uin = A(jω)= Ao/(1+jωτ) = 130/(1+jω●14 ns)
Ib2=0.2 μA
M4
Vb3
Input
M1
M2
Bias current
Ib1+Ib2=1 μA + 0.2 μA =1.2 μA
Vb2
Ib1=1 μA
Power dissipation
P=1.2 V ● 1.2 μA = 1.5 μW
13
The prototype of the input circuit.
Pulse response and noise.
Cfb = 1fF
Qin
Iin(t)
Rfb = 80 MΩ
Output
Cpar
Ib1=1 μA
A(jω)=Ao/(1+j●ω●τo)
δ-pulse response of the preamplifier
3 ● τo
Peaking time =
1+
Ao ● Cfb
-
response peaking time is
5 ns…30 ns.
≈ 5 ns … 30 ns ∝ Cpar
Cpar + Cfb
450
Amplitude =
440
Qin
Cfb
●
1+
1
Cpar + Cfb
Ao ● Cfb
430
U, mV
Decay of the signal is
t
exp
Rfb ● Cfb
420
410
400
100
150
200
250
Time, ns
300
350
ENC ≈ 60..80 e- (RMS)
even with low bias current (Ib1=1 μA)
and
fast peaking time.
14
The prototype of the input circuit.
Physical layout aspect.
Floating P-well for analog NFETs.
VDD_ana
Guard rings
GND_ana
Digital N-type
FET area
Analog P-type
FET area
GND
Analog N-type
FET area
P-well
N-well
P-type substrate
substrate current
- Triple well layout let us better
isolate digital and analog parts
of the chip.
GOSSIPO chip, submitted on December 12, 2005.
15
The prototype of the input circuit.
Principal Block Diagram of the prototype.
Charge sensitive
preamplifier
Cfb ≈ 1fF
Input 1
Ct ≈ 3.3 fF
Objectives for the first
submit.
Voltage follower
1) Operation of the proposed
front-end circuit
-stability of the preamplifier
-pulse response
-noise
-channel-to-channel spread.
Rfb ≈ 80 MΩ
Charge sensitive
preamplifier
Cfb ≈ 1 fF
Input 2
Ct ≈ 3.3 fF
Cpar ≈ 30 fF
CMOS
Comparator
Rfb ≈ 80 MΩ
Start
Stop
CMOS
Counter
Outputs
Cpar ≈ 30 fF
2) Cross-talk between the high
sensitive analog circuit and
high speed switching CMOS
blocks.
Clock
16
The prototype of the input circuit.
Measurements.
δ-pulse response of the
preamplifier. Qin = 410 e-
δ-pulse response of the
preamplifier. Qin = 1000 e-
- The preamplifier with (Cpar = 35 fF and Cfb = 1 fF) demonstrates
a stable operation and an expected pulse response and noise.
ENC = 60 e- (RMS) .
17
The prototype of the input circuit.
Measurements.
δ-pulse response at the output of the CMOS comparator.
Qin = 410 e-.
Threshold = 300 e-.
-
The channel-to-channel
spread of the threshold is
σTHR ≈ 160 e( consistent with simulations).
18
The prototype of the input circuit.
Measurements.
Clock signal is running
at 100 MHz.
The output of the
comparator.
Threshold = 300 e-
- no significant crosstalk between the high sensitive
input and the 100 MHz clock line.
19
Conclusions and plans.
Front-end readout circuit of the GOSSIP chip will benefit from
the low detector parasitic capacitance and no need to
compensate for the leakage current.
- The first prototype of the fast (40 ns peaking time), low-noise
(ENC = 60 e- (RMS) and low-power (2 μw per channel) input
circuit for the GOSSIP chip has been successfully
implemented in 0.13 μm CMOS technology.
-
Owing to the triple well layout used in the prototype, the high
sensitive analog inputs have been effectively isolated from
the high speed switching gates.
- A new prototype featuring TDC-per-pixel concept will be
submitted in the end of 2006.
20
Additional slide.
Protection against discharges.
Layout of the input pad
20um
Polymide
Oxide
High Resistive
Amorphous Silicon
3um
Metal layer TD
Metal layer LM
Qdischarge
Rprot ≈ 1MΩ
Rfb
Output
A
Cp-grid≈ 0.5fF
Cp-sub≈ 10fF
- protective resistor causes neither signal distortion
nor noise increase as long as Rprot●Cp-grid is less than 1ns.
21
Additional slide.
Integrated Grids.
22