A 1-20 GHz 400 ps True-Time Delay With Small Delay Error
in 0.13 μm CMOS for Broadband Phased Array Antennas
Feng Hu, Student Member IEEE, Koen Mouthaan, Member IEEE
Department of Electrical and Computer Engineering, National University of Singapore
hufeng@nus.edu.sg, k.mouthaan@nus.edu.sg
Abstract—A CMOS broadband true-time delay (TTD) with 400
ps delay is presented. A second order all-pass network (APN) is
used as the delay element to improve the delay-bandwidth tradeoff. Coarse delay tuning is realized with a 10-state trombone
topology. To the best of our knowledge, this is the first time that
the APN is used in the trombone topology. The fine tuning of
the TTD is accomplished with the 3-bit switched APN structure.
Both the delay path and the reference path are realized with
the APN to minimize inter-state insertion loss (IL) variation.
An extra continuous tuning stage is also implemented with the
APN to realize broadband continuous tuning. The final TTD is
fabricated in a standard 0.13 μm CMOS process. The core chip
is 1.6 x 2.5 mm2 and it consumes 2.2 mA to 5 mA from a 1.2 V
supply for all the delay states. The maximum delay is 400 ps. The
worst IL is 45 dB at 20 GHz for the largest delay. The measured
input/output return loss is better than 13 dB across 1-20 GHz.
Index Terms—all-pass network; ultra-broadband; true-time
delay; phased array.
I. I NTRODUCTION
Phased array antennas increasingly find their application in
wireless communication and radar systems. The broadband
application necessitates the use of broadband TTDs for the
phased array system.
Due to the low cost when fabricated in volume, CMOS implementations of the TTD are of interest. Although transmission line (TL) based TTDs have shown the largest bandwidth,
their realization in CMOS is difficult due to the stringent requirements on the switching components. In addition, without
the bandwidth-delay trade-off, TL TTDs with large delays
are bulky in CMOS. The artificial transmission line (ATL)
is more popular [1], [2]. The bandwidth of the ATL can be
traded to achieve a larger delay. However, the overall matching
bandwidth is still limited due to the frequency dependent
image impedance [3], [4]. Moreover, the large parasitics of
CMOS spiral inductors impose significant design constraints.
As a result, the APN is considered as a better option for
the delay element because of its large bandwidth for input
and output matching and its good delay-bandwidth trade-off.
Different switching methods have been presented for the APN
based TTD implementation, such as the single-pole-doublethrough (SPDT) based method and the self-switching method
[5]. These techniques, however, are not reported for CMOS
due to the need for high quality switching transistors.
Here, a broadband, large delay TTD based on APNs is
presented in CMOS. The coarse delay is realized with a 10state trombone topology, and to the best of our knowledge,
this is the first time that APNs are utilized in the trombone
Fig. 1. Topology of the TTD.
topology. Conventional SPDT based switching is used for
the fine tuning with both the delay path and reference path
realized by APNs. An additional continuous delay tuning stage
is implemented with APNs as well. This stage allows for
compensation of delay errors introduced in the preceding delay
stages. Section II describes the design of different parts of the
TTD. The measurement results are reported in Section III and
Section IV provides the conclusions.
II. TTD I MPLEMENTATION
The overall TTD block diagram is shown in Fig. 1. The
delay element in the diagram is solely based on second order
APNs. The APN provides a good delay-bandwidth trade-off
and its intrinsic input/output matching. The design parameters
for a second order APN are given as [5]:
2(L − M )
Zo =
(1)
CP
CP (L + M )
=1
4CS (L − M )
(2)
978-1-4799-8275-2/15/$31.00 ©2015 IEEE
The corresponding group delay of a single APN is
τ = τ0
1 + QΩ2
1 + (1/4 − 2Q)Ω2 + Q2 Ω4
(3)
where τo = CP Zo (Zo is the characteristic impedance of the
system), Ω = ωτo and Q = CS /CP . First of all, it can be seen
that the group delay has a multiple-pole response which allows
for a good trade-off for the delay against bandwidth. Secondly,
the shunt capacitance CP has a larger value compared to the
shunt capacitance of the ATL if the same delay and bandwidth
are considered.
Fig. 2. Micrograh of the chip.
A. 10 state trombone using APN
B. 3-bit SPDT based switching APN
The fine tuning of the TTD is implemented with the
switched APN topology using SPDT switches. The good
matching property of the APN simplifies the SPDT design
by eliminating the conventional matching inductors. The size
of the fine tuning stage is thus reduced. In order to reduce the
inter-state IL variation, both the delay path and the reference
path are realized with APNs to obtain a similar frequency
dependent IL response for all states. A fine tuning resolution
of 5.6 ps is used here.
C. APN based continuous tuning stage
The conventional ATL based continuous tuning delay is
utlized by tuning the shunt capacitance. However, in order to
maintain acceptable input/output matching, the shunt capacitance variation range is limited due to the parasitics of the
on-chip spiral inductor. As a result, this work uses the APN
to provide the continuous tuning delay. The shunt capacitor
CP is replaced with the MOS varactor which has an octave
capacitance variation range. Three stages of such APNs are
cascaded to generate a 2.8 ps continuous tuning range.
III. R ESULTS
The TTD is fabricated in a standard 0.13 μm CMOS process.
The micrograph of the TTD is shown in Fig. 2. The core part of
the TTD is 1.6 x 2.5 mm2 . The whole TTD consumes 2.2 mA
to 5 mA from a 1.2 V supply for all different delay states. The
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Due to the aforementioned merits of the APN, the gate line
and drain line of the coarse trombone delay use APNs to alleviate the input/output parasitics requirements of the switching
amplifiers. The tapping point of the switching amplifier is
located at the shunt capacitor CP . For the same bandwidth, it
can be easily shown that CP is larger than the shunt capacitance in the ATL version gate/drain line. The only drawback is
that the voltage at the tapping point degrades with frequency.
However, in the case of a 20 GHz application, the amplitude
penalty is only 2 dB which can be easily compensated by the
enlarged switching amplifiers. The switching amplifier is also
shown in Fig. 1. The size of the amplifiers are scaled so as
to reduce the inter-state IL variations. Additional interstage
peaking inductors are also used to improve the transmission
response. The 10-state trombone is designed to generate a 360
ps delay with 40 ps resolution.
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Fig. 3. Measured input/output reflection coefficients and forward transmission
coefficients of the TTD for all 80 states.
10-state trombone and the 3-bit switched APN stages are used
to generate 80 delay states with the continuous stage constant.
The measured reflection coefficients of the whole TTD are
shown in Fig. 3. The measured input/output return loss is better
than 13 dB across the whole bandwidth of 1-20 GHz. The
lower bandwidth limitation is mainly determined by the DC
blocking capacitor. The corresponding forward transmission
coefficients of the TTD are also shown in Fig. 3. The insertion
loss is 45 dB at 20 GHz in the maximum delay setting.
Fig. 4 shows the measured relative delay of the 3-bit
switched APN stage with the coarse delay stage fixed at 200
ps. The 3-bit switched APN stage exhibits a flat delay response
across the measured frequency range. The maximum delay is
40 ps and the resolution is 5.6 ps. The measured relative delay
of the 10 state trombone is also shown in Fig. 4. The fine
tuning stage is set at 16 ps. It can be seen that the maximum
delay is 360 ps and the resolution is 40 ps.
The relative delay of all the 80 measured states is shown
in Fig. 5 and the standard deviation for each state across the
measured bandwidth is shown in Fig. 6. The standard deviation
of the TTD for the 80 states is below 8 ps.
Fig. 8 shows the continuous tuning property of the TTD and
its input referred 1 dB compression points at 2, 4, 8, 16 and
20 GHz. The designed continuous delay tuning should be 02.8 ps. However, the measured tuning range is 0-2 ps. This is
mainly attributed to the parasitic capacitance of the continuous
tuning stage. The P1dB of the TTD is from 1 dBm to 5 dBm
across the 1-20 GHz.
978-1-4799-8275-2/15/$31.00 ©2015 IEEE
700
350
30
20
10
600
300
Group Delay (ps)
Relative delay
of the trombone stage
Relative delay
of the switched APN stage
400
40
250
200
150
100
5
10 15 20
Frequency (GHz)
0
400
300
200
50
0
1
500
1
100
1
5
10
15
20
Frequency (GHz)
Fig. 4. Measured relative delay of the 3-bit switched APN stage when fixing
the coarse delay stage at its 6th delay setting and relative delay of the 10 state
trombone stage when fixing the fine tuning stage at ’011’.
5
10
15
Frequency (GHz)
20
Fig. 7. Measured group delay of the TTD for all 80 states.
2.5
5
Relative Delay (ps)
400
300
200
4
IP1dB (dBm)
Relative Delay (ps)
4.5
2
1.5
1
3.5
3
2.5
2
0.5
1.5
100
0
0
0
1
5
10
15
Frequency (GHz)
20
0.5
1
Control Voltage (V)
1
0
10
Frequency (GHz)
20
Fig. 8. Measured continuous tuning property and the input referred 1 dB
compression point of the TTD.
Fig. 5. Measured relative delay of the TTD for all 80 states.
TABLE I. Performance summary of the TTD.
Ref.
[1]
Technology
0.18 μm SiGe
7
Frequency Range (GHz)
1-20
1-15
15-40
1-20
6
Maximum Delay (ps)
64
75
42
400
Average P1dB (dBm)
-24
-18
9
2.5
Size (mm2 )
1.6
2.48
0.99
4
PDC (mW)
87.5
138
8.6-24.6
2.6-6
Standard deviation
of the relative delay (ps)
8
5
4
[2]
[3]
This work
0.13 μm CMOS
3
R EFERENCES
2
1
0
0
10
20
30
40
50
Measurement state
60
70
80
Fig. 6. Standard deviation of the relative delay for all 80 measured states.
IV. C ONCLUSION
A 1-20 GHz, 400 ps TTD in 0.13 μm CMOS is presented.
The performance of the TTD is summarized in Table I
together with some state-of-the-art references. By using the
second order APNs, this work achieves the best bandwidthdelay trade-off. Without gain compensation stages, the power
consumption is low and the P1dB is high. However, the IL is
large and additional amplifiers well be needed to compensate
for these losses.
[1] J. Roderick, H. Krishnaswamy, K. Newton, and H. Hashemi, “Siliconbased ultra-wideband beam-forming” IEEE J. Solid-State Circuits, vol.
41, no. 8, pp. 1726-1739, 2006.
[2] T.-S. Chu, J. Roderick, and H. Hashemi,“An integrated ultra-wideband
timed array receiver in 0.13 μm CMOS using a path-sharing true time
delay architecture” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 28342850, 2007.
[3] S. Park and S. Jeon,“A 15-40 GHz CMOS true-time delay circuit for
UWB multi-antenna systems,” IEEE Microw. Wireless Compon. Lett., vol.
23, no. 3, pp. 149-151, 2013.
[4] M.-K. Cho, J.-H. Han, J.-H. Kim, and J.-G. Kim, “An X/Ku-band bidirectional true time delay T/R chipset in 0.13 μm CMOS technology,”
Microwave Symposium (IMS), 2014 IEEE MTT-S International, pp. 1-3,
2014.
[5] J. G. Willms, A. Ouacha, L. de Boer, and F. E. van Vliet, “A wideband
GaAs 6-bit true-time delay mmic employing on-chip digital drivers,”
Microwave Conference, 2000. 30th European, 2000.
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