Hybrid CMOS/Magnetic integrated
electronics
Ricardo C. Sousa, Bernard Dieny
SPINTEC UMR8191 (CEA/CNRS/ UJF)
SPINTEC CEA-INAC 17 rue des Martyrs
38054 Grenoble
France
bernard.dieny@cea.fr
ricardo.sousa@cea.fr http://www.spintec.fr
Workshop on Innovative Memory Technologies
2012, June 21 - MINATEC, Grenoble - France
OUTLINE
Basic phenomena used in spintronic devices
Tunnel MR, Spin-Transfer Torque (STT)
Various categories of MRAM
MRAM written by Spin Transfer Torque (STT
MRAM)
Downsize scalability below 20nm
Extended scalability and new functionalities of
MRAM using thermally assisted writing
Low-power and reconfigurable electronics
based on hybrid CMOS/MTJ technology
Transistor scaling will result in
higher leakage currents for volatile
memory and logic gates.
Energy savings by combining nonvolatile memory and logic functions.
Non-Volatile Logic:
Combining non-volatile elements to reduce standby power consumption
2 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Tunnel Magnetoresistance (TMR)
Tunnel magnetoresistance at RT in magnetic tunnel junctions (MTJ):
Julliere (1975) but only at low T
Moodera et al, PRL (1995);
Myazaki et al, JMMM(1995).
I
Free layer: CoFe 4 nm
or
Like couple
polarizer/analyzer
in optics
Al2O3 barrier 1.5nm
Reference layer :CoFe
3nm
IrMn 7nm
(antiferromagnetic)
-20
TMR=(RAP-RP)/RP~ 40-70%
-10
0
10
20
Applied Mag Field (mT)
Giant tunnel magnetoresistance in crystalline MgO based MTJ
Parkin et al, Nature Mat. (2004);
Yuasa et al, Nature Mat. (2004).
TMR~ 100-600%
Crystalline:
Additional spin-filtering mechanism
according to symmetry of electron
wave functions
-20
-10
0
10
20
Applied Mag Field (mT)
3 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Spin-Transfer Torque (STT)
Predicted by Slonczewski (JMMM.159, L1(1996)) and Berger (Phys.Rev.B54, 9359 (1996))
Giant or Tunnel magnetoresistance:
Acting on electrical current via the magnetization orientation
Spin transfer is the reciprocal effect:
Acting on the magnetization via the spin polarized current
PINNED LAYER
FREE LAYER
M.D.Stiles et al,
Phys.Rev.B.66,
014407 (2002)
TUNNEL BARRIER
Reorientation of spin polarization ⇒Torque on the free layer magnetization
A new way to manipulate the magnetization of magnetic nanostructures
4 /24
Hybrid CMOS/magnetic technology for low power electronics
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STT induced magnetization switching
First observation in fully metallic structures (Co/Cu/Co sandwiches Jc ~2-4.107A/cm²)
Katine et al, Phys.Rev.Lett.84, 3149 (2000)
Field scan
I+
CoFeCu2
Cu
(pinned)
9
R(ohms)
(free)
CoFeCu1
8,9
I-40
-400
9,1
-20
-200
9,1
H = -4 Oe
9
R(ohms)
I = -0.4 mA
Current scan
8,9
8,8
8,8
8,7
8,7
20
40
00
200
400
H(Oe)Field (mT)
Applied Mag
-8
-4
0
I(mA)
4
8
Deac A, Lee KJ, Liu Y, et al.Phys.Rev.B73 (6), 064414 (2006)
First observation in MTJ : Huai et al, APL (2004); Fuchs et al, APL (2004) (Jc ~106A/cm²)
Hayakawa et al,
Japanese Journal of
Applied Physics
44, (2005),L 1267
5 /24
Hybrid CMOS/magnetic technology for low power electronics
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Spintronic components
R(H)
“1”
“0”
Rlow
Rhigh
Write/read heads
Magnetic field sensors
Memories
Cu
PtMn
CoFe
CoFe
(Pt/Co)
Everspin 4Mbit
J
Al2O3
Cu
Logic circuits
RF components
Dieny B et al, Intern.Journ.Nanotechnology, 7, 591 (2010).
6 /24
Hybrid CMOS/magnetic technology for low power electronics
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MRAM basics - Read
Read data by sensing the cell resistance and comparing to a reference cell
Address
Data out (Rhigh)
0
0
1010
Data ref
10
Normalised
count
Norm alised Count
Rmax
Rmax
min
RRlow
-1
Data out (Rlow)
-2
10
-3
10
-4
10
Read @ 20ns in products
Down to sub-10ns demonstrated
-5
10
>25σ
-6
10-610 0
0
100
200
300
400
500
600
Resistance
700
0.5
Resistance (kΩ)
7 /24
800
900
1000
1kΩ
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
MRAM basics - Store
KuV
Switching rate
τ = τ 0e
∆E
k BT
Barrier to overcome for switching
Thermal activation
t0 = 10-9s
Switching probability for one bit
P± = 1 − e
−
t
τ±
Stability barrier KuV
Key role of the thermal stability factor
∆= ∆ E/kBT
8 /24
-2
10-2
-4
10-4
-6
10-6
10
∆E/kBT>49
∆E/kBT>67
∆E/kBT>70
10
Log (Failure rate)
For 1 bit, 10 years retention
For 1 Mbit,
For 1 Gbit
Proba of failure in standby
Probability of Accidental switching for N bits:
 − Nt
 ∆E  

F (t ) = 1 − exp(− Nt / τ ) = 1 − exp 
exp −
k
T
τ
 B 
 0
1bit
32Mbit
1Gbit
1FIT
Δ= 49
70
67
-8
10-8
-10
10-10
30
40
30
40
50
60
50
60
70
70
∆E/KBB
TT
∆E/K
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
80
80
90
90
In-plane versus out-of-plane STT switching
In-plane magnetized MTJ
α = damping
p = polarization
A = Area
g(0)~1
in − plane
jc
πM s2V
 4e  αk BT 
 ∆ +
= 
k BT
 h  g (0) pA 
Thermal stability determined by inplane anisotropy (shape anisotropy)
Simpler materials but additional
penalty in jc due to out-of plane
precession
9 /24
Out-of-plane magnetized MTJ



 4e  α k B T
jcperp =  
∆
 h  g (0) pA
More complex materials but lower jc
expected thanks to direct
proportionality between Jc and thermal
stability
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Various MRAM differing by their write principle
Spin Transfer Torque
« STT » or « SPRAM »
Field-only
« Toggle »
Hx
Planar
Perpendicular
Thermal Assist
« TAS » or « TAMRAM »
Field-TAS
STT-TAS
Hy
1, 4, 16Mb Toggle (2006)
Crocus 1Mb Field-TAS (2011)
Established technology
Lower write current
Minimal cell / array size
Scalable down to 14nm
with dual p-MTJ
1.5M units shipped
4.5M forecasted in 2011
Scalable down to ~ 10nm
High stability
Multibit possible
Not scalable beyond 90 nm
10 /24
Hybrid CMOS/magnetic technology for low power electronics
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Recent Perpendicular STT Demo Chips
10ns
50ns
253 cells
11 /24
Hybrid CMOS/magnetic technology for low power electronics
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Thermally Assisted writing (TA)
Purpose: Solve the dilemma between
 4e  α
perp
I write
= 
k BT .∆
 h  g (0 ) P
•Use temperature-dependence of switching ability
RETENTION
WRITABILITY
e.g.
Write at elevated temperature
Store / read at room temperature
•Same basic concept as in Heat Assisted Magnetic Recording in hard disk drive technology
Plasmonic antenna
for local heating
20nm
B.C.Stipe et al, Nature Photonics 4, 484 (2010)
• In MTJ for MRAM, heating produced by Joule dissipation around the tunnel barrier.
• Write temperature~250°C
12 /24
Hybrid CMOS/magnetic technology for low power electronics
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Thermally Assisted MRAM written by Field
Ta (5nm)
Ru (2nm)
IrMn (6nm)
Storage
Low TB
~200°C
CoFeB (2.5nm)
MgO
CoFeB (2.5nm)
Ru (0.8nm )
CoFe (3nm)
Reference
ON
PtMn (20nm)
High TB
>350°C
1 Mbit chip
Ta (10nm)
Low switching field
at write temperature
thanks to circular bit
shape
Resistance change
Dieny B et al, Intern.Journ.Nanotechnology, 7, 591 (2010).
4
Heating
(106A/cm²)
Heatingcurrent
current,density
d=100nm
0.14
0 .1
mA
11µA
1.15
0 .8
A
90mµA
1.8
1
.3
m
A
140 µA
3
Initial
state
2
Final
state
1
0
-1
00
-10
-100
-5-5
0
0
00
5 05
1100
010
0
H(Oe)
Applied
Mag Field (mT)
13 /24
1 515
0
-20
-10
0
10
20
H(Oe)
Applied Mag Field (mT)
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Thermally Assisted MRAM written by Field
1Mbit chip SRAM compatible demonstrator
130nm technology
Writing demonstrated down to 10ns pulses
(thermal rise time ~5ns)
Write voltage level controlled through
engineering of thermal barriers
2.2
260
2
240
Resistance (Ω)
IOF
External field immunity on stored data verified
up to 15mT
Heat voltage (V)
Write field of 2mT can be used instead of 7mT
in toggle MRAM (thanks to circular pillar)
1.8
1.6
1.4
1.2
Rmax
Rmin
220
200
To be continued...
180
160
140
1
Low write field thanks to circular shape MTJ.
Thermal stability not provided by a shape anisotropy
but by pinning of the storage layer at RT
With KIrMn=3.106erg/cm3,
D=KV/KBT>200 for 50nm diameter
D=KV/KBT=70 for 12nm diameter
14 /24
0.5
1
1.5
2
2.5
IOFLD
3
3.5
Field line voltage (V)
4
120
6
7
8
9
10
11
12
13
10 10 10 10 10 10 10 10
Number of pulses
Very good downsize
scalability provided by
Thermal Assistance
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Write sequence (Field-TA-MRAM)
1) Data set field pulse “0”
2) Data set field pulse “1”
“0”
“1”
64 bits
“0”
“0”
“0”
“1”
“0”
“0”
“0”
“1”
Only 2 pulses of field required to write 64bits
Required field ~ 3-5mT
vs
vs
65 pulses in toggle.
7-10mT in toggle
Energy per 10ns field pulse over 64bits=35pJ i.e. 0.55pJ per bit
Energy per 10ns heating pulse = 1pJ per bit, similar to STT writing
15 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
TA-MRAM as Content Addressable Memory (CAM)
0001
“0”
“0”
“0”
“1”
Iread
1100
“1”
“1”
“0”
“0”
Iread
1010
“1”
1000
“1”
“0”
“1”
“0”
“0”
Iread
“0”
“0”
Iread
V>Vmin
V>Vmin
Vmin
V>Vmin
“1”
“0”
“1”
“0”
Search address of “1010”
CAM for search engines, routers.
Intrinsically combines memory and XOR functions: Magnetic Logic Unit (MLU)
“Match-in-Place” ⇒ security applications
16 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Thermal assistance in perpendicular STT-MRAM
TAS + STT
IHeating
+STT
OFF
ON
OFF
OFF
Takes advantage of a thermally induced anisotropy reorientation
S.Bandiera et al, APL 2011
M
j
r
r
M ⊥P
P
-10
-5
0
5
Applied Mag Field (mT)
17 /24
M^P max
TSTT max
10
Max STT efficiency
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Thermal assistance in perpendicular STT-MRAM
p-MTJ with (Pd/Co)/CoFeB/MgO/CoFeB/(Pd/Co)
RAP
RP
-0.2
-0.1
0
0.1
(T)
0.2
S.Bandiera et al, APL 2011
Reference
Very significant decrease in
coercivity versus bias voltage
due to Joule heating around the
tunnel barrier
Figure of merit:
∆  4e α

=
k BT 
Ic  h P

−1
Figure of merit
/I
Material JC(30ns) (MA/cm2) Δ(d=40nm) Δ/J
C c TMR(%)
α
Nakayama CoFeB/
et al. (2008) TbFeCo
4,9
10
2
10
?
Ohno et al.
(2010)
CoFeB/
MgO
3,8
43
113
120
0,013
Worledge CoFeB/
et al. (2011)
MgO
2,8
20
71
46
0,04
4,6
73
159
10
0,15
This work
(2011)
CoFeB/
(Pd/Co)
Largest Figure of Merit ever reported thanks to TA+STT
18 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Where MRAM can help ?
1) In memory hierarchy, replacement of DRAM or Cache 3 or 2 by STT
MRAM without changing the overall architecture
volatile
2GHz-500ps
1ns
3ns
Non-volatile
Strong decrease in static power
consumption (suppressed leakage in DRAM) ALU
CPU
•No more need for DRAM
FF
refreshment
Registers
•Very fast reboot
ALU
CPU
FF
Registers
Cache 1
Cache 1
Cache 2
30ns
DRAM
100ns
MRAM
File Cache
ms
HDD
SSD
HDD
SSD
(Samsung, Hynix/Toshiba: replacement of DRAM by STT-MRAM beyond the 20nm node)
T.Kawahara, IEEE Design and test of computers, 52, Janv/Feb 2011)
19 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Normally-OFF Computers
Conventional power gating
20 /24
Ultrafast power gating
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Where MRAM can help ?
2) Tighter integration between logic and memory
Same technology as for MRAM
With CMOS technology only:
Dieny B et al, Intern.Journ.Nanotechnology, 7, 591 (2010).
With hybrid CMOS/magnetic:
“Logic-in memory”
MTJs
Logic
CMOS memory
Si
Logic
Si
-Slow communication between
logic and memory
-few long interconnections
-Large capacitive dynamic losses
-complexity of interconnecting paths
-large footprint on wafer
-Memory much closer to logic
-Large static and dynamic energy saving
(“normally-off / Instant-on computing”)
-Fast communication between
logic and memory
-Numerous short vias
-Simpler interconnection paths
-Smaller footprint on wafer
New paradigm for architecture of complex electronic circuit (microprocessors..)
21 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Where MRAM can help ?
3) With ultrafast MRAM (~300ps), non-volatily can be introduced in the logic
gates (Flip-flop, ALU…)
2GHz-500ps
1ns
3ns
volatile
Further decrease in power consumption
Increased resilience
Ultra-fast “on-fly”reconfigurability
ALU
CPU
FF
Registers
Non-volatile
NV-ALU
NV-CPU
NV-FF
Cache 1
Cache 2
30ns
DRAM
100ns
MRAM
File Cache
ms
HDD
SSD
HDD
SSD
T.Kawahara, IEEE Design and test of computers, 52, Janv/Feb 2011)
22 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Magnetic non-volatile logic circuits
Hitachi + Tohoku University
S.Matsunaga et al, Applied Physics Express, vol. 1, 2008.
Non volatile Full Adder
One input is made non-volatile (instant startup, security)
–
Demonstrator : CMOS 0.18µm,
CMOS/Mag
NV-SRAM
Magnetic LUT
Reduced power consumption
Reduced footprint
See also Y.Gang et al, IEEE Trans.Mag.47, 4611 (2011)
23 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Conclusion
•Purpose of hybrid CMOS/Magnetic technology is to combine the best of the two worlds
CMOS
Magnetism
Speed, low dynamic power consumption
perfect for logic
Non-volatility of magnetization
perfect for memory
•Increasing interest for p-STT MRAM for standalone, embedded memories or logicin-memory. Scalability down to 14nm with dual p-MTJ.
•Thermally assisted writing allows to extend the downsize scalability, reduce power
consumption and introduce new functionalities in MRAM (e.g. Match-in-Place)
•Manufacturing technology getting more and
more mature with a growing number of actors
•Huge potential development
24 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr
Acknowledgements
B.Dieny
R.Sousa
J.Herault
S.Bandiera
Y.Hadj-Larbi
B.Rodmacq
S.Auffret
M.Souza
L.Nistor
JP Nozieres
L.Buda-Prejbeanu
J.C.Toussaint
I.Firastrau
M.Chsiev
B.Belhadji
H.Bea
S.Amara
V.Baltz
J.Moritz
Work partly supported by the projects
I.L.Prejbeanu
K.Mackay
L.Lombard
E.Gapihan
C.Ducruet
Y.Conraux
C.Portemont
J.Shin
K.Azizpor
D.Beery
Y.Cohen
J.Reid
B.Cambou
O.Redon
B.Delaet
M.T.Delaye
M.C.Cyrille
RAMAC (ANR 2007)
CILOMAG (ANR 2007)
NANOINNOV SPIN (2009)
HYMAGINE (ERC2009)
PATHOS (ANR 2010)
25 /24
Hybrid CMOS/magnetic technology for low power electronics
– ricardo.sousa@cea.fr