Order this Data Sheet by H4CP/D
MOTOROLA
SEMICONDUCTOR
H4CPlus
SERIES
TECHNICAL DATA
Product Data Sheet
H4CPlus™ SERIES CMOS ARRAYS
The new H4CPlus Series arrays feature new 3.3V, 5V and mixed-voltage
capability, high-speed interfaces, and analog PLLs for chip-to-chip clock skew
management. The gate length has been reduced to 0.65 µm Leff to provide
improved 5V performance and competitive performance at 3.3V.
The low- and mixed-voltage capability lets designers customize the H4CPlus
arrays to fit power and performance needs. All H4CPlus arrays have dual VDD rails
with custom power/ground bus tying to power input and output buffers for full 3.3V,
full 5V or a mix of system voltage levels. Additionally, the core of the arrays may be
powered by either 3.3V or 5V.
New, high-speed CMTL, GTL, and PECL macros offer enhanced chip-to-chip
communication. CMTL (Current Mode Transceiver Logic™), a Motorola innovation
with optional active termination, offers a high speed communication interface at
200+ MHz and can interface to differential and single-ended PECL (Pseudo Emitter
Coupled Logic). Differential and single-ended GTL (industry standard Gunning
Transceiver Logic™) offers high performance data bus and point to point
communications up to 250 MHz. Differential and single-ended PECL inputs offer
ECL compatible clock rates up to 400 MHz worst case. Also, new PCI (Peripheral
Component Interface) compliant I/O buffers are available in 5V and 3.3V versions.
(cont’d. page 2)
H4CPlus Series Features
• 0.65 µm Leff, channelless, triple-layer metal gate arrays
• Typical gate delay of 280 ps at 5V and 420 ps at 3.3V (NAN2, FO=2)
• Low power, 1µW/gate/MHz (3.3V), 3µW/gate/MHz (5V)
• 3.3V, 5V or mixed system and core voltage levels
• Custom power bus tying and ground bus isolation for special power needs
• Configurable I/O cell supports 2 to 24 mA, up to 48mA using dual I/O cells
• PCI compliant 5V and 3.3V I/O buffers with 5V I/O tolerant, 3V I/O input and
output macros, and 5V I/O fail-safe macros
• Differential and single-ended GTL I/O and PECL input macros
• Analog PLL with 70 to 250 MHz worst case VCO frequency
• Pseudo-Random and comparator BIST macros
• Single-, dual-, and quad-port metal SRAMs
• Single- and dual-port diffused SRAMs
• Powerful design environment using Mentor Graphics, Cadence Design
Systems, Synopsys, Quad Design Technology, and Motorola design tools
• OMPAC ball-grid array, MicroCool, and PQFP packaging
Array Name
H4CP011
H4CP028
H4CP048
H4CP075
H4CP109
H4CP146
H4CP178
© MOTOROLA, INC. 1995
Table 1. H4CPlus Series Arrays
Die Size
Available Gates
Die Pads
(mils/side)
11,036
179
120
28,400
239
176
48,100
287
216
74,520
337
256
109,368
391
304
145,544
438
344
178,000
476
376
HIGH PERFORMANCE
TRIPLE LAYER METAL
SUB-MICRON
CMOS ARRAYS
(insert photo of
H4CPlus SERIES
Packages)
QFP
MicroCool
OMPAC
TYPICAL H4CPlus SERIES PACKAGES
I/O Sites
120
160
208
256
312
360
400
Package
Pins
80-100
100-169
100-225
128-225
160-313
160-313
160-313
REV 2
PRODUCT DESCRIPTION
(cont’d from page 1)
Each array can have two APLL (Analog Phase Lock Loop)
macros, placed in the adjacent corners of the die, having
separate APLL power pins for obtaining low noise and phase
jitter. External components are not required since the VCO
filter is contained in the APLL. The APLL can be used in
applications such as clock synthesis with a worst case VCO
frequency of 70 to 250 MHz (30 to 415 MHz typical).
Other design features include Fail-Safe macros, metal and
diffused RAMs, ESSD/LSSD scan macros, JTAG boundary
scan, and Built-In Self Test macros.
HIGH-PERFORMANCE TECHNOLOGY
The H4CPlus Series uses a self-aligned twin tub process
in which n-type and p-type well implants are driven together
to form deep, balanced wells to improve short n-channel transistor performance, see Figure 1. A lightly doped drain (LDD)
diffusion is used to reduce hot carrier injection effects caused
by a high electric field in the short channel transistors. A highly-reliable multi-layer metal structure is achieved by a planarization technique using tapered contacts and vias.
The combination of a small feature size and a thin gate oxide coating provides both high gate density and low power
dissipation. The typical power dissipation for internal gates is
only 1µW/gate/MHz at 3.3V and 3µW/gate/MHz at 5.0V with
a load of 0.05 pF (fanout = 1).
Plasma Nitride
PSG
Passivation
M3
PTO (Plasma Teos Oxide)
Polysilicon
Gate
M2
PTO
(Plasma Teos Oxide)
M1
BPSG
Field Oxide
p-Field
n-MOSFET
p-MOSFET
p-Well
n-Well
Gate Oxide
p-Substrate
Figure 1. H4CPlus Series CMOS Device Cross-Section
The H4CPlus Primary Cell
The primary cell consists of four pairs of n- and p-type
transistors. The transistors are the same size to optimize
both gate density and routability. The primary cell is used to
configure all H4CPlus Series macrocells. Figure 2 shows half
P-Channel
Transistors
of a primary cell (two p-type and two n-type transistors) configured in a 2-input NAND gate (NAN2). The typical gate
delay for a 2-input NAND with a fanout of 2 is 280 ps at 5V
and 420 ps at 3.3V.
N-Channel
Transistors
VDD
A
A
A
A
B
X
B
X
B
P-Well
N-Well
B
Polysilicon
Gate
VDD
VSS
VSS
Figure 2. 2-Input NAND Gate Implemented Within Half of a Primary Cell
MOTOROLA
2
H4CPlus_Series
PRODUCT DESCRIPTION (continued)
Triple-Layer Metal Routing
A triple-layer metal (TLM) structure provides superior
routing access to configure and connect macrocells as well
as distribute power and ground, see Figure 3.
Figure 3. Triple-Layer Metallization (SEM Photo)
One important benefit of TLM routing is improved
routability for higher gate utilization. TLM also provides
improved clock distribution by moving the clock signals to the
top metal layer where the capacitance per unit length is 30%
less than the lower metal layers due to a thicker dielectric
layer. In addition, TLM reduces interconnect delays typically
by 10% with shorter interconnect lengths and improves
power distribution.
• Gate Ensemble Place and Route
The design of the routing layers is accomplished with
Cadence’s Gate Ensemble place and route system. Some of
Gate Ensemble's capabilities include soft/firm grouping of
macros, clock-tree synthesis, incremental layout changes,
and highly accurate distributed RC calculations. In addition,
the power-bus router automatically uses single-, double-, or
quadruple-width power tracks to optimize performance while
minimizing spent routing channels where needed.
• PrediX Floorplanning
PrediX is Motorola’s powerful floorplanning and routability analysis tool that enables designers to predict and
improve routing congestion especially in complex circuits.
PrediX is easy to use and interfaces with Gate Ensemble to
assure the desired results in layout and timing.
SPECIAL DESIGN FEATURES
THE H4CPlus SERIES LIBRARY
Pull Resistors
Out
H4CPlus_Series
Pad
T
I/O Cell
ESD Diodes
Active Terminations
JTAG
Logic
Array Core
I/O Cell
I/O Macrocell Library
The H4CPlus Series I/O cells, see Figure 4, are configurable into inputs, outputs, bidirectionals, oscillators, JTAG I/
O, CMTL, GTL, and PECL interfaces. The standard CMOS,
TTL, slew control, 3-state, open-drain and Schmitt-trigger I/O
functions are available as well. The I/O cell also provides
pull-up and pull-down resistors, active terminations for
CMTL, voltage translation between 3.3V and 5V levels, and
power and ground connections.
• 3.3V, 5V, and Mixed-Voltage I/O
The I/O cell can support any combination of 3.3V and 5V
in system and core voltage requirements. This is accomplished with a voltage translator to translate between logic
levels based on the system and core voltages, see Figure 4.
Low-voltage interfaces are important in systems requiring
low-power since most of the power dissipated in ICs occurs
in the outputs. However, performance is usually sacrificed for
lower power. The H4CPlus Series I/O offers all combinations
of system and core voltage levels to meet power and performance goals. For example, the ONL8 is a 12mA output for a
3.3V/3.3V (3.3V Input/Output with 3.3V core. Its power dissipation is about 56% less than the 5V/5V ON8 output, but it is
41% slower at 100pF, see Figure 5. The ONLX8 (3.3V/5V)
and the ONX8 (5V/3.3V) is moderately slower than the ON8.
Configurable Output
Pad
Volt. Trans.
The H4CPlus Series library is an optimized set of macros
containing a complete suite of I/O functions, combinatorial
and sequential functions. Many basic logic functions come in
several versions including standard/high-drive capacity and
scan/non-scan to provide the widest choice of functions.
In
I/O Cell
Configurable Input
Figure 4. H4CPlus Series I/O Cell
• Selectable Output Drive
Up to 24 mA is available from a single I/O cell, two cells
may be paralleled for up to 48 mA drive from a single output
pin. (All JTAG outputs and bidirectionals are not parallelable,
but have higher current capacity versions available.) Unused
output drivers may also be used to drive highly loaded internal signals such as clock networks.
• Slew Rate Control
Slew rate control outputs are available to reduce system
SSO noise as well as over-shoot and undershoot of output
signals caused by fast rise and fall times. All 4 and 8 mA output buffers have a moderate (10%) and slow (30%) slew
control version.
MOTOROLA
3
SPECIAL DESIGN FEATURES (continued)
• PCI I/O Buffers
System
ONL8
ONX8
ONLX8
ON8
4
3.3V/3.3V Core
5V/3.3V Core
3.3V/5V Core
5V/5V
Core
tPLH
3
2
1
0
0
20
40
60
80
100
Load (pF)
Figure 5. Performance Comparison of 12mA
Output Buffers
PCI (Peripheral Component Interface) is emerging as a
high-performance local bus architecture. It is a highly flexible, processor independent architecture that has applications
in low- to high-end desktop, server and low-power, mobile
systems. Motorola offers PCI compliant 3.3V and 5V I/O
buffers to allow connection of H4CPlus arrays to any PCI
local bus “speedway”.
• GTL Interface
GTL is able to drive system backplanes while still occupying only a single I/O site for 50Ω and two sites for 25Ω.
This licensed implementation provides a high performance
bus driver for system I/O data rates exceeding 200 Mbits/sec
depending on the bus fanout loading. Differential GTL is also
available for providing the clock signals to Fast Static
BiCMOS RAMs and for point to point applications providing
worst case clock rates of greater than 200 MHz.
• PECL Interface
Standard positive ECL voltage levels can be received
with differential and single-ended PECL receiver macros at
worst case clock rates up to 400 MHz. The H4CPlus arrays
can also drive Standard PECL inputs by using CMTL or GTL
output macros as described in application note AN1521.
• Fail-Safe I/O Macros
5 Volt Fail-Safe I/O macros are provided for bus applications that will not load the active bus when power is
removed. These macros can be designed in applications
requiring "hot plug" operation where a card is inserted while
the system is running.
• Extended Voltage Range I/O Macros
Extended Voltage Range I/O macros, or 5V tolerant 3.3V
I/Os provide a flexible design solution for designers implementing 3 volt systems in a 5 volt world. These macros designated by an "E" in their name require only a 3 volt supply,
but can tolerate the reception of a 5 volt signal on the pad.
• CMTL Interface
Motorola’s new Current Mode Transceiver Logic (CMTL)
buffers provide a low-power alternative to high-speed interfaces. On-chip active termination allows for the lowest possible power dissipation while enhancing the performance.
They may also be configured with external 50Ω terminations
in bidirectional or PECL applications.
The drivers have been engineered to operate without
external reference or termination voltages and over a wide
range of common-mode voltages. The flexibility of this
design allows simple, direct interfaces to ECLinPS or other
ECL-level chips operating in a PECL environment with standard terminations.
Applications for CMTL range from video to telecommunications to tightly-coupled processor/cache interfaces. I/O
pair delay is less than 2ns worst-case. Systems are no
longer limited by slow buffers for critical chip-to-chip paths.
n-BITS
FIFO
Control
FIFO
n-BITS
HighSpeed
Data
n-Bit Shift Register
400 Mb/sec
Data
Out
400 MHz
Clock
ECLinPS™ Logic
H4CPlus Series with CMTL I/O
Enable
Graphics
Engine
Data Out
or
Data In
m-bits
Vref
m-bits
CPU
or
Address
Signal
Processor
Control
n-bits
H4CPlus Series with CMTL I/O
ASIC #1
ASIC #2
Enable
Enable
Data Out
Data Out
Data In
High-Speed
Input
Data In
Self-Terminating
Differential
High-Speed
Output
Self-Terminating
Single-Ended
Vref
PECL I/O RAM
or RAMDAC
High-Speed
Input
High-Speed
Output
Figure 6. Typical CMTL Applications
MOTOROLA
4
H4CPlus_Series
SPECIAL DESIGN FEATURES (continued)
Internal Macrocell Library
The mature H4C Series library has been optimized to a set
of the most popular and efficient functions, including several
new scan macros, for the H4CPlus library. All H4CPlus macrocells have been characterized at typical operating conditions for 3.3V and 5.0V operation for the highest modelling
accuracy. A summary of available macrocell types is shown in
Table 2.
Table 2. Summary of Macrocells
Library Functions
Macros
AND
7
NAND
11
OR
7
NOR
11
0.8
0.7
0.6
Ave. Prop. Delay (ns)
• Oscillators
Three different oscillator I/O macros are available on the
H4CPlus Series arrays: non-inverting buffer, clock buffer,
and Schmitt trigger versions. These macros can be configured for ceramic resonators from 32 KHz to above 60 MHz
with quartz crystals.
• JTAG Boundary Scan I/O
The H4CPlus Series I/O cell has JTAG logic built-in to
minimize the impact on performance and gate overhead.
Also, the JTAG control and scan data signals between I/Os
are connected automatically by design.
0.5
0.4
0.3
NAN2 (3.3V)
NAN2B (3.3V)
NAN2H (3.3V)
NAN2 (5V)
NAN2B (5V)
NAN2H (5V)
0.2
0.1
0.0
0
1
2
3
4
5
6
7
8
Fanout
Figure 7. Performance of NAN2 Macros
Several types of macrocells come in high-drive, balanced
slew-rate, or complementary output versions. High-drive versions provide improved performance on nets with high
fanouts. Balanced slew rate versions of macrocells provide
more symmetrical rise and fall slew rates with slightly better
performance than standard macros. For example, Figure 7
shows the NAN2H at 3.3V and 5V to have better performance
than the balanced and standard-drive NAN2.
EXOR, EXNOR
5
A/N, A/O, O/N, O/A
22
Metallized SRAMs
Inverting Buffer
9
Non-Inverting Buffer
8
The metal SRAMs are a family of asynchronous single, dual, and quad-port blocks up to 2304 bits. These RAMs are
gate array based (not diffused), and are an excellent choice
for small memory block applications such as “scratch-pads”
or FIFOs.
3-State Buffer
8
D Flip-Flop
23
Latch
11
Multiplexer
13
Table 4. Sizes of Metallized SRAMs
H4CPlus Series Metallized SRAM Sizes
Decoder
4
Arithmetic
9
Single-Port
Dual-Port
Quad-Port
Misc.
6
8x8
8x9
16x18
8x18
8x18
16x36
16x8
8x36
32x18
16x18
8x72
32x36
16x36
16x9
Table 3. Summary of Special Functions
Special Function
Macros
Metallized SRAMs
24
BIST
5
Analog PLL
10
Internal JTAG
6
32x8
16x18
32x18
16x36
32x36
16x72
64x18
32x9
64x36
32x18
32x36
32x72
H4CPlus_Series
MOTOROLA
5
SPECIAL DESIGN FEATURES (continued)
ARCHITECTURAL FEATURES
The H4CPlus Series offers solutions to many of today's design problems. Increasing application complexities place
higher demands on performance, clock skew management,
testability, I/O capability and workstation based design environments. This section describes some of the special features of the H4CPlus Series that provide solutions to these
problems.
Design for Testability
The time and cost to test an ASIC increases exponentially
as the complexity and size of the ASIC grows. Using a design
for test (DFT) methodology allows large, complex ASICs to be
efficiently and economically tested.
Motorola supports several DFT methodologies, including
ESSD/LSSD scan, JTAG boundary scan, and BIST for memories. To take full advantage of these DFT methodologies,
Motorola has supported the development of a low-cost, highspeed scan tester.
• ESSD/LSSD Scan
Motorola offers Edge Sensitive Scan Design and Level
Sensitive Scan Design (ESSD/LSSD) versions of flip-flops,
latches and other functions in the H4CPlus Series library. Automatic Test Pattern Generation (ATPG) can be performed
using Mentor Graphics’ FastScan ATPG tool.
• JTAG Boundary Scan
Motorola’s JTAG I/O and JTAG control macrocells are designed to conform to the IEEE 1149.1 JTAG boundary scan
specification. The JTAG I/O macrocells are designed to optimize performance and minimize silicon overhead by embedding all sequential and multiplexing logic within the I/O sites
of the array.
• Built-In Self Test
Two versions of Built-in-Self-Test (BIST) are available for
memories: “Pseudo-Random” BIST is relatively easy to implement, requires few gates, and can achieve fault coverage
up to 99%. “Comparator” BIST, on the other hand, is more
complicated to design and requires more gate overhead, but
can achieve 100% fault coverage.
Clock Distribution and Management
ASICs are becoming an integral part of system design and
are regularly found interfacing with multiple chips including
other ASICs, microprocessors and memories. Optimizing
performance of such systems rests on maximizing communication between chips using synchronous interfaces. Clock
skew control and distribution, both on-chip and between
chips, is of critical importance.The Motorola solution to clock
management is to use the clock tree to control skew on-chip
and an analog PLL to control clock skew between ASICs.
MOTOROLA
6
• Clock Distribution
Motorola offers clock tree synthesis during layout to build
balanced clock distribution networks or clock trees. Clock
trees are load-balanced networks that synchronizes clock
signals for all on-chip sequential elements. Clock trees have
a minimal effect on design routability, critical data paths, timing driven layout and floorplanning.
• Analog Phase Locked Loop
APLL (Analog Phase Lock Loop) macros can be used in
applications such as clock synthesis with a worst case VCO
frequency of 70 to 250 MHz (30 to 415 MHz typical). The
APLL is an embedded function and requires 6 (CMOS) or 7
(PECL) pins for VCO control, reference frequency, test, and
power signals. No external filters are needed.
An APLL is diffused into two opposite corners of all
H4CPlus arrays. No area within the core of the array is used
so the APLL does not contribute to the total gate count.
Table 5. Analog PLL Features
Features
Output Frequency (Vco/2)
Frequency multiplication
Phase Error +Jitter
Max. Clock Tree Delay @ 50MHz
Max. Lock Time
Pins
Area
External Components
Analog PLL
35MHz - 125MHz
Yes
±250ps
20ns
<10µs
6 (CMOS), 7 (PECL)
4-5 I/O sites
None
• Diffused SRAMS
User definable SRAM configurations are available using
Motorola’s Felix SRAM compiler. Felix generates several versions of a given SRAM size, each with different performance,
gate counts, and physical configurations.
Table 6. Diffused SRAM Features
Features
Technology
Strobe
Ports
Words
Bits/Words
Max. Bits
Routability
Diffused SRAMs
3V and 5V
Synchronous
Single, Dual
Single: 16 - 4096
Dual: 8 - 1024
Single: 1 - 64
Dual: 1 - 128
Single: 65536 (64K)
Dual: 16384 (16K)
M3 open
H4CPlus_Series
AN INTEGRATED DESIGN SYSTEM SOLUTION
THE OPEN ARCHITECTURE CAD SYSTEM
The Open Architecture CAD System (OACS) offers a
highly versatile and powerful design environment for the
design of Motorola’s H4CPlus Series CMOS arrays. The
OACS integrates several of the industry's most powerful
design tools with selected Motorola high-productivity tools
into standard verilog and EDIF netlist based CAD environments. The information in this data sheet reflects two major
versions of OACS: OACS 4.0 and OACS 3.2M.
OACS 4.0 is Motorola’s point tool CAE solution based on
Cadence Design System’s Concept schematic editor, Synopsys’ synthesis tools, and Cadence’s Verilog XL logic simulator.
OACS 3.2M is Motorola’s framework based CAE solution
using Mentor Graphic’s Falcon Framework. This solution
provides support of Mentor’s design entry tools and QuickSim II logic simulation.
OACS 4.0 and 3.2M Features
Supported Third-Party Design Tools:
• Cadence
- Concept, Verilog XL, Veritime, Verifault,
Gate Ensemble, and Dracula
• Mentor Graphics
- FastScan, DFTAdvisor, ASICVectors Interface,
Falcon Framework, Design Architect,
QuickSim II, QuickPath, and AutoLogic
• Quad Design
- MOTIVE
• Synopsys
- Design Compiler, HDL Compiler, Test
Compiler, and DesignWare
Supported Motorola Design Tools:
• Mustang and MTV automatic test pattern generation
and verification
• TestPAS test vector validation and extraction
• ERC and MARV comprehensive electrical and
manufacturing rules checking
• PrediX floorplanning and routability prediction
• PrediX IPS physical placement
Supported Systems Capabilities:
• Verilog (OACS 4.0) and EDIF 2.0.0 (OACS 3.2M)
backplanes to provide open design environments
• Testability support: ESSD/LSSD scan, JTAG boundary
scan, BIST, and scan synthesis
• Sophisticated delay and timing limits calculations for
accurate simulation and timing analysis
• Estimated and actual (back-annotated) wire
capacitances
• Includes intrinsic, rise/fall time, output pin loading and
distributed RC delays
• Continuous process, temperature, and voltage
variation
• Clock skew management: clock-tree synthesis and
PLL
H4CPlus_Series
• Supports multiple technologies: HDC Series, H4C
Series, H4CPlus Series, and M5C Series
• Supported on HP9000/7XX and SUN 4 SPARC
workstations
The OACS Design Flow
From the conception of your design to its fabrication, you
will see that the OACS design flow is accurate, efficient, and
flexible. The design flow has three basic phases (see Figure
8) design capture and verification, physical design, and postlayout design verification.
• Design Capture and Verification
Pre-layout design is performed by the customer using
OACS tools to develop and simulate the ASIC product. In
addition to schematic capture, designs can be synthesized
using a hardware description language (HDL or VHDL),
equations, or truth tables. The design may be floorplanned to
optimize for density or performance. PrediX, Motorola’s floorplanning tool, allows experimentation with various floorplans
to achieve desired gate density and performance goals. In
addition, PrediX provides to the designer routability information to guide the designer in the floorplanning phase. At this
point in the design phase, delay and timing calculations,
netlist verification, automatic test pattern generation, or static
timing analysis can be performed. Pre-layout simulations use
estimated best/typical/worst-case delays based on gate,
load, slew rate, and floorplan driven estimated RC delays.
Prior to the release of the design to layout, the test vectors
created by the customer must pass specific rules to take full
advantage of Motorola’s production test equipment.
• Physical Design
Physical design, place and route, is performed by Motorola’s Option Development Engineers (ODE). An ODE is dedicated to each option and works directly with the customer to
satisfy their layout requirements. Options such as timing
driven layout and clock tree synthesis are available to optimize silicon performance. Optionally, the user may choose to
use PrediX IPS (Integrated Placement Solution) to perform
macro placement on the target die and leave only the routing
to the ODE. PrediX IPS not only enables the customer to
control the actual placement of the critical paths within the
circuit, but also improve the accuracy of the estimated parasitics and resulting estimated timing over that provided by a
standard PrediX floorplan. Upon completion of the physical
design, back-annotation data of actual wire routing lengths
and RC parasitics is provided to the customer for post-layout
verification.
• Post-Layout Design Verification
The post-layout design verification is performed by the
customer to assure that the physical layout of the design satisfies all performance and timing requirements. Post-layout
simulations use the actual parasitics obtained from the physical layout to provide simulations that represent the circuit’s
behavior in silicon. Following a successful post-layout design
verification and customer sign-off, Motorola begins manufacturing of the ASIC design.
MOTOROLA
7
AN INTEGRATED DESIGN SYSTEM SOLUTION
Behavioral Description
CREATE_BLOCK - Create Directory Structure
DESIGN_INFO - Collect Design Data
Verilog / QuickSim II - Behavioral Simulation
DESIGN CAPTURE AND VERIFICATION
AutoLogic - Logic Synthesis
Design Compiler - Logic Synthesis
Test Compiler / DFTAdvisor - Test Synthesis
ASIC_CONCEPT - Schematic Capture
EDIF Netlists
Design Architect - Schematic Capture
Verilog Netlists
Mentor EDDM Database
EDIFIN - Design Translation
Pinout - I/O Ring Definition
Mentor EDDM Database
ASIC_CONFIG - Design File Creation
Tool Control Files
ERC - Electrical Rules Checking
ERC - Electrical Rules Checking
Creates Netlist if Required
Verilog - Functional Simulation
QuickSim II - Functional Simulation
PrediX -Floorplanning, Placement
& Routability Prediction
Estimated Metal Lengths and Capacitances
DECAL - Estimated Timing
QuickSim II - Estimated Timing Simulation
Invokes Timebase
Estimated Timing Data
ASIC_Verilog - Estimated Timing Simulation
ASIC_MOTIVE - Timing Analysis
ASIC_FastScan / Mustang - ATPG and Fault Grading
Functional Test Patterns
Scan Test Patterns
QuickPath - Timing Analysis
Invokes Timebase
Functional Test Patterns
EDIF Netlist, Layout & Test Vector Data
Gate Ensemble, Dracula - Layout
Actual Metal Lengths and Capacitances
QuickPath - Timing Analysis
Invokes Timebase
DECAL - Back-Annotated Timing
Actual Timing Data
ASIC_MOTIVE - Timing Analysis
ASIC_Verilog - Post-Layout Simulation
QuickSim II - Post Layout Timing Simulation
Invokes Timebase
Release to Motorola
POST-LAYOUT DESIGN
VERIFICATION
Verified Test Patterns
ASIC_RELEASE - Release Files
PHYSICAL
PHYSICAL
DESIGN
DESIGN
TestPAS - Test Pattern Processing
Figure 8. OACS Design Flow
MOTOROLA
8
H4CPlus_Series
PACKAGING
Beyond standard QFPs, Motorola offers two styles of
high performance, surface mounted packages to complement the H4CPlus Series arrays.
OMPAC (Over-Molded Pad Array Carrier)
Motorola has developed a unique plastic pad array carrier
package (OMPAC) to support trends toward PC board space
savings, improved manufacturing yields and better electrical
and thermal performance. OMPAC’s low profile is ideal for
portable products. Its ability to handle large die and pin counts
without coplanarity and skew problems makes it well suited to
CMOS gate arrays.
The OMPAC package primarily consists of a thin, double
metal printed circuit board that is overmolded with plastic. The
integrated circuit is attached to a gold plated die flag on the
substrate with a silver filled epoxy. Electrical connections to
the integrated circuit are made using conventional gold ball
bonding techniques. Etched copper traces extend from the
bond finger connections to plated thruhole vias near the edge
of the package, which connect to an array of solder ball terminals (lands) on the bottom of the substrate (see Figure 10).
Figure 9. Over-Molded Pad Array Carrier (OMPAC)
saves board space and improves manufacturing yields
MOLDING COMPOUND
DIE
DIE ATTACH EPOXY
BT RESIN EPOXY
COPPER FOIL
GOLD PLATED DIE ATTACH
SOLDER MASK
SOLDER BALL
SOLDER MASK
COVERING THERMAL VIA
THERMAL VIA:
COPPER PLATED THROUGH-HOLE
Figure 10. Simplified Cross-Sectional View of OMPAC
MicroCool QUAD FLAT PACK
Drypack
The MicroCool QFP is a new QFP compatible plastic
package with higher heat dissipation capacity. It has a heat
slug attached to a printed circuit board which supports a copper lead frame. The package is supported within an MCR to
maintain pin coplanarity. The MicroCool is a high pin density
package that is capable of meeting the higher power dissipation (up to 3 W, depending on temperature and ambient conditions) and higher performance requirements of the H4CP
Series.
QFPs, MicroCools and the OMPAC packages will be
shipped by Motorola baked and drypacked. The trend towards Surface Mount Technology (SMT) with high density,
thinner packages (which are more sensitive to thermal stress
failure during board mounting) has led Motorola to conduct
numerous studies. The resultant action is a slow bake of
moisture from the SMT package and shipping in drypack
bags to shield the unit from moisture absorption. Units are
baked at 125oC for 24* hours, cooled and placed in a vacuum
sealed drypack with desiccant bags, humidity indicator card,
and lot identification stickers.
*Note: Varies by package type, please consult factory.
H4CPlus_Series
MOTOROLA
9
PACKAGING (Continued)
ARRAY NAME
CDA Array (Die Size) mils/side
# of I/O Cells
# of Programmable Signal or Power
and Ground Pads*
# of Dedicated Power and
Ground Pads*
PACKAGE TYPE
Q
80 QFP (CU)
Q
100 QFP (CU)
Q
128 QFP (CU)
Q
160 QFP (CU)
Q
208 QFP (CU)
Q
240 QFP (CU)
160 MicroCool (CD)
Q
208 MicroCool (CD)
Q
169 OMPAC (CU)
Q
225 OMPAC (CU)
Q
256 OMPAC (CU)
Q
313 OMPAC (CU)
324 CBGA (CU)
Table 7. Package Selection
H4CP011 H4CP028 H4CP048 H4CP075
H4CP109
H4CP146
H4CP178
179
120
239
160
287
208
337
256
391
312
438
360
476
400
100
156
184
212
252
280
304
20
20
32
44
52
64
72
A
A
P
A
A,F
A
P
A
A,F
A,F
A
A,F
A,F
A,F
A,F
A,F
A,F
A,F
A,F
A,F
A,F
A,F
A,F
A
A
A
P
A
P
A
P
A
P
A
P
A
A
A
A
A
P
*Numbers indicate wirebond pads availability
QFP: Plastic Quad Flat Pack (CU) denotes Cavity Up (CD) denotes Cavity Down
MicroCool: QFP-type package with heat slug
OMPAC: Over-Molded Pad Array Carrier, a PGA type package with solder balls instead of pins,
Prototypes for the 169 and 225 OMPAC are supplied in a GTPAC package
CBGA: Ceramic Ball Grid Array, a small footprint hermetic package with superior electrical and excellent thermal performance
A = Available.
F = Flexible power pin assignment.
P = Planned.
Q = Qualified. (Consult factory for qualification status)
Note: The 225 OMPAC package has a number of (System/Core) power combinations, see individual pad to pin tables for
specific power features.
MOTOROLA
10
H4CPlus_Series
THE MACROCELL LIBRARY
The following tables detail the elements which make up the
H4CPlus Series library. The elements are organized into the
following categories: Input/Output, Bidirectional Input and
Output Macros, System Interface Macros, Power/Ground
Macrocells, Internal Macrocells, Memory Blocks (RAM Macrocells).
Gates = equivalent gate count (Internal Macrocells)
System/Core I/O Voltage definition:
5/5 V = 5 Volt System and 5 Volt Core
5/3.3 V = 5 Volt System and 3.3 Volt Core
3.3/5 V = 3.3 Volt System and 5 Volt Core
3.3/3.3 V = 3.3 Volt System and 3.3 Volt Core
CMOS Input Logic
ICI
•
ICN
•
ICNH
•
ICXN
•
•
ICXNH
•
•
ILCI
•
•
ILCN
•
•
ILCNH
•
•
ILSN
•
•
ILSNH
•
•
ISN
•
ISNH
•
ISXN
•
•
ISXNH
•
•
TTL Input Logic
ILTXN
•
ILTXNH
•
ITN
•
ITNH
•
ITSN
•
ITSNH
•
ILTSXN
•
ILTSXNH
•
TTL, Fail-Safe Input Logic
ITNF
•
H4CPlus_Series
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
CMOS/TTL Output Logic
ON2x
•
•
3 •*
•
ON4x
•
•
6 •*
•
ON8x
•
•
12 •*
•
ON16x
•
•
24 •*
•
ON32x
•
•
48 •*
•
ONL2x
•
•
2 •
ONL4x
•
•
3 •
•
ONL8x
•
•
6 •*
•
ONL16x
•
•
12 •*
•
ONL32x
•
•
24 •
•
ONLX2x
•
•
2 •
ONLX4x
•
•
3 •
•
ONLX8x
•
•
6 •*
•
ONLX16x
•
•
12 •*
•
ONLX32x
•
•
24 •
•
ONX2x
•
•
3 •
ONX4x
•
•
6 •
•
ONX8x
•
•
12 •
•
ONX16x
•
•
24 •
•
ONX32x
•
•
48 •
•
TTL, Fail-Safe Output Logic
ON8TF
•
•
12 •
1. See electrical specifications for additional inforx = Suffix such as S2, T, and OD.
* = 3-State with Slew Rate Control
JTAG
Open-Drain
3-State
Drive(mA)1
5.0V
Core
Logic
3.3V
5.0V
System
Logic
Output
Macro
3.3V
JTAG
H4CPlus Series Output Macros
Schmitt
Trigger
Non-Inverting
High Drive
Non-Inverting
Inverting
5.0V
Core
Logic
3.3V
5.0V
3.3V
Input
Macro
System
Logic
H4CPlus Series Input Macros
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MOTOROLA
11
THE MACROCELL LIBRARY (Continued)
12
JTAG
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
JTAG 2
•
•
•
•
3-State
OpenDrain
•
Drive(mA1
•
Core
Logic
CMOS/TTL Output Logic
BON2x
•
•
3
BON4x
•
•
6
BON8x
•
•
12
BON16x
•
•
24
BON32x
•
•
48
BONL2x
•
•
2
BONL4x
•
•
3
BONL8x
•
•
6
BONL16x
•
•
12
BONL32x
•
•
24
BONLX2x
•
•
2
BONLX4x
•
•
3
BONLX8x
•
•
6
BONLX16x
•
•
12
BONLX32x
•
•
24
BONX2x
•
•
3
BONX4x
•
•
6
BONX8x
•
•
12
BONX16x
•
•
24
BONX32x
•
•
48
TTL, Fail-Safe Output Logic
BON8TF
•
•
12
TTL, Extended Range Voltage Output Logic
BONLE8T
•
•
6
BONLE16T
•
•
12
MOTOROLA
JTAG TAP I /O Functions
System Logic
Schmitt
Trigger
Inverting
5.0V
3.3V
•
•
5.0V
5.0V
3.3V
CMOS Input Logic
BICI
•
BICN
•
BICXN
•
BILCI
•
BILCN
•
BILSN
•
BISN
•
BISXN
•
TTL Input Logic
BILTXN
•
BITN
•
BITSN
•
BILTSXN
•
TTL, Fail-Safe Input Logic
BITNF
•
System
Output
Logic
Macro
Core
Logic
3.3V
5.0V
Input
Macro
3.3V
System
Logic
Non-Inverting
Bidirectional Input and Output Macros
•*
•*
•*
•*
•*
•
•
•*
•*
•
•
•
•*
•*
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
JTAG I/O
Macro
3.3V
CMOS Input Logic
TCK
TCKH
TDI
TDOUT
TMS
TRSTB
TCKX
TCKHX
TDIX
TDOUTX
TMSX
TRSTBX
TDOUTLX
•
TCKL
•
TCKHL
•
TDIL
•
TDOUTL
•
TMSL
•
TRSTBL
•
TTL Logic
TCKT
TCKHT
TDIT
TMST
TRSTBT
TCKTX
TCKHTX
TDITX
TMSTX
TRSTBTX
TCKLTX
•
TCKHLTX
•
TDILTX
•
TMSLTX
•
TRSTBLTX
•
5.0V
•
•
•
•
•
•
•
•
•
•
•
•
Core Logic
3.3V
5.0V
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1. See electrical specifications for additional information.
2. For Bidirectional JTAG Macro the O is removed in
the name.
i.e.: BON2T = BN2TJ
x = Suffix such as S2, T, and OD.
* = 3-State with Slew Rate Control
H4CPlus_Series
THE MACROCELL LIBRARY (Continued)
H4CPlus_Series
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Core
Logic
•
•
•
•
•
•
•
•
•
•
•
•
CMTL Output Logic
BOD32TCMT
O32CM
OD32CMT
OD32TCMT
ODX32CM
ODLX32CMT
•
ODL32CMT
•
GTL Output Logic
BON40G
ON20G
ODL20G
•
OD20G
BONL40G
•
ONL20G
•
PCI Output Logic
BONTPC
BONXTPC
BONLXTPC
•
ONPCS2
ONPC
ONTPC
BONLTPC
•
BONTPCS2
ONLPC
•
ONLTPC
•
ONXPC
ONXTPC
ONLXPC
•
ONLXTPC
•
ONTPCS2
Analog PLL
AP1
AP2
APD1
APD2
APT1
APT2
PLLDelay
•
APL1
•
APL2
•
APDL1
•
APDL2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
JTAG
System
Logic
3.3V 5.0V 3.3V 5.0V
•
•
•
•
•
•
•
•
Output
Macro
Differential
3.3V 5.0V 3.3V 5.0V
CMTL Input Logic
BICMD
•
•
ICMD
•
•
ILCMD
•
•
GTL Input Logic
BIGN
•
•
IGI
•
•
•
IGN
•
•
BILGN
•
•
ILGI
•
•
•
ILGN
•
•
IGD
•
•
ILGD
•
•
PCI Input Logic
IPCH
•
•
IPCXN
•
•
IPCXNH
•
•
BILPC
•
•
BIPCXN
•
•
ILPC
•
•
ILPCH
•
•
PECL Input Logic
IPD
•
•
IPN
•
•
ILPD
•
•
ILPN
•
•
IPXD
•
•
IPXN
•
•
Oscillators
OSCPB
•
•
OSCPHB
•
•
OSCPSB
•
•
OSCPBL
•
•
OSCPHBL
•
•
OSCPSBL
•
•
Reference Voltage Macros/Resistors
PUL
•
•
•
•
PDL
•
•
•
•
ENID
•
•
•
•
JTAG
Core
Logic
Differential
System
Logic
Non-Inverting
Input
Macro
Inverting
H4CPlus Series System Interface Macros
•
•
•
•
•
•
•
•
•
MOTOROLA
13
THE MACROCELL LIBRARY (Continued)
#
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
1
2
3
4
INTERNAL MACROS
AND Gates
AND2
2-Input AND Gate
AND2H
2-Input AND Gate, 2X Drive
AND3
3-Input AND Gate
AND3H
3-Input AND Gate, 2X Drive
AND4
4-Input AND Gate
AND4H
4-Input AND Gate, 2X Drive
AND8H
7-Input AND Gate, 2X Drive
NAND Gates
NAN2
2-Input NAND Gate
NAN2H
2-Input NAND Gate, 2X Drive
NAN2B
2-Input NAND Gate, Balanced
NAN3
3-Input NAND Gate
NAN3H
3-Input NAND Gate, 2X Drive
NAN4
4-Input NAND Gate
NAN4H
4-Input NAND Gate, 2X Drive
NAN5
5-Input NAND Gate
NAN5H
5-Input NAND Gate, 2X Drive
6-Input NAND Gate, 2X Drive,
NAN6CH
1X Complementary Output
NAN8H
7-Input NAND Gate, 2X Drive
OR Gates
OR2
2-Input OR Gate
OR2H
2-Input OR Gate, 2X Drive
OR3
3-Input OR Gate
OR3H
3-Input OR Gate, 2X Drive
OR4
4-Input OR Gate
OR4H
4-Input OR Gate, 2X Drive
OR8H
7-Input OR Gate, 2X Drive
NOR Gates
NOR2
2-Input NOR Gate
NOR2H
2-Input NOR Gate, 2X Drive
NOR2B
2-Input NOR Gate, Balanced
NOR3
3-Input NOR Gate
NOR3H
3-Input NOR Gate, 2X Drive
NOR4
4-Input NOR Gate
NOR4H
4-Input NOR Gate, 2X Drive
NOR5
5-Input NOR Gate
NOR5H
5-Input NOR Gate, 2X Drive
6-Input NOR Gate, 2X Drive,
NOR6CH
1X Complementary Output
NOR8H
7-Input NOR Gate, 2X Drive
EXCLUSIVE OR & EXCLUSIVE NOR Gates
EXNORA
2-Input EXNOR, Unbuffered Inputs
EXNOR3H
3-Input Exclusive NOR, 2X Drive
2-Input Exclusive OR, Unbuffered
EXORA
Inputs
EXOR3H
3-Input Exclusive OR, 2X Drive
EXOR4H
4-Input Exclusive OR, 2X Drive
AND/NOR, AND/OR, OR/NAND, & OR/AND Gates
2-Input AND + 2-Input NOR, into
ANDOI22
2-Input NOR
2-Input AND+2-Input NOR,
ANDOI22H
→2-Input NOR 2X Drive
2-Input AND, 1-Wide,→2-Input OR,
AO21H
2X Drive
2-Input AND, 2-Wide, into 2-Input OR,
AO22H
2X Drive
MOTOROLA
14
Gates
#
2
2
2
3
3
3
6
5
6
7
1
2
2
2
3
2
4
4
5
8
9
10
11
12
13
14
15
16
6
17
7
18
2
2
2
3
3
3
8
19
1
2
2
2
4
4
4
4
5
6
20
21
22
1
2
3
4
5
6
7
8
7
9
3
8
3
1
2
8
10
3
3
4
5
6
4
3
7
8
INTERNAL MACROS
Gates
AND/NOR, AND/OR, OR/NAND, & OR/AND Gates (Cont’)
AO321H
3,2,1-input AND-OR, 2X Drive
5
AO4321H
4,3,2,1-input AND-OR, 2X Drive
8
AOI21
2-Input AND, 1-Wide,→2-input NOR
2
2-Input AND, 1-Wide, → 2-input NOR,
AOI21H
3
2X Drive
AOI211
2-Input AND, 1-Wide,→3-input NOR
2
2-Input AND, 1-Wide, → 3-input NOR,
4
AOI211H
2X Drive
AOI22
2-Input AND, 2-Wide,→2-input NOR
2
2-Input AND, 2-Wide,→2-input NOR,
AOI22H
4
2X Drive
2-Input OR, 1-Wide,→2-input AND,
3
OA21H
2X Drive
2-Input OR, 2-Wide,→2-input AND,
3
OA22H
2X Drive
OAI21
2-Input OR, 1-Wide,→2-input NAND
2
2-Input OR, 1-Wide,→2-input NAND,
OAI21H
3
2X Drive
OAI211
2-Input OR, 1-Wide,→3-input NAND
2
2-Input OR,1-Wide,→3-input NAND,
4
OAI211H
2X Drive
OAI22
2-Input OR, 2-Wide,→2-input NAND
2
2-Input OR, 2-Wide, → 2-input NAND,
OAI22H
4
2X Drive
2-Input OR + 2-Input NAND,→2-Input
3
ONDAI22
NAND
2-Input OR + 2-Input NAND,→ 2-Input
4
ONDAI22H
NAND, 2X Drive
Inverting Buffers
INV
Inverter
1
Inverter, Balanced
1
INVB
(Symmetrical Rise & Fall)
INV2
2-Inverters in parallel
1
2-Inverters in parallel, Balanced
INV2B
2
(Symmetrical Rise & Fall)
INV4
4-Inverters in parallel
2
4-Inverters in parallel, Balance
4
INV4B
(Symmetrical Rise & Fall)
INV8
7-Inverters in parallel
4
7-Inverters in parallel, Balanced
INV8B
8
(Symmetrical Rise & Fall)
Inverted Buffer (used to drive internal
INVX
-logic from an I/O Site)
Non-Inverting Buffers
BUF
1X drive Buffer
1
BUF2
2X drive Buffer
2
2X drive Buffer, Balanced
BUF2B
3
(Symmetrical Rise & Fall)
BUF4
4X drive Buffer
3
4X drive Buffer, Balanced
5
BUF4B
(Symmetrical Rise & Fall)
BUF8
8X drive Buffer
5
8X drive Buffer, Balanced
BUF8B
9
(Symmetrical Rise & Fall)
Non-Inverting Buffer (used to drive
-BUFX
internal logic from an I/O Site)
3
H4CPlus_Series
THE MACROCELL LIBRARY (Continued)
#
INTERNAL MACROS
1 TBUF
2 TBUFH
3 TBUFP
4 TBUFPH
5 INVT
6 INVTH
7 INVTP
8 INVTPH
1 DFF1A
2 DFF4A
3 DFFGLP
4 DFFP
5 DFFPH
6 DFFLPA
7 DFFLPAH
8 DFFRP
9 DFFRPH
10 DFFRLP
11
12
13
14
15
16
17
DFFRLPH
DFFRSLPB
DFFRSPHB
DFFSCH
DFFSCAH
DFFSP
DFFSPH
18 DFFSLP
19 DFFSLPH
20 DFFSRPA
21 DFFSRLPA
22 DFFSSP
23 DFFSSLP
1
2
3
4
LATN
LATNH
LATP
LATPH
5 LATRN
6 LATRNH
7 LATRP
8
9
10
11
LATRPH
LAT4TH
LSSD1AH
SRLSSD1H
H4CPlus_Series
3-State Buffers
3-state Buffer, Active Low Enable
3-state Buffer, Active Low Enable,
2X Drive
3-state Buffer, Active High Enable
3-state Buffer, Active High Enable,
2X Drive
Inverting 3-state Buffer, Active Low
Enable
Inverting 3-state Buffer, Active Low
Enable, 2X Drive
Inverting 3-state Buffer, Active High
Enable
Inverting 3-state Buffer,
Active High Enable, 2x Drive
D Type Flip-Flops
Scan D Flip-Flop
4-Bit Scan D Flip-Flop
D Flip-Flop, Multiplexed (or Scan)
Input with HOLD function
D Flip-Flop
DFFP, 2X Drive
D Flip-Flop, Multiplexed (or Scan)
W/Unbuffered Input/ Clock
DFFLP, 2X Drive
D Flip-Flop with Reset
DFFRP, 2X Drive
D Flip-Flop W/Reset, Multiplexed
(or Scan) Input
DFFRLP, 2X Drive
D Flip-Flop w/Set and Reset
D Flip-Flop w/Set and Reset, 2X Dr.
DFFSC, 2X Drive
DFFSCA, 2X Drive
D Flip-Flop with Set
DFFSP, 2X Drive
D Flip-Flop w/Set, Multiplexed
(or Scan) Input
DFFSLP, 2X Drive
D Flip-Flop with Synchronous Reset
D Flip-Flop, Multiplexed (or Scan)
Input with Synchronous Reset
D Flip-Flop with Synchronous Set
D Flip-Flop, Multiplexed (or Scan)
Input with Synchronous Set
Latches
D-Type Latch, Neg Gate Latched
LATN, 2X Drive
D-Type Latch, Pos Gate Latched
LATP, 2X Drive
D-Type Latch W/Reset, Neg Gate
Latched
LATRN, 2X Drive
D-Type Latch W/Reset, Pos Gate
Latched
LATRP, 2X Drive
LAT4TH, 2X Drive
LSSD1A, 2X Drive
SRLSSD1, 2X Drive
Gates
4
5
4
5
2
3
3
4
15
48
13
8
8
8
9
8
10
11
11
14
10
18
20
8
10
12
12
9
12
9
12
5
6
5
6
6
7
6
7
23
14
13
#
INTERNAL MACROS
Gates
Multiplexers
1 MUX2A
2-1 Multiplexer, 1X Drive
3
2 MUX2H
2-Input Multiplexer, 2X Drive
3
3 MUX2IH
MUX2I, 2X Drive
3
4 MUX4H
4-Input Multiplexer, 2X Drive
7
5 MUX41A
Four 2-1 MUX with Common Select
12
6 MUX41AH
MUX41A, 2X Drive
14
7 MUX8AH
7-Input Multiplexer, 2X Drive
18
4-Input Multiplexer W/individual
8 MX41
5
Selects
9 MX41H
MX41, 2X Drive
6
6-Input Multiplexer W/Individual
8
10 MX61
Selects
11 MX61H
MX61, 2X Drive
9
8-Input Multiplexer W/Individual
12 MX81
10
Selects
13 MX81H
MX81, 2X Drive
12
Decoders
1 DEC4H
DEC4, 2X Drive
9
1 of 4 Decoder, Active High Outputs,
2 DEC4AH
14
2X Drive
1 of 8 Decoder with Enable, Active Low
3 DEC1OF8
16
Outputs
1 of 8 Decoder with Enable, Active
30
4 DEC8AH
High Outputs, 2X Drive
Arithmetic Circuits
1 AD4FULA
4-Bit Full Adder, 2X Drive
40
4-Bit Full Adder with Propagate &
2 AD4PG
94
Generate, 2X Drive
3 ADFULH
ADFUL, 2X Drive
10
4 ADFULHA
Full Adder, 2X Drive
10
5 ADHALFH
ADHALF, 2X Drive
6
6 ECOMP4
4-Bit Equality Comparator
16
7 LACG4
4-bit Look-Ahead-Carry Generator
32
8 MCOMP4
4-bit Magnitude Comparator
35
9 SBHALF
Half Subtracter
6
Miscellaneous
1 DCR4H
4-Bit Decrementer, 2X Drive
28
2 DLY8
7-Stage Inverter Delay
4
3 INC4H
4-Bit Incrementer, 2X Drive
28
4 MUL8X8
8X8 -Bit Unsigned Multiplier
1106
5 ROT8A
7-Bit Rotate, 1X Drive
54
6 SHIFT8
7-Bit Shift Register
45
BIST Soft Macros
Address Counter Cell for Simplified
1 ADDR_CELL
20
BIST
2 DATA_CELL Pattern generator & Signature Analysis 27
3 COMPACELL Address Cell for Comparator BIST
34
4 COMPDCELL Data Cell for Comparator BIST
54
COMP
5
BIST Controller for Comparator BIST
780
BISTCNTL
JTAG Control Macro Functions
1 BPREG
1-Bit Bypass Register
10
2 ENSCANI
Enable Boundary scan Macro
20
32-Bit device Identification Code
3 IDREG
256
Register
4 MC_IREG
1-Bit Instruction Register (Soft Macro)
25
5 MC_IREG4
4-Bit Instruction Register (Soft Macro) 124
TAP Controller (FIRM Macro) Fixed
6 FMC_TAPCB
276
Placement which effects Routing
MOTOROLA
15
THE MACROCELL LIBRARY (Continued)
#
1
2
3
4
5
6
7
8
9
10
INTERNAL MACROS
Miscellaneous JTAG Macro
B-S Register Clock Driver
B-S Register Clock Driver
B-S Register Clock Driver
B-S Register Enable Scan Macro
B-S Reg. input Mode Control Driver
B-S Reg. Output Mode Control Driver
Clock Net ISO and Test Data Resync
B-S Register Shift Driverr
B-S Register Test Data Buffer
B-S Register Update Driver
CKDRMID
CKDRCC1
CKDRCC2
ENSCANJ
IMCDR
OMCDR
ISOR
SHDR
TDBUF
UDDR
MEMORY BLOCKS
Gates
#
0
0
0
0
0
0
0
0
0
0
8
9
10
1
2
3
4
5
6
7
8
9
10
11
12
MEMORY BLOCKS
#
1
2
3
4
5
6
7
Name
Gate
Count
Ram Size
Single-Port RAM’s (Low Power)
RSB8X8
8 word X 8bit
RSB8X18
8 word X 18bit
RSB16X8
16 word X 8bit
RSB16X18
16 word X 18bit
RSB16X36
16 word X 36 bit
RSB32X8
32 word X 8bit
RSB32X18
32 word X 18 bit
198
440
342
760
1440
630
1400
1
2
3
4
Name
Gate
Count
Ram Size
Single-Port RAM’s (Low Power)(Cont’)
RSB32X36
32 word X 36 bit
RSB64X18
64 word X 18 bit
RSB64X36
64 word X 36 bit
Dual-Port RAM’s (High Speed)
RDB8X9
8 word X 9 bit
RDB8X18
8 word X 18 bit
RDB8X36
8 word X 36 bit
RDB8X72
8 word X 72 bit
RDB16X9
16 word X 9 bit
RDB16X18
16 word X 18 bit
RDB16X36
16 word X 36 bit
RDB16X72
16 word X 72 bit
RDB32X9
32 word X 9 bit
RDB32X18
32 word X 18 bit
RDB32X36
32 word X 36 bit
RDB32X72
32 word X 72 bit
Quad-Port RAM’s
RQB16X18
16 word X 18 bit
RQB16X36
16 word X 36 bit
RQB32X18
32 word X 18 bit
RQB32X36
32 word X 36 bit
2660
2680
5092
356
608
1112
2156
725
1193
2129
4050
1400
2300
4100
7798
2200
3766
4762
7738
MACROCELL EXAMPLES
INPUT MACROCELLS
5/5 V
3.3/3.3 V
Inverting CMOS Inputs and Bidirectional Input
(3.3 V and 5 V System/Core Voltages)
SECTIONS USED
ICI/ILCI
BICI
MACRO
1/0
1/0
Rev. 1.09
OUTPUTS/INPUTS
ICI/ILCI
BICI
DI / PAD,IC
DI / BC
MACRO
INPUT CAP.
ICI/ILCI
BICI
PAD: 5.29pF
BC: 0.39pF
ICI/ILCI
Function Table
PAD
L
H
DI
H
L
XXX
PAD
DI
XX
MACRO
ICI/BICI
ILCI
IC
BICI
DI
BC
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5/5 V
Sym
Parameter
FO=0
FO=2
FO=8 K (ns/pF)
Rev. 1.09
3.3/3.3 V
FO=0
FO=2
0.23
0.20
0.20
0.15
0.24
0.22
0.23
0.18
ICI/BICI
tPLH
tPHL
tr
tf
Propagation Delay,
PAD to DI
Output Rise Time, DI
Output Fall Time, DI
0.18
0.16
0.18
0.17
0.19
0.18
0.20
0.19
0.23
0.22
0.27
0.25
FO=8
K (ns/pF)
ILCI
0.12
0.15
0.24
0.18
0.29
0.27
0.33
0.25
0.15
0.18
0.33
0.24
Capacitance per fanout = 0.05 pF (metal capacitance is not included).
MOTOROLA
16
H4CPlus_Series
MACROCELL EXAMPLES (Continued)
OUTPUT MACROCELLS
SECTIONS USED
All
MACRO
0/1
Rev. 1.09
OUTPUTS/INPUTS
All
PAD / DO
MACRO
INPUT CAP.
ON2,ONL2
ON8,ONL8
ONX2
ONX8
ONLX2
ONLX8
DO: 0.28pF
DO: 0.56pF
DO: 0.40pF
DO: 0.47pF
DO: 0.30pF
DO: 0.75pF
Function Table
DO
L
H
PAD
L
H
ONn / ONXn / ONLXn / ONLn
DO
XX
MACRO
ONn
ONXn
ONLXn
ONLn
5/5 V
5/3.3 V
3.3/5 V
3.3/3.3 V
n=2, 4, 8, 16
Non-Inverting Output Buffers
(3.3 V and 5 V System/Core Voltages)
XXX
PAD
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5/5 V
Sym
Parameter
pF=0
pF=50 pF=100 K (ns/pF)
Rev. 1.09
3.3/5 V
pF=0
pF=50
ON2
tPLH
tPHL
tr
tf
Propagation Delay,
DO to PAD
tPLH
tPHL
tr
tf
Propagation Delay,
DO to PAD
Output Rise Time, PAD
Output Fall Time, PAD
Output Rise Time, PAD
Output Fall Time, PAD
pF=100
K (ns/pF)
ONLX2
0.41
0.38
0.22
0.23
4.92
6.27
10.61
11.80
9.43
12.15
21.00
23.37
ON8
0.09
0.12
0.21
0.23
0.89
0.35
0.36
0.18
4.85
4.47
9.34
9.55
8.80
8.59
18.33
18.92
ONLX8
0.08
0.08
0.18
0.19
0.43
0.75
0.21
0.46
1.74
2.03
3.13
3.29
3.05
3.32
6.06
6.11
0.03
0.03
0.06
0.06
0.77
0.68
0.53
0.48
2.19
1.87
3.46
2.79
3.61
3.07
6.40
5.10
0.03
0.02
0.06
0.05
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5/3.3 V
Sym
Parameter
pF=0
pF=50 pF=100 K (ns/pF)
Rev. 1.09
3.3/3.3 V
pF=0
pF=50
ONX2
tPLH
tPHL
tr
tf
Propagation Delay,
DO to PAD
tPLH
tPHL
tr
tf
Propagation Delay,
DO to PAD
Output Rise Time, PAD
Output Fall Time, PAD
Output Rise Time, PAD
Output Fall Time, PAD
H4CPlus_Series
pF=100
K (ns/pF)
ONL2
0.70
0.86
0.49
0.54
5.19
6.56
10.87
12.10
9.69
12.27
21.26
23.66
ONX8
0.09
0.11
0.21
0.23
0.55
0.53
0.32
0.31
6.95
7.58
14.63
14.40
13.35
14.63
28.93
28.49
ONL8
0.13
0.14
0.29
0.28
1.06
1.15
0.70
0.58
2.49
2.72
3.57
3.40
3.92
4.29
6.43
6.23
0.03
0.03
0.06
0.06
0.57
0.95
0.25
0.56
2.41
2.49
4.28
3.98
4.25
4.03
8.32
7.41
0.04
0.03
0.08
0.07
MOTOROLA
17
MACROCELL EXAMPLES (Continued)
CMTL Differential Input and Bidirectional Input
(3.3 V and 5 V Core Voltages)
1/0
1/0
MACRO
Function Table
PAD/BC
L
H
L
H
Rev. 1.09
OUTPUTS/INPUTS
ICMD/ILCMD
BICMD
DI / PAD,PAD2,IC,IC2
DI / BC,BC2
MACRO
INPUT CAP.
ICMD
BICMD
PAD,PAD2: 5.06pF
BC,BC2: 0.130F
PAD2/BC2
H
L
L
H
DI
L
H
ND
ND
ND = Not Defined
ICMD / ILCMD
XXX
PAD
XXX
PAD2
IC
DI
XX
SECTIONS USED
ICMD
BICMD
ILCMD
IC2
BICMD
XX
MACRO
ICMD/ILCMD
BICMD
5/5 V
3/3 V
BC2
DI
BC
CMTL SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5/5 V
Sym
Parameter
FO=0
FO=2
Propagation Delay,
PAD,PAD2 to DI
0.88
0.83
0.08
0.05
0.89
0.85
0.08
0.06
FO=8
Rev. 1.09
3/3 V
K (ns/pF)
FO=0
FO=2
0.11
0.15
0.04
0.12
1.22
1.27
0.09
0.09
1.24
1.29
0.10
0.11
ICMD/BICMD
tPLH
tPHL
tr
tf
Output Rise Time, DI
Output Fall Time, DI
FO=8
K (ns/pF)
ILCMD
0.93
0.89
0.10
0.10
1.29
1.34
0.14
0.16
0.17
0.19
0.13
0.16
NAN2
INTERNAL MACROCELLS (COMBINATIONAL)
2-Input NAND Gate, 1X Drive
(3.3 V and 5 V Core Voltages)
MACRO
EQUIV. GATES
NAN2
1
MACRO
Rev. 1.09
OUTPUTS/INPUTS
NAN2
X / A,B
MACRO
INPUT CAP.
NAN2
A,B: 0.05pF
FUNCTION TABLE
A
B
X
L
L
H
L
H
H
H
L
H
H
H
L
A
NAN2
X
B
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5V
Sym
Parameter
FO=0
FO=2
FO=8
K (ns/pF)
NAN2
0.12
0.21
0.45
0.82
tPLH
Propagation Delay,
A to X
0.27
0.38
0.72
1.14
tPHL
tPLH
0.17
0.25
0.49
0.82
Propagation Delay,
B to X
0.24
0.36
0.70
1.13
tPHL
Output Rise Time, X
0.23
0.47
1.20
2.42
tr
Output Fall Time, X
0.20
0.40
0.99
1.96
tf
Rev. 1.09
FO=0
3.3 V
FO=2
FO=8
0.17
0.34
0.22
0.31
0.29
0.22
0.29
0.49
0.34
0.46
0.63
0.47
0.63
0.94
0.68
0.91
1.66
1.23
K (ns/pF)
1.15
1.50
1.15
1.50
3.44
2.54
Fanout (FO) capacitance does not include estimated metal lengths (each FO = 0.06pF).
MOTOROLA
18
H4CPlus_Series
MACROCELL EXAMPLES (Continued)
INTERNAL MACROCELLS (SEQUENTIAL)
DFFSCH
D Flip-Flop with Scan Latch 2X Drive
(3.3 V and 5 V Core Voltages)
MACRO
EQUIV. GATES
DFFSCH
18
MACRO
DFFSCH
Rev. 1.09
OUTPUTS/INPUTS
Q,QB,SQ /
D,CK,SDI,BCLK,ACLK,EN
MACRO
INPUT CAP.
DFFSCH
ACLK,BCLK,EN: 0.10pF
CK: 0.05pF
D: 0.16pF
SDI: 0.20pF
FUNCTIONAL DESCRIPTION:
This macro consists of a D type Flip-Flop with Q feedback
(hold) capability. It allows scan data to be muxed into the slave
stage and contains a separate scan latch for storing scan data
independent of Q. CK clocks the Flip-Flop, BCLK controls latching scan data into the slave stage and ACLK controls the final
scan data latch.
FUNCTION TABLE
D
EN
CK
SDI
BCLK
ACLK
Q
QB
SQ
X
X
L
X
L
L
Q
QB
SQ
Notes
1
X
L
/
X
L
L
Q
QB
SQ
2
L
H
/
X
L
L
L
H
SQ
3
H
H
/
X
L
L
H
L
SQ
3
X
X
L
X
L
H
Q
QB
QB
4
X
X
L
L
H
L
H
L
SQ
5
X
X
L
H
H
L
L
H
SQ
5
X
X
L
L
H
H
H
L
L
6
X
X
L
H
H
H
L
H
H
6
D
CK
Q
QB
DFFSCH
SQ
SDI
BCLK
ACLK
EN
1. No Clock 2. Active Clock, disabled 3. Active Clock, enabled
4. Scan-out Clock applied 5. Scan-in Clock applied 6. Flush or Ring-oscillate
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5V
Sym
Parameter
FO=0
FO=2
FO=8
DFFSCH
0.67
0.75
1.00
tPLH
Propagation Delay,
ACLK to SQ
0.66
0.73
0.96
tPHL
tPLH
0.66
0.69
0.77
Propagation Delay,
BCLK to Q
0.88
0.93
1.08
tPHL
tPLH
1.13
1.16
1.23
Propagation Delay,
BCLK to QB
1.29
1.33
1.45
tPHL
tPLH
1.83
1.91
2.16
Propagation Delay,
BCLK to SQ
1.85
1.93
2.16
tPHL
tPLH
0.96
0.98
1.06
Propagation Delay,
CK to Q
1.09
1.14
1.28
tPHL
tPLH
1.34
1.37
1.44
Propagation Delay,
CK to QB
1.60
1.64
1.76
tPHL
tPLH
2.18
2.26
2.51
Propagation Delay,
CK to SQ
2.28
2.35
2.58
tPHL
tPLH
0.56
0.58
0.66
Propagation Delay,
SDI to Q
0.75
0.80
0.94
tPHL
tPLH
0.96
0.98
1.05
Propagation Delay,
SDI to QB
1.12
1.16
1.28
tPHL
tPLH
1.68
1.75
1.98
Propagation Delay,
SDI to SQ
1.68
1.76
2.01
tPHL
Output Rise Time, Q
0.29
0.35
0.52
tr
Output Fall Time, Q
0.44
0.49
0.67
tf
Output Rise Time, QB
0.26
0.32
0.49
tr
Output Fall Time, QB
0.31
0.36
0.53
tf
Output Rise Time, SQ
0.20
0.44
1.17
tr
Output Fall Time, SQ
0.18
0.30
0.65
tf
Rev. 1.09
K (ns/pF)
FO=0
3.3 V
FO=2 FO=8
0.83
0.76
0.26
0.48
0.23
0.41
0.83
0.76
0.27
0.48
0.23
0.41
0.83
0.76
0.25
0.48
0.24
0.40
0.76
0.82
0.57
0.59
0.56
0.55
2.44
1.17
0.98
0.90
0.95
1.32
1.74
1.80
2.77
2.62
1.38
1.62
2.03
2.26
3.28
3.25
0.81
1.13
1.54
1.58
2.40
2.57
0.38
0.59
0.32
0.36
0.25
0.24
1.09
0.99
0.99
1.39
1.77
1.85
2.89
2.72
1.42
1.68
2.06
2.31
3.39
3.34
0.85
1.20
1.58
1.63
2.49
2.69
0.46
0.66
0.40
0.43
0.60
0.39
1.44
1.27
1.10
1.58
1.87
2.01
3.23
2.99
1.53
1.88
2.16
2.46
3.74
3.61
0.96
1.39
1.67
1.78
2.77
3.03
0.71
0.89
0.64
0.63
1.63
0.81
K (ns/pF)
1.16
0.92
0.36
0.65
0.33
0.52
1.16
0.92
0.37
0.64
0.33
0.52
1.16
0.92
0.36
0.65
0.32
0.52
0.92
1.16
0.82
0.75
0.79
0.68
3.44
1.40
Capacitance per fanout = 0.05 pF (metal capacitance is not included).
H4CPlus_Series
MOTOROLA
19
MACROCELL EXAMPLES (Continued)
CMOS TIMING REQUIREMENTS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
Sym
Parameter
Rev. 1.09
5V
3.3 V
Minimum Requirement
Minimum Requirement
DFFSCH
tsu
Set Up Time, BCLK to ACLK
1.70
2.59
tsu
Set Up Time, CK to ACLK
1.84
2.74
tsu
Set Up Time, SDI to ACLK
1.67
2.50
tsu
Set Up Time, SDI to BCLK
1.33
1.93
tsu
Set Up Time, D to CK
0.15
0.34
tsu
Set Up Time, EN to CK
0.43
0.66
th
Hold Time, ACLK to BCLK
-1.21
-1.71
th
Hold Time, ACLK to CK
-1.21
-1.87
th
Hold Time, ACLK to SDI
-1.08
-1.58
th
Hold Time, BCLK to CK
-1.07
-1.65
th
Hold Time, BCLK to SDI
0.00
-0.01
th
Hold Time, CK to BCLK
-1.05
-1.51
th
Hold Time, CK to D
0.43
0.57
th
Hold Time, CK to EN
0.23
0.31
trec
Recovery Time, CK to ACLK
1.97
2.93
trec
Recovery Time, ACLK to CK
-1.49
-2.20
tw
Pulse Width, ACLK(H)
0.43
0.65
tw
Pulse Width, BCLK(H)
1.28
1.89
tw
Pulse Width, CK(L)
0.59
0.94
tw
Pulse Width, CK(H)
1.52
2.20
FUNCTIONAL DIAGRAM: DFFSCH
C
CKB
Q
*
EN
CKB
CKB
C
C
ACKB
D
C
QB
BC
CKB
SQ
BCKB
AC
CK
C
*
AC
*
BC
CKB
ACKB
ACLK
ACKB
AC
BCLK
BCKB
BC
*2X for DFFSCH
SDI
Note: Outputs have balanced drive.
MOTOROLA
20
H4CPlus_Series
MACROCELL EXAMPLES (Continued)
METALLIZED SRAM BLOCKS
• Random Access Memories
Motorola offers 26 different building blocks that can be
used to construct Single-, Dual-, and Four-Port memories. A
comprehensive guide to using these blocks and their performance is shown in the H4CPlus Series Design Reference
Guide. (H4CPDM/D)
• Multiple Memory Blocks
It is possible to combine two or more memory blocks to
create larger memory blocks. When multiple blocks are used,
the user is responsible for creating the external decoder logic
needed. The maximum number of SRAM blocks on an array
is restricted to 16, depending on array/SRAM sizes.
• Array Sizing
To choose an array into which a design with SRAM will fit,
two considerations must be evaluated: the physical size/layout of the SRAM or SRAMs, and the gate utilization.
RDBXXxXX
RDBXXxXX -High Speed Dual-Port SRAM
Equivalent Gates: see below
Pin names:
A_A(0-m) - address bus for Port A
A_B(0-m) - address bus for Port B
DIN_A(0-n) -input data
WB_A - Write enable bus for Port A
DO_B(0-n) - data output determined by address bus, Port B
Size
(Words X Bits)
8X9
8X18
8X36
8X72
DO_B(0-n)
A_A(0-m)
A_B(0-m)
DIN_A(0-n)
WB_A(0-n)
Port A Input
Capacitance
Size
Total
Name
(Columns X Rows) Gate Count Per Address Line
8-WORD BLOCK
RDB8X9
13X14
356
RDB8X18
22X14
608
0.15 pF
RDB8X36
40X14
1112
RDB8X72
77X14
2156
Port A Input
Capacitance
WB_A Line
Port B Input
Capacitance
Per Address Line
0.18 pF
0.15 pF
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5.0 V
Sym
Parameter
FO=0
FO=2
FO=8 K (ns/pF)
RDB8X9
tPLH
1.75
1.83
2.07
0.81
Propagation Delay,
A0-A2 to DO0-DO8
tPHL
1.92
1.99
2.20
0.68
tPLH
1.47
1.55
1.80
0.81
Propagation Delay,
DIN0-DIN8 to DO0-DO8
tPHL
2.11
2.18
2.39
0.70
tPLH
2.34
2.43
2.68
0.83
Propagation Delay,
RWB0-RWB8 to DO0-DO8
tPHL
2.40
2.47
2.69
0.71
tr
Output Rise Time, DO0-DO8
0.18
0.43
1.19
2.52
tf
Output Fall Time, DO0-DO8
0.41
0.51
0.82
1.02
RDB8X18
tPLH
1.84
1.93
2.17
0.82
Propagation Delay,
A0-A2 to DO0-DO17
tPHL
2.07
2.14
2.35
0.70
tPLH
1.47
1.55
1.80
0.81
Propagation Delay,
DIN0-DIN17 to DO0-DO17
tPHL
2.11
2.18
2.38
0.70
tPLH
2.48
2.56
2.81
0.82
Propagation Delay,
RWB0-RWB17 to DO0-DO17
tPHL
2.64
2.70
2.89
0.63
tr
Output Rise Time, DO0-DO17
0.18
0.43
1.19
2.52
tf
Output Fall Time, DO0-DO17
0.66
0.75
1.00
0.84
Rev. 1.09
FO=0
3.3 V
FO=2
FO=8
2.67
2.94
2.51
3.03
3.74
3.54
0.35
0.48
2.79
3.02
2.63
3.12
3.86
3.63
0.72
0.61
3.14
3.25
2.98
3.38
4.20
3.88
1.83
0.98
1.20
0.77
1.17
0.87
1.13
0.85
3.70
1.25
2.92
2.99
2.51
3.03
3.99
3.77
0.40
0.42
3.04
3.08
2.63
3.11
4.11
3.85
0.75
0.56
3.39
3.34
2.98
3.37
4.46
4.09
1.82
0.99
1.18
0.88
1.17
0.87
1.16
0.80
3.56
1.43
K (ns/pF)
Capacitance per fanout = 0.06 pF (metal capacitance is not included).
H4CPlus_Series
MOTOROLA
21
MACROCELL EXAMPLES (Continued)
CMOS SWITCHING CHARACTERISTICS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
5.0 V
Sym
Parameter
FO=0
FO=2
FO=8 K (ns/pF)
RDB8X36
tPLH
2.10
2.19
2.45
0.87
Propagation Delay,
A0-A2 to DO0-DO35
tPHL
2.32
2.39
2.59
0.66
tPLH
1.47
1.56
1.80
0.81
Propagation Delay,
DIN0-DIN35 to DO0-DO35
tPHL
2.11
2.18
2.39
0.70
tPLH
2.89
2.98
3.23
0.83
Propagation Delay,
RWB0-RWB35 to DO0-DO35
tPHL
2.94
3.01
3.23
0.72
tr
Output Rise Time, DO0-DO35
0.20
0.45
1.21
2.52
tf
Output Fall Time, DO0-DO35
0.62
0.71
0.97
0.86
RDB8X72
tPLH
2.28
2.36
2.61
0.84
Propagation Delay,
A0-A2 to DO0-DO71
tPHL
2.62
2.69
2.88
0.65
tPLH
1.48
1.56
1.80
0.81
Propagation Delay,
DIN0-DIN71 to DO0-DO71
tPHL
2.11
2.18
2.39
0.70
tPLH
3.44
3.52
3.76
0.81
Propagation Delay,
RWB0-RWB71 to DO0-DO71
tPHL
3.47
3.53
3.73
0.66
tr
Output Rise Time, DO0-DO71
0.37
0.61
1.31
2.33
tf
Output Fall Time, DO0-DO71
0.65
0.73
1.00
0.89
Rev. 1.09
FO=0
3.3 V
FO=2
FO=8
3.43
3.28
2.51
3.03
4.52
4.40
0.56
1.35
3.54
3.37
2.63
3.11
4.64
4.48
0.90
1.43
3.88
3.65
2.98
3.37
5.00
4.72
1.91
1.65
1.12
0.91
1.17
0.87
1.19
0.80
3.37
0.73
3.82
3.72
2.52
3.02
5.38
4.79
0.67
0.82
3.93
3.80
2.64
3.11
5.49
4.87
0.97
0.93
4.26
4.04
2.99
3.37
5.83
5.11
1.87
1.25
1.11
0.80
1.17
0.87
1.12
0.80
3.00
1.07
K (ns/pF)
Capacitance per fanout = 0.06 pF (metal capacitance is not included).
TIMING REQUIREMENTS
(Input Edge Rate tr,tf=1.00ns) TJ= 25.0oC (Nominal) all units are in ns.
Abbr.
Parameter
Set Up Time,
tDSU
Set Up Time,
tAWB
Set Up Time,
tASU
Hold Time,
tDH
Hold Time,
tDH
Pulse Width
tWP
MOTOROLA
22
DINA(n) to WBA (WL = 9)
DINA(n) to WBA (WL = 18)
DINA(n) to WBA (WL = 36)
DINA(n) to WBA (WL = 72)
AA(n) to WBA (WL = 9)
AA(n) to WBA (WL = 18)
AA(n) to WBA (WL = 36)
AA(n) to WBA (WL = 72)
AA(n) to WBA (WL = 9)
AA(n) to WBA (WL = 18)
AA(n) to WBA (WL = 36)
AA(n) to WBA (WL = 72)
WBA to DINA(n) (WL = 9)
WBA to DINA(n) (WL = 18)
WBA to DINA(n) (WL = 36)
WBA to DINA(n) (WL = 72)
WBA to AA(n) (WL = 9)
WBA to AA(n) (WL = 18)
WBA to AA(n) (WL = 36)
WBA to AA(n) (WL = 72)
WBA (L) (WL = 9)
WBA (L) (WL = 18)
WBA (L) (WL = 36)
WBA (L) (WL = 72)
Rev. 1.09
8-WORD BLOCK
5V
3.3 V
0.28
0.53
0.12
0.27
-0.05
-0.08
-0.47
-0.46
0.02
-0.16
0.01
-0.27
-0.23
-0.61
-0.52
-0.94
4.00
5.01
4.22
5.28
4.65
5.90
5.06
6.56
0.87
1.28
1.10
1.62
1.41
2.14
1.98
2.85
0.66
1.10
0.82
1.35
1.14
1.87
1.61
2.44
1.97
3.00
2.20
3.28
2.62
3.93
3.09
4.53
H4CPlus_Series
MACROCELL EXAMPLES (Continued)
FUNCTIONAL DIAGRAM: of High Speed Dual-Port RAM
DINA(0-n)
DOB(0-n)
INPUT
DRIVERS
OUTPUT
DRIVERS
ROW 0_A
AA(0-m)
WB0
PORT A
ADDRESS
DECODER
WBA
ROW 0_B
MEMORY
CELL
ROW 1_B
ROW 1_A
PORT B
ADDRESS
DECODER
AB(0-m)
MEMORY
CELL
WB1
READ CYCLE High Speed Dual-Port RAM
AB(0-m)
t
t
DOB(0-n)
AA
OH
Previous Data
DOUT
WRITE CYCLE High Speed Dual-Port RAM
t ASU
t WP
t WDO
WBA(0-n)
t AWB
AA(0-m)
t AH
Write Address
t DH
t DSU
Write Data
DINA(0-n)
t DDO
Data at Read Address
DOB(0-n)
t AA
AB(0-m)
H4CPlus_Series
Read Address
MOTOROLA
23
H4CPlus DC ELECTRICAL CHARACTERISTICS
Table 7. Electrical Considerations for H4CPlus Series Arrays
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDD=3V/3.3V±0.3V
VDD=5V±10%
Unit
VDD
DC Supply Voltage
-0.5 to 4.6
-0.5 to 6.0
V
Vin
DC Input Voltage
-0.5 to VDD + 0.5
-0.5 to VDD + 0.5
V
DC Output Voltage
-0.5 to VDD + 0.5
-0.5 to VDD + 0.5
V
I
DC Current Drain per Pin, Any Single Input or Output
±50
±50
mA
I
DC Current Drain per Pin, Any Paralleled Outputs
±100
±100
mA
I
DC Current Drain VDD and VSS Pins
±100
±100
mA
-65 to +150
-65 to +150
°C
300
300
°C
Vout
Tstg
Storage Temperature
TL
Lead Temperature (10 second soldering)
Note: Maximum ratings are those values beyond which damage to the device may occur.
RECOMMENDED OPERATING CONDITIONS (to guarantee functionality)
Symbol
VDD*
VDD*
*
Parameter
Min
Max
Unit
DC Supply Voltage, VDD = 5.0V (Nominal)
4.5
5.5
V
DC Supply Voltage, VDD = 3.0/3.3V (Nominal)
2.7
3.6
V
For testing, only. VDD range is wider for simulation purposes.
Notes:
1. All parameters are characterized for DC conditions after thermal equilibrium has been established.
2. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Vss or VDD).
3. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that Vin and Vout be constrained to the
range VSS≤ (Vin or Vout)≤VDD.
MOTOROLA
24
H4CPlus_Series
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
Table 8. DC Electrical Characteristics for H4CPlus Series Arrays (Ta = -40˚C to 85˚C)
Sym.
VIH
VIL
VT+
Parameter
Condition
Max.
Min.
Max.
Input High Voltage,
CMOS Inputs (3.3V and 5V core)
2.0
VDD+0.3
0.7 VDD
VDD+0.3
TTL Inputs (5V core)
2.0
VDD+0.3
2.2*
VDD+0.3
Input Low Voltage,
CMOS Inputs (3.3V and 5V core)
-0.3
0.8
-0.3
0.3 VDD
TTL Inputs (5V core)
-0.3
0.8
-0.3
0.8
-
0.75VDD
-
0.7VDD
N/A
N/A
-
2.4
0.25VDD
-
0.25VDD
-
N/A
N/A
0.8
-
0.12VDD
-
Positive Threshold Voltage,
CMOS Schmitt Trigger
Negative Threshold Voltage,
CMOS Schmitt Trigger
TTL Schmitt Trigger
VHy
Hysteresis - CMOS Schmitt Trigger
Hysteresis - TTL Schmitt Trigger
VT+ to VT-
N/A
0.05VDD
-
-24.0
-
-48.0
-
-12.0
-
-24.0
-
-6.0
-
-12.0
-
ON4 Output Type
-3.0
-
-6.0
-
ON2 Output Type
-2.0
-
-3.0
-
24
-
48.0
-
12
-
24.0
-
6
-
12.0
-
ON4 Output Type
3
-
6.0
-
ON2 Output Type
2
-
3.0
-
ON16 Output Type
ON8 Output Type
VDD =Min,
VOH Min= 0.8VDD
Output Low Current,
ON32 Output Type
ON16 Output Type
IOL
0.1VDD
N/A
Output High Current,
ON32 Output Type
IOH†
VDD=5V±10%
Guaranteed
Min.
TTL Schmitt Trigger
VT-
VDD=3V/3.3V±0.3V
Guaranteed
ON8 Output Type
VDD =Min,
VOL Max= 0.4 Volts
Unit
V
V
V
V
V
mA
mA
VOH
Output High Voltage, LVCMOS
VDD = Min, IOH= -100µA
OVDD3-0.2
-
OVDD3-0.2
-
V
VOL
Output Low Voltage, LVCMOS
VDD = Min, IOL= +100µA
-
0.2
-
0.2
V
Input Leakage Current,
No Pull Resistor
Vin = VDD or VSS
-5
5
-5
5
with Pullup Resistor
PUL; Vin = VSS
-5
-100
-10
-200
with Pulldown Resistor
PDL; Vin = VDD
5
100
10
200
Output Leakage Current,
3-State Output
Output = Off-State
Vout = VDD or VSS
-10
10
-10
10
Output Leakage Current,
Open Drain Output (Device Off)
Output = Off-State
Vout = VDD
-10
10
-10
10
Max Quiescent Supply Current
Iout = 0mA
Vin = VDD or VSS
Iin
Ioz**
IDD
µA
µA
Design Dependent
mA
* VIH = 2.0V at VDD = 5V±5%
** Single-Drive Output
† For 3.3V ± 0.3 and 5V ±10%, only. For 2.7 V consult factory.
N/A = Not Applicable
H4CPlus_Series
MOTOROLA
25
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
Table 9. DC Electrical Characteristics for H4CPlus Series GTL Driver (Ta = -40˚C to 85˚C)
Sym.
Parameter
Conditions
VDD= 3.3V±0.3V
Guaranteed
Min.
Max.
VDD=5V±10%
Guaranteed
Min.
Unit
Max.
DC Characteristics for GTL Receivers
VIH
Input High Voltage,
GTL Inputs
-
VIL
Input Low Voltage,
GTL Inputs
-
VVR08+0.10
VDD+0.30 VVR08+0.10 VDD+0.30
V
-0.30
VVR08-0.10
-0.30
VVR08-0.10
V
VIDH
Minimum Input High Voltage,
GTL Differential Input
-
-
100
-
100
mV
VIDL
Input Low Voltage,
GTL Differential Input
-
-
100
-
100
mV
VICM
Input Common
Range, VCM min
-
0.6
-
V
-
1.1
-
2.0
V
Mode
0.40
Voltage
-
VCM max
IIH
Input High Current,
GTL Input
Vin=VTT, VDD= Max
-
5
-
5
µA
IIL
Input Low Current,
GTL Inputs
Vin=0.4V, VDD= Max
-
-5
-
-5
µA
-
0.68
0.90
0.68
0.90
V
-
-
1.3
-
3.8
mA
VVR08 GTL Ref. Voltage
IDD*
Typical Quiescent Supply Current
VOH*
Output High Voltage,
20mA Output Macros
DC Characteristics for GTL Drivers
VOL
VOL
VOD
IOH=-10µA, VDD= Min
VTT -0.05
VTT +0.05
VTT -0.05
VTT +0.05
40mA Output Macros
IOH=-10µA, VDD= Min
VTT -0.05
VTT +0.05
VTT -0.05
VTT +0.05
Output Low Voltage,
20mA Output Macros
IOL=20mA, VDD= 3 V
-
0.4
-
-
40mA Output Macros
IOL=40mA, VDD= 3 V
-
0.4
-
-
Output Low Voltage,
20mA Output Macros
IOL=24mA, VDD= 4.5 V
-
-
-
0.4
40mA Output Macros
IOL=48mA, VDD= 4.5 V
-
-
-
0.4
Differential Output Voltage,
20mA Output Macros
IOL=20mA
VTT -0.45
-
-
-
IOL=24mA
-
-
VTT -0.45
-
V
V
V
V
IOZH
GTL Output Off Current High
Vout=1.2V, VDD= Max
-
10
-
10
µA
IOZL
GTL Output Off Current Low
Vout=0.4V, VDD= Max
-
-10
-
-10
µA
* Not tested.
Notes:
1. Recommended: VTT = 1.2V ± 5%, VVR08 = (2/3) VTT, RT = 25Ω/50Ω, VTT MAX = VDD+0.3V
MOTOROLA
26
H4CPlus_Series
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
Table 10. Electrical Characteristics for H4CPlus CMTL Buffers (Ta = -40˚C to 85˚C)
Sym.
Parameter
Conditions
VDD= 3.3V±0.3V
Guaranteed
Min.
VDD=5V±10%
Guaranteed
Max.
Min.
Max.
Unit
DC Characteristics for CMTL Receivers
VIDH
Minimum Input High Voltage,
CMTL Inputs (Differential)
-
-
100
-
100
mV
VIDL
Maximum Input Low Voltage,
CMTL Inputs (Differential)
-
-
100
-
100
mV
VICM
Input Common
Range, VICM Min
VDDmax
0.6
-
1.0
-
V
VDDmin
-
2.2
-
3.5
V
Mode
Voltage
VICM Max
IIH
Input High Current,
CMTL Inputs (No Termination)
Vin=VOHmax, VDD= Max
-
5
-
5
µA
IIL
Input Low Current,
CMTL Inputs (No Termination)
Vin=VOLmin, VDD=Max
-
5
-
5
µA
IDD*
Max Quiescent Supply Current
-
-
1.8
-
4.7
mA
-
-
2.5
3.7
1.3
2.0
2.4
3.1
DC Characteristics for CMTL Drivers
Minimum Output High Voltage,
CMTL Outputs (no Load)**
VOH
VDD= Min
CMTL Outputs (50Ω)†
CMTL Outputs (100Ω)†
1.4
2.1
2.5
3.2
CMTL Outputs IOH=0.5mA
N/A
N/A
-
3.5
-
-
1.0
2.0
1.1
2.0
1.6
2.4
CMTL Outputs (100Ω)†
1.0
1.9
1.5
2.3
CMTL Outputs IOL=20mA
N/A
N/A
1.7
2.7
-
-
1.0
2.5
Maximum Output Low Voltage,
CMTL Outputs (no Load)**
VOL
VDD= Min
CMTL Outputs (50Ω)†
Differential Output Voltage,
CMTL Outputs (no Load)**
|VOD|
VDD= Min
CMTL Outputs (50Ω)†
0.19 Typ.
0.4
1.1
CMTL Outputs (100Ω)†
0.29 Typ.
0.5
1.4
Output Offset Voltage,
CMTL Outputs (no Load)**
VOS
-
-
2.1
2.6
CMTL Outputs (50Ω)†
1.35
1.85
2.1
2.65
CMTL Outputs (100Ω)†
1.35
1.85
2.1
2.65
VDD= Min
V
V
V
V
IOZH
CMTL Output Off Current High
Vout=VDD, VDD=Max
-10
10
-10
10
µA
IOZL
CMTL Output Off Current Low
Vout=VSS, VDD=Max
-10
10
-10
10
µA
Output Impedance (Typical)
100Ω < Load < 200 Ω †
Ro
50
30
Ω
* Not tested.
** OD32TCMT and BOD32TCMT macros, only.
† Loads across differential CMTL outputs.
N/A = Not Applicable
H4CPlus_Series
MOTOROLA
27
H4CPlus DC ELECTRICAL CHARACTERISTICS (Continued)
Table 11. Electrical Characteristics for PECL Receivers (Ta = -40˚C to 85˚C)
Sym.
Parameter
Conditions
VDD= 3.3V±0.3V
Guaranteed
Min.
Max.
VDD=5V±10%
Guaranteed
Min.
Unit
Max.
DC Characteristics for PECL Receivers
VIH
Input High Voltage,
PECL Single-Ended
-
VIL
Input Low Voltage,
PECL Single-Ended
-
VVR38+0.10 VDD+0.30 VVR38+0.10 VDD+0.30
V
-0.30
VVR38-0.10
-0.30
VVR38-0.10
V
VIDH
Minimum Input High Voltage,
PECL Differential Input
-
-
100
-
100
mV
VIDL
Input Low Voltage,
PECL Differential Input
-
-
100
-
100
mV
VICM
Input Common
Range, VCM min
1.2
-
1.4
-
V
-
VDD-0.8
-
VDD-0.8
V
Mode
Voltage
-
VCM max
IIH
Input High Current,
PECL Input
Vin=VDD, VDD=Max
-
5
-
5
µA
IIL
Input Low Current,
PECL Input
Vin=VSS, VDD=Max
-
5
-
5
µA
-
1.5 (ILP-)
5.3 (IPX-)
-
4.3 (IPD)
5.1 (IPN)
mA
IDD*
VVR38
Max Quiescent Supply Current
PECL Reference Voltage
PECL Single-Ended
VDD -1.3 Typ.
VDD -1.3 Typ.
V
* Not tested.
Table 12. DC Electrical Characteristics for H4CPlus Series PCI Buffers (Ta = -40˚C to 85˚C)
Sym.
Parameter
Condition
VDD= 3.3V±0.3V
Guaranteed
Min.
VDD=5V±10%
Guaranteed
Max.
Min.
Max.
Unit
DC Characteristics for PCI Receivers
VIH
Input High Voltage
0.475VDD
VDD+0.5
2.0
VDD+0.5
V
VIL
Input Low Voltage
-0.5
0.325VDD
-0.5
0.8
V
IIH
Input High Leakage Current
3.3 V: 0<Vin<VDD
5.0 V: Vin = 2.7 V
-
10
-
70
µA
IIL
Input Low Leakage Current
3.3 V: 0<Vin<VDD
5.0 V: Vin = 0.5 V
-
-10
-
-70
µA
DC Characteristics for PCI Drivers
VOH
Output High Voltage
3.3 V: Iout = -500 µA
5.0 V: Iout = -2 mA
0.9VDD
-
2.4
-
V
VOL
Output Low Voltage
3.3 V: Iout =1500 µA
5.0 V: Iout = 6 mA
-
0.1VDD
-
0.55
V
AC Characteristics for PCI Drivers (Not Tested)
VOHmin
Output High Voltage Minimum
3.3 V: Iout = -12(VDD)mA
5.0 V: Iout = -44 mA
0.3VDD
-
1.4
-
V
VOHmax
Output High Voltage Maximum
3.3 V: Iout = -32(VDD)mA
5.0 V: Iout = -142 mA
-
0.7VDD
-
3.1
V
VOLmin
Output Low Voltage Minimum
3.3 V: Iout = 16(VDD) mA
5.0 V: Iout = 95 mA
0.6VDD
-
2.2
-
V
VOLmax
Output Low Voltage Maximum
3.3 V: Iout = 38(VDD) mA
5.0 V: Iout = 206 mA
-
0.18 VDD
-
0.71
V
MOTOROLA
28
H4CPlus_Series
Table 13. DC Electrical Characteristics for H4CPlus Series (Ta = -40˚C to 85˚C)
Sym.
Parameter
Condition
VDD= 3.3V±0.3V
Guaranteed
Min.
Max.
VDD=5V±10%
Guaranteed
Min.
Unit
Max.
Leakage Current for Fail-Safe and Extended Voltage Range Bidirectional I/O
Ioff
Ioff*
Leakage Current for bidirectional VDD = OVDD5 = 0 to MAX
Fail-Safe I/O,
Vin= VDD or VSS
No pull resistor
Output = Off-State
N/A
Leakage Current for bidirectional VDD = OVDD5 = 0 to MAX
Fail-Safe I/O,
Vin= VDD or VSS
with pulldown resistor
Output = Off-State
N/A
N/A
-20
+200
Leakage Current for bidirectional VDD = OVDD3 = 0 to MAX
Vin= 0 to 5.5 V
extended voltage range I/O,
Output = Off-State
No pull resistor
-20
+20
N/A
N/A
Leakage Current for bidirectional VDD = OVDD3 = 0 to MAX
extended voltage range I/O,
Vin= 0 to 5.5 V
with pulldown resistor
Output = Off-State
-20
N/A
-20
+20
µA
µA
+200
N/A
N/A
*For the bidirectional extended voltage range I/O, the bidirectional input macro must be a 3.3V System and 3.3V Core macro.
N/A = Not Applicable
Concept, Gate Ensemble, Dracula, Verifault, Veritime, and Verilog XL are trademarks of Cadence Design Systems, Inc.
HP9000/7XX Series is a trademark of Hewlett-Packard, Inc.
ASICVectors Interface, AutoLogic, Design Architect, FastScan, Quickpath, QuickSim II, and TimeBase are trademarks of Mentor Graphics Corp.
HDC, H4C, H4CPlus, M5C, MCR, MicroCool, Mustang, OMPAC, OACS, PrediX, CMTL, and TestPAS are trademarks of Motorola, Inc.
SPARC is a registered trademark of SPARC International, Inc.
Design Ware, Design Compiler, HDL Compiler, and Test Compiler are trademarks of Synopsys, Inc.
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MOTIVE is a trademark of Quad Design Technology, Inc.
GTL is a trademark of Xerox Corp.
H4CPlus_Series
MOTOROLA
29
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H4CP/D