MT3326
Version 1.08
GPS SoC Chip
Data Sheet
r
o
f
e
s
a
e
Specifications are subject to change without notice
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
MT3326 Data Sheet
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 1 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
Revision History
Revision
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.80
0.81
1.00
1.01
1.02
1.03
1.04
1.05
1.06
1.07
1.08
Date
2007/08/10
2007/08/23
2007/11/05
2007/12/26
2008/05/30
2008/06/13
2008/06/16
2008/06/19
2008/06/23
2008/07/02
2008/07/18
2008/07/25
2008/08/22
2008/10/21
2008/11/17
2008/11/21
2009/1/6
2009/01/14
Comments
First release
Add package part, and RF block diagram
Added RF part description
Update IC logo
Add 1 pps spec. and WLCSP packaging
Add WLCSP ball map and TFBGA ball map
Extend IO power voltage to 1.8V
Add LDO spec. and modify WLCSP info.
Fix DVDDIO voltage range to 1.7V and sync pin names
Add power scheme and figures update
Modify WLCSP package dimension information.
Sync pin name of different packages
Add 912600 spec. description for USRT
Rotate the QFN top view.
Add Ta, Tstg, and absolute max rating spec.
Specify strap pin pull direction
Remove 1.8V IO feature
Update SPI frequency
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 2 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
Table of Contents
r
o
f
e
s
a
e
Revision History.....................................................................................................................2
Table of Contents ..................................................................................................................3
1. General Description........................................................................................................5
2. Features .........................................................................................................................6
3. Pin Assignment and Description / Functional Diagram...................................................7
4.
5.
6.
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
3.1.
Pin Assignment (Top View) ............................................................................................. 7
3.2.
Pin Identification (48 Pin) ................................................................................................ 8
3.3.
Pin Description ................................................................................................................ 9
BLOCK DIAGRAMS .....................................................................................................13
4.1.
SYSTEM BLOCK DIAGRAM......................................................................................... 13
4.2.
FUNCTIONAL BLOCK DIAGRAM ................................................................................ 14
4.3.
RF part functional block diagram................................................................................... 15
4.4.
Reference design schematics ....................................................................................... 15
MT3326 RF Part Description ........................................................................................16
5.1.
Antenna Detection......................................................................................................... 16
5.2.
LNA/Mixer...................................................................................................................... 16
5.3.
VCO/Synthesizer........................................................................................................... 16
5.4.
IF CSF ........................................................................................................................... 17
5.5.
PGA............................................................................................................................... 17
5.6.
ADC............................................................................................................................... 17
r
o
f
ease
MT3326 Digital Part Description ...................................................................................18
6.1.
Boot ROM...................................................................................................................... 18
6.2.
Clock Module................................................................................................................. 18
6.3.
Reset Controller ............................................................................................................ 18
6.4.
UART............................................................................................................................. 18
6.5.
Interrupt Control Unit ..................................................................................................... 18
6.6.
GPIO Unit ...................................................................................................................... 19
6.7.
Serial Peripheral Interface (SPI).................................................................................... 19
6.8.
SRAM ............................................................................................................................ 19
6.9.
Factory Testing.............................................................................................................. 19
C
K
IATE
MED
7.
8.
l
e
R
l
a
i
t
n
e
d
i
f
on
X
C
W
_
k
n
i
EEL
MT3326 Power Scheme ...............................................................................................20
7.1.
Single Source Power Scheme....................................................................................... 20
7.2.
Multi-Source Power Scheme with 2.8V IO Power ......................................................... 20
Electrical Characteristics ..............................................................................................21
8.1.
DC Characteristic .......................................................................................................... 21
Page 3 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
8.1.1.
Absolute Maximum Ratings ............................................................................................ 21
8.1.2.
Recommended Operating Conditions ............................................................................ 21
8.1.3.
General DC Characteristic.............................................................................................. 21
8.1.4.
DC Electrical Characteristics for 2.8 Volts Operation..................................................... 21
8.1.5.
1.5V RF LDO DC Characteristic ..................................................................................... 22
8.1.6.
1.2V Core LDO DC Characteristic .................................................................................. 22
8.1.7.
DC Electrical Characteristics for RF Part ....................................................................... 22
8.1.8.
LNA AC Electrical Characteristics for RF Part................................................................ 22
8.1.9.
RX Chain from LNA to PGA, before ADC....................................................................... 23
8.1.10.
RX Chain from Mixer to PGA, before ADC ..................................................................... 23
8.1.11.
Image-Reject Down-conversion Mixer............................................................................ 23
8.1.12.
Channel Select Filter (CSF)............................................................................................ 23
8.1.13.
Programmable Gain Amplifier (PGA).............................................................................. 23
8.1.14.
2-Bit & 4-Bit Quantizer (ADC) ......................................................................................... 24
8.1.15.
Integrated Synthesizer .................................................................................................... 24
8.1.16.
Crystal Oscillator (XO) .................................................................................................... 24
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
8.2.
9.
AC Characteristics......................................................................................................... 24
8.2.1.
RS232 Interface Timing .................................................................................................. 24
8.2.2.
SPI Interface Timing ....................................................................................................... 25
8.2.3.
I2C Interface Timing........................................................................................................ 26
Package Dimensions....................................................................................................27
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 4 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
1. General Description
MT3326, a high performance single chip, single die host-based GPS solution, which includes on chip
CMOS RF and digital baseband. It achieves the industry’s highest levels of sensitivity, accuracy, and
Time-to-First-Fix (TTFF) with lowest power consumption in a small-footprint lead-free package. Its small
footprint and minimal accessary provide significant reductions in the design, manufacturing and testing
resource required to navigation device and handsets.
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
With an on-chip integrated LNA, MT3326 delivers a total receiver noise figure of 4 dB (before ADC).
With its on-chip image-rejection mixer, the spec of external SAW filter is alleviated. With an on chip automatic
center frequency calibration band pass filter, external filter is not required. The integrated PLL with Voltage
Controlled Oscillator (VCO) provides excellent phase noise performance and fast locking time.
MT3326 supports up to 210 PRN channels. With 66 search channels and 22 simutaneous tracking
channels, MT3326 acquires and tracks satellites in the shortest time even at indoor signal levels. MT3326
supports various location and navigation applications, including GPS, SBAS (WAAS, EGNOS, GAGAN,
MSAS), DGPS (RTCM), and AGPS.
On chip power management design makes MT3326 easily integrated into your system without extra
voltage regulator. With linear regulator embedded, MT3326 give user plenty of choices for their application
circuit.
Through MT3326's excellent low power consumption characteristic(acquisition 50mW, tracking 38mW),
power sensitive devices, especially embedded systems, need not worry about operating time anymore and
user can get more fun.
With MT3326’s powerful interface, host system can communicate with MT3326 efficiently through UART
and SPI at baudrate as fast as 921600 bps to save host CPU processing time.
Form system design view, if host system already has TCXO or RTC, MT3326 can share these sources
with host system and this will save system BOM cost and system PCB area.
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 5 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
2. Features
„
„
„
„
„
Specification
ƒ 22 tracking/ 66 acquisition-channel GPS
Receiver
ƒ WAAS/EGNOS/MSAS/GAGAN supported
ƒ Support up to 210 PRN channels
ƒ RTCM ready
ƒ Jammer detection and reduction
ƒ Indoor and outdoor multi-path detection and
compensation
ƒ FCC E911 compliance and A-GPS supported
ƒ Maximum fix update rate up to 5Hz
ƒ
„
Typical accuracy = 39ns with 26MHz TCXO.
r
o
f
e
s
a
e
Power down mode
ƒ Intelligent power management
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
RF Configuration
ƒ 4-bit IF signal.
ƒ SoC, integrated in single chip with CMOS
process.
Reference Oscillator
ƒ TCXO
ƒ Frequency : 12.6MHz to 40.0MHz
ƒ Frequency Max Error : +/- 2.5 ppm
Built-in PLL series
ƒ Built-in small jitter clock synthesizer to provide
better acquisition and tracking quality.
1 pulse-per-second (1PPS) GPS time reference
ƒ Duty cycle adjustable
ƒ
„
Power Scheme
ƒ Self build 1.2V core power and 1.5V RF LDO
ƒ Bypass mode for external 1.2V and 1.5V
suppliers
„
Build-in reset controller
ƒ Needless of external reset control IC
„
Serial interface
ƒ Two UARTs
ƒ SPI
ƒ I2C
ƒ GPIO interface (up to 20 pins)
„
NMEA
ƒ NMEA 0183 standard V3.01 and backward
compliance
ƒ Support 219 different Datum
„
Outline
ƒ 48-pin QFN lead-free package 6mm x 6mm x
0.85.mm
ƒ No external TTL component
Typical accuracy = 61ns with 16.368MHz TCXO.
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 6 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
3. Pin Assignment and Description / Functional Diagram
3.1. Pin Assignment (Top View)
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
MT3326
RFCMOS SoC
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 7 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
3.2. Pin Identification (48 Pin)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
Pin name
VCC_LNA
RF_IN
VS_AA
VS_LNA
VCC_BAT
VS_VCO
PLL_LF
GND_VCO1
VCC_SX
OSC2
OSC1
VS_SDM
Pin No.
13
14
15
16
17
18
19
20
21
22
23
24
Pin name
RF LDO output
RF LDO input
ACDUP
Core LDO input
Core LDO output
RTCCLK/GIO13
MS0
MS1
ECLK
SYNC
TX1/I2CC
RX1/I2CD
Pin No.
25
26
27
28
29
30
31
32
33
34
35
36
r
o
f
e
s
a
e
Pin name
DVDDIO
SCK0/TX0
SCS0#/CTS0
SO0/RTS0
SIN0/RX0
DVDD12
GIO2
GIO3
GIO4
GIO5
GIO6
STANDBY/GIO
7
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
12
Pin name
DVDDIO
INTR
GIO0
GIO1
HRST#
DVDD12
VCC_ADC
TEST1
VCC_IF
MIX_IN
GND_MIX3
LNA_OUT
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 8 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
3.3. Pin Description
Pin Numbers
Symbol
Type
r
o
f
e
s
a
e
Description
RF Interface
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
48
LNA_OUT
RF
LNA RF output
46
MIX_IN
RF
Mixer RF Input or external LNA input
2
RF_IN
RF
LNA RF Input pin, a matching circuit is
required
and should be AC couple.
44
TEST1
Analog
IF test output ,normally this pin is NC
7
PLL_LF
Analog
SX loop filter
11
OSC1
Analog
Input for XTAL or TCXO
10
OSC2
Analog
Input for XTAL or not connected
43
VCC_ADC
Analog
Voltage supply for ADC block
5
VCC_BAT
Analog
Supply Voltage of external LNA and
antenna detect circuit
45
VCC_IF
Analog
Voltage supply for IF block
1
VCC_LNA
Analog
1.5V Vcc supply for LNA block
9
VCC_SX
Analog
1.5V Vcc supply for SX block
3
VS_AA
Analog
Monitor pin for active antenna
4
VS_LNA
Analog
Supply voltage to external LNA
6
VS_VCO
Analog
Supply voltage to internal VCO
12
VS_SDM
Analog
Supply voltage to internal SDM
47
GNDMIX3
GND
8
GNDVCO1
GND
GND pin for VCO
DGND
GND
GND pin for Digital
AGND
GND
GND pin for Analog
GND
GND pin for RF
l
e
R
l
a
i
t
n
e
d
i
f
on
GND pin for MIXer
C
K
IATE
MED
GND_RF
System Interface
41
r
o
f
ease
HRST#
X
C
W
_
k
n
i
EEL
2.8V LVTTL input
75K pull up, SMT
System reset. Active low
Page 9 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
36
STANDBY
2.8V LVTTL I/O
PPU, PPD
slow slew rate, SMT,
2mA, 4mA, 6mA, 8mA,
PDR
Standby mode
Default input, 75K pull up
Share with GIO7
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
38
INTR
18
RTCCLK
21
ECLK
22
SYNC
19
20
MS0
MS1
2.8V LVTTL I/O
PPU, PPD, SMT,
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull down
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull down
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull down
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
10mA, 12mA, 14mA,
16mA, PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
10mA, 12mA, 14mA,
16mA, PDR
2.8V LVTTL I/O
75K pull up
slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
C
K
IATE
MED
RX1
23
TX1
26
SCK0
External RTC clock input
Default: input, 75K pull down
Share with GIO13
External clock input to bypass internal PLL
Default: input, 75K pull down
Share with GIO11
External frame sync signal
Default: input, 75K pull down
Share with GIO12
Default: input, 75K pull up
Share with GIO9 output
Strap pin for host interface select
0 : SPI
1 : UART
Default: input, 75K pull up
Strap pin, default MUST pull up
Share with GIO10
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
Peripheral Interface
24
External interrupt 0
Default input, 75K pull up
Strap pin, default MUST pull up
Share with GIO8
Serial input for UART 1
Default: input, 75K pull up
Share with GIO15
X
C
W
_
k
n
i
EEL
Serial output for UART 1
Default: output, 4mA driving
Share with GIO14
Synchronous serial interface (SPI)
Default: output 4mA driving
Share with TX0 / GIO16
Page 10 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
29
SIN0
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
Synchronous serial interface (SPI)
Default: input
Share with RX0 / GIO19
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
28
SO0
27
SCS0#
Synchronous serial interface (SPI)
Default: output 4mA driving
Strap pin, default MUST pull up
Share with RTS0 / GIO18
SPI slave select 0. Active low
Default output 4mA driving
Share with CTS0 / GIO17
GPIO
39
GIO0
GIO1
40
GIO2
31
32
GO3
GIO4
33
35
GO5
GIO6
GPIO 0
Default output, 4mA driving
GPIO 1
Default input 75K pull down
GPIO 2
Default : input 75K pull down
GPO 3
Default : output low 4mA driving, pull up
Strap pin clk_sel[1]
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
C
K
IATE
MED
34
2.8V LVTTL I/O
PPU, PPD, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
PPU, PPD, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull down
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
10mA, 12mA, 14mA,
16mA, PDR
2.8V LVTTL I/O
75K pull down
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
10mA, 12mA, 14mA,
16mA, PDR
2.8V LVTTL I/O
75K pull up
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
10mA, 12mA, 14mA,
16mA, PDR
2.8V LVTTL I/O
75K pull down
slow slew rate, SMT
2mA, 4mA, 6mA, 8mA,
PDR
GPIO 4
Default : input 75K pull down
GPO 5
Default : output low 4mA driving, pull up
Strap pin clk_sel[0]
X
C
W
_
k
n
i
EEL
GPIO 6
Default : input 75K pull down
Share with DUTY input
Page 11 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
GIO7 share with STANDBY
GIO8 share with INTR
GIO9 share with MS0
GIO10 share with MS1
GIO11 share with ECLK
GIO12 share with SYNC
GIO13 share with RTCCLK
GIO14 share with TX1/I2CC
GIO15 share with RX1/I2CD
GIO16 share with SCK0/TX0
GIO17 share with SCS0#/CTS0
GIO18 share with SO0/RTS0
GIO19 share with SIN0
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
GIO19~GIO
7
Analog & Analog Power Supply
15
16
17
14
13
ACDUP
CORE LDO
input
CORE LDO
output
RF LDO
input
RF LDO
output
Analog
Voltage reference Cap
Analog
1.2V LDO input for digital core power
Analog
1.2V LDO output for digital core power
Analog
1.5V LDO input for RF portion
Analog
1.5V LDO output for RF portion
Digital Power Supply
30,42
DVDD12
Digital power
Core Power at 1.2V
25,37
DVDDIO
Digital power
IO Pad Power
r
o
f
ease
Note:
PPU: Programmable pull up
l
e
R
l
a
i
t
n
e
d
i
f
on
PPD: Programmable pull down
PSR: Programmable slew rate
PDR: Programmable driving
C
K
IATE
Strap pin clk_sel[1:0]
11 : 16.368/16.369 MHz
10 : 26MHz
01 : test mode
00 : 12.4~40 MHz wide range mode
MED
X
C
W
_
k
n
i
EEL
Page 12 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
4. BLOCK DIAGRAMS
4.1. SYSTEM BLOCK DIAGRAM
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
RFCMOS
MT3326
2.8V
Fig. 1 MT3326 system block diagram
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 13 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
4.2. FUNCTIONAL BLOCK DIAGRAM
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
Fig. 2 MT3326 functional block diagram
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 14 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
4.3. RF part functional block diagram
LNAOUT
MIXER IN
IF Filter
PGA
LNA
r
o
f
e
s
a
e
4 bit
l
e
R
ial
ADC
Antenna
Detector
K
E
T
A
I
D
ME
RF LDO
(1.5V)
t
n
e
d
i
f
n
o
C
RC/CR
(High resolution)
÷2
÷2
VCO
(2xLO)
SDM
X
C
W
_
k
n
i
EEL
CP
PFD
XOSC
Fig. 3 MT3326 RF functional block diagram
4.4. Reference design schematics
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
MT3326
X
C
W
_
k
n
i
EEL
Fig. 4 MT3326 reference design schematic.
Page 15 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
5. MT3326 RF Part Description
5.1.
r
o
f
e
s
a
e
Antenna Detection
Antenna detection capability in the MT3326 enables IC to recognize the presence of an external antenna.
In the event that there is a short circuit occurring at the active antenna portion, the IC is able to limit the drawn
current to a safe level. By using baseband control, active antenna current will be limited around 30mA or
40mA, which is set by baseband. And when active antenna sink a current higher than 3mA, the IC will send a
signal to baseband to indicate that active antenna is functional.
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
On board external LNA can also make use of VS_LNA pin as a power supply to draw current. This
allows external LNA to be powered-down through IC’s baseband control.
Vcc_BAT(4.2~2.7v)
IC
Iclamp
VC_BAT
VS_LNA
Sense voltage &
control current
10 ohm
VS_AA
Ext LNA
Vcc_BAT(4.2~2.7v)
IC
Iclamp
VC_BAT
VS_LNA
Sense voltage &
control current
r
o
f
ease
10 ohm
VS_AA
l
e
R
l
a
i
t
n
e
d
i
f
on
Active Antenna
Fig. 5 Antenna detection functional diagram
5.2.
C
K
IATE
LNA/Mixer
MED
X
C
W
_
k
n
i
EEL
Upon receiving RF input signal in through either GPS antenna to internal LNA or external antenna and
LNA, the mixer down converts the amplified signal (1575.42MHz) to a differential IF signal of 4.092MHz. The
current chip configuration also allows external LNA to be connected directly to the MIXER_IN pin. The internal
LNA has a power-down option. Upon detection of an external active antenna connected to VS_AA, this
internal LNA will automatically enter into power-down mode. This feature can also be disabled through
baseband control to allow active antenna to be directly connected to RF_IN.
5.3. VCO/Synthesizer
The entire frequency synthesizer including crystal oscillator, VCO, divider, phase frequency detector
(PFD), charge pump (CP), and loop filter are all integrated on MT3329 chip. Upon power-on, VCO is
auto-calibrated to its required sub-band. The synthesizer has two topologies (integer-N or fractional-N)
Page 16 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
selectable through the base band control
Integer-N synthesizer is meant for supporting 16.368MHz and 26MHz reference frequency. Other clock
modes from 12.6MHz up to 40MHz are supported by fractional-N synthesizer, together with a sigma-delta
modulator (SDM) and multi-modulus divider (MMD).
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
5.4. IF CSF
The down converted IF signal from the mixer output passes through a bandpass CSF. Centered at
4.08/4.092MHz (fref 26MHz / 16.368MHz), the filter rejects out-of-band (10MHz) interferences by more than
20dB, and has a pass band ripple of <0.2dB. The filter also provides a 17dB pass band gain to improve noise
figure.
It supports both 2MHz (GPS) and 4MHz (Galileo).
5.5. PGA
The PGA has approximately 48dB of gain control range with approximately 1.6dB per step. The maximum
gain is around 48dB.
5.6. ADC
The differential IF signal is being quantized by a 2 or 4-bit ADC, depending on the option set by base
band control.
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 17 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
6. MT3326 Digital Part Description
r
o
f
e
s
a
e
6.1. Boot ROM
The embedded Boot ROM provides a function of loading a set of user code through UART/SPI into the
SRAM. It can be used to execute code download and one external strap pin is needed.
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
6.2. Clock Module
This module generates all internal clocks required by processor, correlator, internal memory, bus interface
and so on. The referenced input clock is generated from RF block. For system flexibility and the maximum
power savings, various power management modes are supported.
6.3. Reset Controller
A build-in reset controller generate reset signal for all digital blocks. It includes power on reset feature and
hardware trapping function. Software reset function for different circuit blocks are also included for usage
flexibility.
r
o
f
ease
Fig. 6 Reset signal characteristic
l
e
R
l
a
i
t
n
e
d
i
f
on
6.4. UART
UART is an abbreviation of “Universal Asynchronous Receiver/Transmitter”. MT3326 contains two full
duplex serial ports. It is used in serial data communication, and a UART converts bytes of data to and from
asynchronous start-stop bit streams represented as binary electrical impulses.
C
K
IATE
In MT3326, there are several functions related to UART communication, such as measurement data
output and aiding information input from host CPU. MT3326 also supports the wake up function from UART
activity. In generally, UART0 and UART1 are used for measurement data output and aiding data from host.
Customers can adjust UART2 port as they want. The receive (RX) and transmit (TX) side of every port
contains a 16-byte FIFO. The bit rates are selectable and ranging from 4.8 to 921.6 kbps. UART can provide
the developers signal or message outputs.
MED
6.5. Interrupt Control Unit
X
C
W
_
k
n
i
EEL
The interrupt control unit manages all internal and external sources of interrupts. These include Watch
dog, all peripheral interfaces such as UART, I2C, SPI, and external user interrupt pins. These interrupt
sources could act as wake up event during power saving mode also.
Page 18 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
6.6. GPIO Unit
GPIO is the abbreviation of General Purpose Input/Output. MT3326 supports a variety of peripherals
through at most 20 GPIO ports that are programmable to users. The unit that manages all GPIO lines
supports a simple control interface. GPIO can provide the developers signal or message outputs.
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
6.7. Serial Peripheral Interface (SPI)
The serial peripheral interface port manages communication between digital BB and external devices
6.8. SRAM
There is on-chip SRAM embedded in MT3326, and it supports variable DSP architecture to fit our
customer design requirement. These SRAM includes DSP instructions and data memory. Instruction
downloaded from host CPU is executed at the chip initial setup stage after MT3326 power active and reset
de-assert.
6.9. Factory Testing
MT3326 provides full coverage of all the memory during chip testing and qualification. A memory built-in
self-test (MEMBIST) function is used. The SCAN test logic using automatic test pattern generation (ATPG) is
usually combined with MEMBIST to provide functional test coverage at the wafer level.
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 19 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
7. MT3326 Power Scheme
r
o
f
e
s
a
e
7.1. Single Source Power Scheme
The PMIC provides single power source 2.8V that connected to MT3326 internal 1.2V, 1.5V LDO and
VIO input pins.
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
Bandgap
&
PWRST
1.2V BB
LDO
1.5V RF
LDO
2.8V
1.8V
1.5V
PMIC
1.2V
1.8V / 2.8V
IO
1.2V BB
Block
1.5V RF
Block
7.2. Multi-Source Power Scheme with 2.8V IO Power
The PMIC provides power source 2.8V that connected to MT3326 internal 1.2V, 1.5V LDO and VIO
input pins. The PMIC also provides 1.5V and 1.2V for RF and base band blocks respectively.
Bandgap
&
PWRST
1.2V BB
LDO
1.5V RF
LDO
l
e
R
l
a
i
t
n
e
d
i
f
on
C
K
E
T
A
I
MED
X
C
W
_
k
n
i
EEL
1.8V / 2.8V
IO
1.2V BB
Block
r
o
f
ease
1.5V RF
Block
Page 20 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
2.8V
1.8V
1.5V
1.2V
PMIC
MT3326
Specifications are subject to change without notice
8. Electrical Characteristics
r
o
f
e
s
a
e
8.1. DC Characteristic
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
8.1.1. Absolute Maximum Ratings
SYMBOL
DVDDIO
VCC_LNA
VCC_IF
VCC_ADC
VCC_SX
VCC_BAT
PARAMETER
2.8V Digital Power Supply
RF power supply
RATING
-0.3 to 3.6
-0.3 to 3.6
UNITS
V
V
Active antenna, external LNA power supply
-0.3 to 4.2
V
8.1.2. Recommended Operating Conditions
SYMBOL
DVDDIO
VCC_LNA
VCC_IF
VCC_ADC
VCC_SX
VCC_BAT
Tj
Ta
Tstg
PARAMETER
2.8V Digital Power Supply
MIN
2.0
TYP
2.8
MAX
3.6
UNITS
V
RF power supply
1.4
1.5
1.6
V
Active antenna, external LNA power supply
Commercial Junction Operating Temperature
Industry Junction Operating Temperature
Operation Temperature
Storage Temperature
2.6
0
-40
-40
-65
3.3
25
25
25
25
4.2
115
125
85
150
V
°C
°C
°C
°C
r
o
f
ease
8.1.3. General DC Characteristic
SYMBOL
IIL
IIH
IOZ
PARAMETER
Input low current
Input high current
Tri-state leakage current
K
E
T
A
I
D
E
M
l
e
R
tial
CONDITIONS
No pull-up or down
No pull-up or down
MIN
-1
-1
-10
n
e
d
i
f
Con
MAX
1
1
10
UNITS
uA
uA
uA
8.1.4. DC Electrical Characteristics for 2.8 Volts Operation
X
C
W
_
k
n
i
EEL
SYMBOL
PARAMETER
VIL
Input Lower Voltage
VIH
Input High Voltage
Schmitt Trigger Negative Going
VTThreshold Voltage
Schmitt Trigger
VT+
Positive Going Threshold Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
RPU
Input Pull-Up Resistance
CONDITIONS
LVTTL
MIN
-0.28
2.0
MAX
0.6
3.08
UNITS
V
V
0.68
1.36
V
1.36
1.7
V
-0.28
2.4
40
0.4
VDD28 + 0.28
190
V
V
KΩ
LVTTL
|IOL| = 1.6~14 mA
|IOH| = 1.6~14 mA
PU=high, PD=low
Page 21 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
RPD
Input Pull-Down Resistance
PU=low, PD=high
40
190
r
o
f
e
s
a
e
8.1.5. 1.5V RF LDO DC Characteristic
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
SYMBOL
RF_LDO_
Input
RF_LDO_
output
Imax_2.8
Icc
Iq
PARAMETER
RF LDO input
Supply voltage
RF LDO output
MIN
2
TYP
2.8
MAX
3.3
UNIT
V
1.4
1.5
1.6
V
RF LDO current
limit @Vin=2.8V
For normal RF
operation current
Load regulation
30
KΩ
note
mA
17
23
mA
10
mV
PSRR-1MHz
45
dB
Quiescent current
80
uA
1mA to 30mA
load
Co=1uF,
ESR=0.05,
Iload=20mA
8.1.6. 1.2V Core LDO DC Characteristic
SYMBOL
PARAMETER
CORE_LDO 1.2V LDO input
_input
Supply voltage
CORE_LDO 1.2V LDO output
_output
Imax
1.2V LDO current
limit @Vin=2.8V
Icc
For normal Core
operation current
Load regulation
TYP
2.8
MAX
3.3
UNIT
V
1.1
1.2
1.3
V
90
note
mA
35
r
o
f
ease
mA
10
mV
l
e
R
l
a
i
t
n
e
d
i
f
on
PSRR-1kHz
Quiescent current
Iq
MIN
2.6
45
30
dB
uA
1mA to 90mA
load
8.1.7. DC Electrical Characteristics for RF Part
C
K
IATE
VCC = 1.5V, Ta = 25 °C unless otherwise specified.
MED
SYMBOL
Icc
Icc
(STAND-BY
)
Icc
(DOZE)
Icc(Off)
PARAMETER
Total Supply Current
MIN
X
C
W
_
k
n
i
EEL
Only the PLL, Oscillator and Regulator are
kept powered up.
Only the Oscillator and Regulator are kept
powered up.
Power-down state current
TYP
16.5
MAX
UNITS
mA
7.9
mA
0.37
mA
8.1.8. LNA AC Electrical Characteristics for RF Part
Page 22 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
2
μA
MT3326
Specifications are subject to change without notice
SYMBOL
Vcc
Icc
NF
|S21|
|S12|
|S11|
|S22|
IIP3
P1dB
Tstart
PARAMETER
Supply Voltage
Supply current
Noise Figure 50 ohm Rs
Forward Voltage Gain
Reverse Isolation
Input Return Loss 50 Ohm RS
Output Return Loss 50 Ohm RL
Input referred IP3 50 ohm RS
1dB Input Compression point
Circuit Start-up time
MIN
1.4
TYP
1.5
MAX
1.6
2.5
2.5
UNITS
V
mA
dB
dB
dB
dB
dB
dBm
dBm
μs
r
o
f
e
s
a
e
2.1
19
30
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
-10
-10
-17
-27
5
8.1.9. RX Chain from LNA to PGA, before ADC
SYMBOL
Vcc
NF
Gain
P1dB
Tstart
PARAMETER
Supply Voltage
Noise Figure 50 ohm Rs
Forward Voltage Gain
1dB Input Compression point
Circuit Start-up time
MIN
1.4
TYP
1.5
2.7
100
-65
MAX
1.6
3.2
5
UNITS
V
dB
dB
dBm
μs
8.1.10. RX Chain from Mixer to PGA, before ADC
SYMBOL
Vcc
NF
Gain
P1dB
Tstart
PARAMETER
Supply Voltage
Noise Figure 50 ohm Rs
Forward Voltage Gain
1dB Input Compression point
Circuit Start-up time
MIN
1.4
50
TYP
1.5
7
80
-45
l
e
R
l
a
i
t
n
e
d
i
f
on
PARAMETER
Input Return Loss 50 Ohm RS
Image Rejection Ratio
Circuit Start-up time
C
K
IATE
MED
8.1.12. Channel Select Filter (CSF)
SYMBOL
Fc
BW3dB
Ripple
Tstart
PARAMETER
Centre Frequency
3dB Bandwidth
Passband Ripple
Circuit Start-up time
EEL
MIN
-10
TYP
MAX
30
X
C
W
ink_
MIN
TYP
4.092
2.49
<0.1
8.1.13. Programmable Gain Amplifier (PGA)
Page 23 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
UNITS
V
dB
dB
dBm
μs
r
o
f
ease
5
8.1.11. Image-Reject Down-conversion Mixer
SYMBOL
|S11|
IRR
Tstart
MAX
1.6
8
100
5
MAX
0.1
5
UNITS
dB
dB
μs
UNITS
MHz
MHz
dB
μs
MT3326
Specifications are subject to change without notice
SYMBOL
Gv
Tstart
PARAMETER
Voltage Gain
Circuit Start-up time
MIN
0
TYP
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
PARAMETER
Operating Frequency
Circuit Start-up time
MIN
TYP
16.368
MIN
TYP
3142.656
UNITS
dB
μs
MAX
26
5
UNITS
MHz
μs
MAX
UNITS
MHz
V
r
o
f
e
s
a
e
8.1.14. 2-Bit & 4-Bit Quantizer (ADC)
SYMBOL
Fo
Tstart
MAX
48.8
5
8.1.15. Integrated Synthesizer
SYMBOL
Fosc
V
DIV
Tstart
PARAMETER
VCO Oscillation Frequency
Tuning Voltage Range
Programmable Divider Ratio
Circuit Start-up time
0.2
32
Vcc-0.2
127
100
μs
8.1.16. Crystal Oscillator (XO)
SYMBOL
Ftcxo
Vtcxo
PARAMETER
TCXO Oscillation Frequency
TCXO output swing
MIN
12.6
0.2
TYP
16.368
0.8
MAX
40
UNITS
MHz
Vpp
8.2. AC Characteristics
8.2.1. RS232 Interface Timing
Baud Rate Required (bps)
4800
9600
14400
19200
38400
57600
115200
921600
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
C
K
IATE
MED
Note:
Programmed Baud Rate (bps)
4800.000
9600.000
14395.778
19188.746
38422.535
57633.803
115267.606
909333.333
X
C
W
_
k
n
i
EEL
Baud Rate Error (%)
0.000
0.000
-0.0293
-0.0586
0.0587
0.0587
0.0587
-1.33
1. UART baud-rate settings with UART_CLK frequency = 16.368MHz (UART_CLK uses the
reference clock of the system).
Page 24 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
Fig. 7 RS232 interface timing diagram
8.2.2. SPI Interface Timing
Description
SCS# setup time
SCS# hold time
SO setup time
SO hold time
SIN setup time
SIN hold time
Symbol
Min
Max
Unit
Notes
T1
T2
T3
T4
T5
T6
0.5T
0.5T
0.5T – 3t
0.5T + 2t
3t
10
0.5T - 2t
0.5T + 3t
-
ns
ns
ns
ns
ns
ns
1
1
1, 2
1, 2
1, 2
1
Note:
1.
The condition of SPI clock cycle (T) is (44/ 12) Mhz ~ (rf_clk / 1020) Mhz.
2. t indicates the period of SPI controller clock, which is 44MHz or rf_clk.
3. 44MHz is the max frequency setting of SPI from PLL.
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
Fig. 8 SPI interface timing diagram
X
C
W
_
k
n
i
EEL
Page 25 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
8.2.3. I2C Interface Timing
Description
I2C_DATA setup time
I2C_DATA hold time
Symbol
T1
T2
Min
0.4T - 10
0.6T - 10
r
o
f
e
s
a
e
Max
0.4T + 10
0.6T + 10
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
Unit
ns
ns
Note:
Notes
1
1
1. The condition of I2C clock cycle (I2C_CLK) is (rf_clk) Mhz ~ (rf_clk / 252) Mhz.
Fig. 9 I2C interface timing diagram
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 26 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
9. Package Dimensions
QFN 48 Outline Dimensions
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
*Package Information
QFN-48 : N
WLCSP : P
TFBGA : A
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 27 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 28 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 29 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
MT3326
Specifications are subject to change without notice
r
o
f
e
s
a
e
l
e
R
l
a
i
t
n
e
d
i
f
n
o
C
K
E
T
A
I
D
ME
X
C
W
_
k
n
i
EEL
ESD CAUTION
MT3326 is ESD (electrostatic discharge) sensitive device and may be damaged with ESD or spike voltage. Although
MT3326 is with built-in ESD protection circuitry, please handle with care to avoid permanent malfunction or
performance degradation.
Use of the GPS Data and Services at the User's Own Risk
The GPS data and navigation services providers, system makers and integrated circuit manufactures
(“Providers”) hereby disclaim any and all guarantees, representations or warranties with respect to the Global
Positioning System (GPS) data or the GPS services provided herein, either expressed or implied, including
but not limited to, the effectiveness, completeness, accuracy, fitness for a particular purpose or the reliability
of the GPS·data or services.
The GPS·data and services are not to be used for safety of life applications, or for any other application in
which the accuracy or reliability of the GPS·data or services could create a situation where personal injury or
death may occur. Any use therewith are at the user’s own risk. The Providers specifically disclaims any and
all liability, including without limitation, indirect, consequential and incidental damages, that may arise in any
way from the use of or reliance on the GPS data or services.
r
o
f
ease
l
e
R
l
a
i
t
n
e
d
i
f
on
MED
C
K
IATE
X
C
W
_
k
n
i
EEL
Page 30 of 30
MEDIATEK CONFIDENTIAL, NO DISCLOSURE
易迪拓培训
专注于微波、射频、天线设计人才的培养
网址：http://www.edatop.com
射 频 和 天 线 设 计 培 训 课 程 推 荐
易迪拓培训(www.edatop.com)由数名来自于研发第一线的资深工程师发起成立，致力并专注于微
波、射频、天线设计研发人才的培养；我们于 2006 年整合合并微波 EDA 网(www.mweda.com)，现
已发展成为国内最大的微波射频和天线设计人才培养基地，成功推出多套微波射频以及天线设计经典
培训课程和 ADS、HFSS 等专业软件使用培训课程，广受客户好评；并先后与人民邮电出版社、电子
工业出版社合作出版了多本专业图书，帮助数万名工程师提升了专业技术能力。客户遍布中兴通讯、
研通高频、埃威航电、国人通信等多家国内知名公司，以及台湾工业技术研究院、永业科技、全一电
子等多家台湾地区企业。
易迪拓培训推荐课程列表： http://www.edatop.com/peixun/tuijian/
射频工程师养成培训课程套装
该套装精选了射频专业基础培训课程、射频仿真设计培训课程和射频电
路测量培训课程三个类别共 30 门视频培训课程和 3 本图书教材；旨在
引领学员全面学习一个射频工程师需要熟悉、理解和掌握的专业知识和
研发设计能力。通过套装的学习，能够让学员完全达到和胜任一个合格
的射频工程师的要求…
课程网址：http://www.edatop.com/peixun/rfe/110.html
手机天线设计培训视频课程
该套课程全面讲授了当前手机天线相关设计技术，内容涵盖了早期的
外置螺旋手机天线设计，最常用的几种手机内置天线类型——如
monopole 天线、PIFA 天线、Loop 天线和 FICA 天线的设计，以及当前
高端智能手机中较常用的金属边框和全金属外壳手机天线的设计；通
过该套课程的学习，可以帮助您快速、全面、系统地学习、了解和掌
握各种类型的手机天线设计，以及天线及其匹配电路的设计和调试...
课程网址： http://www.edatop.com/peixun/antenna/133.html
WiFi 和蓝牙天线设计培训课程
该套课程是李明洋老师应邀给惠普 (HP)公司工程师讲授的 3 天员工内
训课程录像，课程内容是李明洋老师十多年工作经验积累和总结，主要
讲解了 WiFi 天线设计、HFSS 天线设计软件的使用，匹配电路设计调
试、矢量网络分析仪的使用操作、WiFi 射频电路和 PCB Layout 知识，
以及 EMC 问题的分析解决思路等内容。对于正在从事射频设计和天线
设计领域工作的您，绝对值得拥有和学习！…
课程网址：http://www.edatop.com/peixun/antenna/134.html
`
易迪拓培训
专注于微波、射频、天线设计人才的培养
网址：http://www.edatop.com
CST 学习培训课程套装
该培训套装由易迪拓培训联合微波 EDA 网共同推出，是最全面、系统、
专业的 CST 微波工作室培训课程套装，所有课程都由经验丰富的专家授
课，视频教学，可以帮助您从零开始，全面系统地学习 CST 微波工作的
各项功能及其在微波射频、天线设计等领域的设计应用。且购买该套装，
还可超值赠送 3 个月免费学习答疑…
课程网址：http://www.edatop.com/peixun/cst/24.html
HFSS 学习培训课程套装
该套课程套装包含了本站全部 HFSS 培训课程，是迄今国内最全面、最
专业的 HFSS 培训教程套装，可以帮助您从零开始，全面深入学习 HFSS
的各项功能和在多个方面的工程应用。购买套装，更可超值赠送 3 个月
免费学习答疑，随时解答您学习过程中遇到的棘手问题，让您的 HFSS
学习更加轻松顺畅…
课程网址：http://www.edatop.com/peixun/hfss/11.html
ADS 学习培训课程套装
该套装是迄今国内最全面、最权威的 ADS 培训教程，共包含 10 门 ADS
学习培训课程。课程是由具有多年 ADS 使用经验的微波射频与通信系统
设计领域资深专家讲解，并多结合设计实例，由浅入深、详细而又全面
地讲解了 ADS 在微波射频电路设计、通信系统设计和电磁仿真设计方面
的内容。能让您在最短的时间内学会使用 ADS，迅速提升个人技术能力，
把 ADS 真正应用到实际研发工作中去，成为 ADS 设计专家...
课程网址： http://www.edatop.com/peixun/ads/13.html
我们的课程优势：
※ 成立于 2004 年，10 多年丰富的行业经验，
※ 一直致力并专注于微波射频和天线设计工程师的培养，更了解该行业对人才的要求
※ 经验丰富的一线资深工程师讲授，结合实际工程案例，直观、实用、易学
联系我们：
※ 易迪拓培训官网：http://www.edatop.com
※ 微波 EDA 网：http://www.mweda.com
※ 官方淘宝店：http://shop36920890.taobao.com
专注于微波、射频、天线设计人才的培养
易迪拓培训
官方网址：http://www.edatop.com
淘宝网店：http://shop36920890.taobao.com