PRELIMINARY DATA SHEET
SKY74137: RF Transceiver for Multi-Band GSM, GPRS, and
EDGE Applications
Applications
Description
• GSM850, EGSM900, DCS1800, and PCS1900 handsets
The SKY74137 RF transceiver is a highly integrated device for
multi-band Global System for Mobile Communications (GSM),
General Packet Radio Service (GPRS), and/or Enhanced Data Rate
for GSM Evolution (EDGE) receive applications. The device
supports GSM850, EGSM900, DCS1800, and PCS1900
applications.
• GPRS handsets and modules
• EDGE handsets and modules
Features
• Polar Loop™ transmitter on a single chip
• No delay adjustment required
• Integrated quad-band transmit VCO with doubler
• Direct down-conversion receiver
• Four separate LNAs with differential inputs
• Gain selectable in 2 dB steps
• Integrated receive baseband filtering with programmable
bandwidth
• Integrated, low-droop DCOC sequencer
• Meets AM suppression requirements without calibration
• Interfaces to low dynamic range receive ADC
• Single integrated, fully programmable fractional-N synthesizer
suitable for multi-slot EGPRS operation
• Fully integrated wideband UHF VCO
• Integrated loop filters: UHF, transmit AM, transmit PM
• Automatic frequency control possible with fractional-N
synthesizer
• Integrated crystal oscillator maintaining amplifier with
sinusoidal output buffer
• Digital crystal oscillator center frequency control
• Integrated LDO voltage regulators for direct connection to
battery
• Low power standby mode
• Multiplexed and non-multiplexed I/Q input and output lines
• Separate enable lines for transmit, receive, and synthesizer
The receive path implements a direct down-conversion
architecture that eliminates the need for Intermediate Frequency
(IF) components. The transceiver consists of four integrated Low
Noise Amplifiers (LNAs), a quadrature demodulator, selectable
baseband filter bandwidths, and low-droop DC Offset Correction
(DCOC) sequencer.
Similar to its predecessors, Skyworks innovative DCR™
architecture allows for this highly integrated device to be
combined with virtually any standard GSM/EGPRS baseband
without requiring any special processing interfaces.
The device implements Skyworks Polar Loop transmit
architecture. This architecture, while maintaining the traditional
analog In-Phase and Quadrature (I/Q) signals, autonomously splits
the amplitude and phase within the device. The filter-saving
advantage of the translation-loop approach is embedded in the
architecture. Also included is an AM loop that provides both signal
AM and power level control.
The SKY74137 features an integrated, fully programmable,
sigma-delta fractional-N synthesizer suitable for EGPRS multi-slot
operation. The reference frequency for the synthesizer is supplied
by an integrated Voltage Controlled Crystal Oscillator (VCXO)
circuit that enables the use of a low-cost crystal. The VCXO also
provides a buffered reference frequency output to supply other
devices in the system.
Skyworks offers lead (Pb)-free “environmentally
friendly” packaging that is RoHS compliant
(European Parliament for the Restriction of
Hazardous Substances).
• Band selection with three-wire interface
• Low external component count
• RFLGA™ (40-pin, 6 x 6 mm) Pb-free (MSL3, 260 °C per JEDEC
J-STD-020) package with downset paddle
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PRELIMINARY DATA SHEET • SKY74137
The Polar Loop architecture of the SKY74137 enables the use of a
non-linear Power Amplifier (PA) such as Skyworks SKY77331.
Together, these two devices form the Helios™ second generation
(Helios II) EDGE chipset.
are shown in Figure 1. A functional block diagram is shown in
Figure 2. Signal pin assignments, functional pin descriptions, and
equivalent circuitry are provided in Table 1.
TXHB
TXLB
QP/TX_QP
QM/TX_QM
IM/TX_IM
IP/TX_IP
VDIGENA
LOMON
VCC3
The SKY74137 is packaged in a small, 40-pin 6 x 6 mm RF Land
Grid Array (RFLGA) package. The pin configuration and package
40
39
38
37
36
35
34
33
32
N/C or RX_QP
850LNA_N
4
28
N/C or RX_QM
850LNA_P
5
27
CHIPENA
900LNA_N
6
26
SXENA
900LNA_P
7
25
CLK
1800LNA_N
8
24
LATCHENABLE
1800LNA_P
9
23
DATAIN
1900LNA_N
10
22
VCC2
1900LNA_P
11
21
XTAL
RXENA
12
13
14
15
16
17
18
19
20
XTUNE
29
LPFADJ
3
13MHZ_26MHZ
or XBUF
N/C or RX_IM
VPC
COMPP
30
COMPN
N/C or RX_IP
2
VAPC
31
TXENA
VCC4
1
TXRFin
VCC1
S481
Figure 1. SKY74137 Pinout – 40-Pin RFLGA (Top View)
1/2-LO Mixers
DCOC1
1900LNA
DCOC2
DCOC3
DCOC4
DCOC5
1900
1800LNA
RXI
1800
gmC1
and
PGA1
Sallen Key
LPF
gmC2
and
Aux
PGA2
RXQ
900LNA
900
850LNA
M
U
X
Sigma Delta
Fractional-N PLL
850
/3
Q
/2
/3
3 GHz
UHF VCO
CLK
DATAIN
LATCHENABLE
Bus Interface
and Registers
Crystal
Osc
TXHB
XTAL
13MHZ_26MHZ,
XBUF
PFD
One VCO + Doubler
I
TXLB
TXI
Baseband VGA
TXQ
CHIPENA
VDIGENA
VPC
IF VGA
/9/10
/11/12
/13/14
LDOs
TXRFin
VCC1
VCC2
VCC3
VCC4
VAPC
X2
S514
Figure 2. SKY74137 RF Transceiver Block Diagram
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PRELIMINARY DATA SHEET • SKY74137
Table 1. SKY74137 Signal Descriptions (1 of 3)
Pin #
Name
Description
1
VCC1
Voltage supply 1
2
TXENA
Transmitter enable
3
VPC
Output to PA
4
850LNA_N
Negative 850 MHz LNA input.
5
850LNA_P
Positive 850 MHz LNA input.
6
900LNA_N
Negative 900 MHz LNA input.
7
900LNA_P
Positive 900 MHz LNA input.
8
1800LNA_N
Negative 1800 MHz LNA input.
9
1800LNA_P
Positive 1800 MHz LNA input.
10
1900LNA_N
Negative 1900 MHz LNA input.
11
1900LNA_P
Positive 1900 MHz LNA input.
12
RXENA
Receiver enable
13
VCC4
Voltage supply 4
14
TXRFin
Transmit feedback input.
15
VAPC
VGA gain control input (takes analog signal from baseband ramp
signal).
16
COMPP
Positive node for access to on-chip dominant pole filter.
17
COMPN
Negative node for access to on-chip dominant pole filter.
Equivalent Circuits
Vout
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PRELIMINARY DATA SHEET • SKY74137
Table 1. SKY74137 Signal Descriptions (2 of 3)
Pin #
Name
Description
18
LPFADJ
Receiver low pass bandwidth adjust.
19
13MHZ_26MHZ or XBUF
Select 13 MHz or 26 MHz output with a DC signal connection. XBUF
provides the buffered reference signal to the baseband (a DCblocking capacitor is needed).
20
XTUNE
Crystal oscillator varactor control.
21
XTAL
Crystal/external reference.
22
VCC2
Voltage supply 2
23
DATAIN
Data input (serial interface)
24
LATCHENABLE
Latch enable (serial interface)
25
CLK
Clock input (serial interface)
26
SXENA
Synthesizer enable
27
CHIPENA
Master enable for all LDOs.
28
N/C or RX_QM
No connection. Negative receiver Q output if separate
transmit/receive I/Q is required.
29
N/C or RX_QP
No connection. Positive receiver Q output if separate transmit/receive
I/Q is required.
30
N/C or RX_IM
No connection. Negative receiver I output if separate transmit/receive
I/Q is required.
31
N/C or RX_IP
No connection. Positive receiver I output if separate transmit/receive
I/Q isrequired.
Equivalent Circuits
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PRELIMINARY DATA SHEET • SKY74137
Table 1. SKY74137 Signal Descriptions (3 of 3)
Pin #
Name
Description
32
VCC3
Voltage supply 3
33
LOMON
Monitors UHF VCO signal.
34
VDIGENA
LDO enable for serial interface and registers.
35
IP/TX_IP
Positive I channel if using multiplex transmit/receive I/Q. Positive
transmit I channel in non-multiplex mode.
36
IM/TX_IM
Negative I channel if using multiplex transmit/receive I/Q. Negative
transmit I channel in non-multiplex mode.
37
QM/TX_QM
Negative Q channel if using multiplex transmit/receive I/Q. Negative
transmit Q channel in non-multiplex mode.
38
QP/TX_QP
Positive Q channel if using multiplex transmit/receive I/Q. Positive
transmit Q channel in non-multiplex mode.
39
TXLB
Transmitter VCO low band output.
40
TXHB
Transmitter VCO high band output.
Technical Description
The SKY74137 RF transceiver contains the following sections, as
shown in Figure 2.
• Receive section. Includes: four integrated, differential LNAs;
quadrature demodulator circuitry that performs direct downconversion; baseband amplifier circuitry with I/Q outputs;
baseband filter with programmable bandwidths; and five stages
of DCOC. The SKY74137 achieves high IP2 without the need for
IP2 calibration.
• Synthesizer section. Includes an integrated on-chip VCO
locked by a fractional-N synthesizer loop, a crystal oscillator to
supply the reference frequency, a reference frequency output
buffer, and an integrated loop filter.
• Transmit section. The SKY74137 implements the entire
Skyworks Polar Loop transmit architecture on a single chip
(including both Amplitude Modulation [AM] and Phase
Modulation [PM] loops). The AM loop sets the amplitude at the
PA, which controls the EDGE signal AM, power level, and
Equivalent Circuits
ramping. This loop includes AM detectors, error extractor,
baseband Variable Gain Amplifier (VGA), on-chip loop filter, and
output buffer. The PM loop is a frequency translation loop
traditionally used for Gaussian Minimum Shift Keying (GMSK);
its low noise output requires no external filters. This loop
includes a Phase-Frequency Detector (PFD), charge pump, onchip loop filter, and integrated high-power transmit VCOs.
The wide bandwidth of both loops ensures accurate modulation
and excellent spectral performance with no adjustments (e.g.,
there is no provision for a “delay adjustment,” since none is
required). The only calibration needed is for the absolute PA
power level. Common to both loops are the downconversion
mixer, IF VGA, and I/Q modulator.
The receiver I/Q outputs are multiplexed with the transmitter I/Q
inputs so that only four pins are used for all I/Q signals.
If a separate transmit/receive I/Q is required, as in the case of
dual-mode WCDMA/GPRS operation, four additional pins are
provided (pins 28 to 31).
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PRELIMINARY DATA SHEET • SKY74137
fixed conjugate pole pairs, and one programmable conjugate pole
pair. The result is a flat passband with minimal group delay
distortion at any bandwidth setting.
A three-wire serial interface controls the transceiver and
synthesizer. Band selection, receiver gain control, and the division
ratios and charge pump currents in the synthesizer and
transmitter are programmed using 24-bit words. These 24-bit
words are programmed using the three-wire input signals CLK,
DATAIN, and LATCHENABLE.
DC Offset Correction (DCOC)
The TXENA, RXENA, and SXENA signals separately enable the
SKY74137 transmitter, receiver, and synthesizer sections,
respectively. It is also possible to enable the transmitter, receiver,
and synthesizer sections using the three-wire serial interface.
Five DCOC loops ensure that DC offsets generated in the
SKY74137 do not overload the baseband chain at any point. After
correction, the corrected voltages are held digitally for the
duration of the receive slot(s).
Receive Section
LNA and Quadrature Demodulator
Four separate LNAs are integrated in the SKY74137 to address
different bands of operation. These LNAs have separate
differential inputs, which are nominally 150 Ω and, therefore,
easily matched to the most common GSM Surface Acoustic Wave
(SAW) filters. The LNA gain is switchable between high and low
settings using the three-wire bus.
The LNA outputs feed into a quadrature demodulator that downconverts the RF signals directly to baseband. The baseband I and
Q paths consist of cascaded amplifiers and low pass filter
sections. The baseband section provides eight programmable
bandwidth settings in 10 kHz increments, from 90 kHz to
160 kHz. This provides added flexibility when interfacing to any
mixed signal baseband device.
Overall receiver gain stages are depicted in Figure 3.
The positive edge of the RXENA signal starts the digital DCOC. A
special, fast DCOC is carried out every time the receiver gain is
programmed while RXENA is high. This ensures that a DCOC is
complete in the time available, even if the gain is changed
between slots in multislot mode.
The DCOC timing diagram is shown in Figure 4.
AM Suppression and IP2 Calibration
For direct conversion GSM applications, it is imperative to have
extremely low second-order distortion. Mathematically, secondorder distortion of a constant tone generates a DC term
proportional to the square of the amplitude. In general, a strong
interfering Amplitude Modulated (AM) signal is, therefore,
demodulated by second-order distortion, which generates an ACinterfering baseband signal. The SKY74137 can effectively handle
such AM-modulated interferers.
All baseband filtering is provided on-chip using no external
capacitors. The filter chain consists of two fixed real poles, two
SKY74137
LO
DCOC 1
DCOC 2
DCOC 3
DCOC 4
DCOC 5
RXI+
RXI–
–25.2 dBv
55 mV RMS
3 dB
RXQ+
RXQ–
Gain LNA
Mixer
LPF1
gmC1/PGA1
gmC2
PGA2
High Gain, 15 dB
+40 dB
–12, –2, +6, +16 dB
18 dB
Low Gain, –5 dB
+22 dB
0 dB
0 dB
Gain Step, 20 dB
+18 dB
+2 dB
+6 dB
30 dB
S659
Figure 3. SKY74137 Analog Gain Stages
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PRELIMINARY DATA SHEET • SKY74137
fref
fref/M
RXena
DCOC 1
DCOC 2
tDC1
tDC2
tDC3
DCOC 3
tDC4
DCOC 4
tDC5
DCOC 5
tFEENA
FEena
LNA Enabled
Receive Slot
S660
Figure 4. SKY74137 DCOC Timing Diagram
A commonly used measure for receiver second-order distortion is
the second-order intercept point, IP2. For example, to ensure that
the unwanted baseband signals are 9 dB below the wanted signal
required under the AM suppression test for type approval (see
3GPP TS 51.010-1), an input IP2 of 43 dBm is required.
synthesizer phase-locks the Local Oscillator (LO) used in both
transmit and receive paths to a precision frequency reference
input. Fractional-N operation offers low phase noise and fast
settling times, allowing for multiple slot applications such as
GPRS.
The SKY74137 IP2 meets the GSM AM suppression test
requirements in all bands with good margin and without
calibration.
The SKY74137 frequency stepping function with a 3 Hz resolution
allows quad band operation in both transmit and receive bands
using a fully integrated on-chip UHF VCO. The fine synthesizer
resolution allows direct compensation or adjustment for reference
frequency errors.
Flexible Receiver Bandwidth Control
The receiver baseband filters have programmable bandwidths
with eight possible settings. For easy bandwidth switching during
operation, two individual bandwidth settings are defined:
“Bandwidth A” and “Bandwidth B.”
The fractional-N synthesizer consists of the following:
When the B/W and DC Offset Control Register is programmed
(during device initialization, for example), “Bandwidth A” and
“Bandwidth B” can each be assigned any of the eight possible
bandwidths. The active setting (A or B) is then selected using bit
[18] of the T/R Register (RX BW). This allows for fast and easy
switching between two receiver bandwidths during a call, without
programming any additional registers. Typically, two different
bandwidths need to be used for EDGE signals and GMSK signals
to optimize reception of each.
• N-divider with a sigma-delta modulator
Synthesizer Section
• VCO
• High frequency prescaler
• Reference buffer and divider
• Integrated loop filter
• Fast PFD and charge pump
The user must provide the following three parameters:
• Reference divider value from 1 to 2
• N-divider value in a manner similar to an integer-N synthesizer
• A fractional ratio
The SKY74137 includes a fully integrated UHF VCO with an onchip 3rd order loop filter. A single sigma-delta fractional-N
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PRELIMINARY DATA SHEET • SKY74137
The generated frequency is given by the following equation:
fVCO
where: fvco
N
FN
R
fref
FN ⎞
⎛
2 ⎜ N + 3.0 + 22 ⎟ f ref
2 ⎠
= ⎝
R
= Generated VCO frequency
= N-divider ratio, integer part
= Fractional setting
= R-divider ratio
= Reference frequency
UHF Phase Locked Loop (PLL) Frequency Setting
In the SKY74137, the 3 GHz VCO is followed by a divide-by-two
and divide-by-three inside the UHF PLL. To tune the receive
frequency, the UHF PLL is set according to the following
equations:
GSM850/900:
fVCO = 3 × f RX
DCS1800 and PCS1900:
fVCO =
3
× f RX
2
In the transmit mode, the first IF (IF1) subtracted from the second
IF (IF2) determines the transmit frequency as follows:
FTX = IF2 − IF1
F
Where: IF2 = VCO in the low band
3
or,
IF2 =
FVCO
in the high band
2×3
F
IF1 = VCO , where D1 = 9, 10, 11, or 12
3 D1
or,
IF1 =
FVCO
, where D2 = 13 or 14
2 D2
Therefore, the transmit frequency in the low band, when the D1
divider is selected is:
FTX = FVCO
⎛ D − 1⎞
⎟
⎜ 1
⎜ 3D ⎟
1 ⎠
⎝
Or, when the D2 divider is selected:
⎛ D − 1.5 ⎞
⎟
FTX = FVCO ⎜ 2
⎟
⎜ 3D
2 ⎠
⎝
The transmit frequency in the high band, when the D1 divider is
selected is:
FTX = FVCO
⎛ 2D − 1 ⎞
⎟
⎜ 1
⎜ 3D ⎟
1 ⎠
⎝
Or, when the D2 divider is selected:
⎛ 2 D − 1.5 ⎞
⎟
FTX = FVCO ⎜ 2
⎟
⎜ 3D
2 ⎠
⎝
Digital Frequency Centering
The SKY74137 re-centers the UHF VCO frequency range each
time the synthesizer is programmed. This proprietary Skyworks
technique, called Digital Frequency Centering (DFC) extends the
VCO frequency coverage, speeds up settling time, and ensures
robust performance since the VCO is always operated at the
center of its tuning range.
Each time the synthesizer is programmed, the DFC circuit is
activated and the VCO is centered to the programmed frequency
in less than 20 µs. After this, normal PLL operation is resumed
and the fine settling of the frequency is finalized.
DFC typically adjusts the 3 GHz VCO center frequency to within a
few MHz and no more than 10 MHz offset, and presets the tuning
voltage to the center of the range before the PLL takes over. This
speeds up frequency settling and ensures that the PLL control
voltage never operates close to the rails.
DFC is the result of an adaptive circuit that corrects for any VCO
center frequency errors caused by variations of the integrated
VCO circuit, temperature, supply voltage, aging, etc. The 3 GHz
VCO can be centered at any frequency in the range from 2607
MHz to 3103 MHz. Once centered, the VCO has a minimum
analog tuning range of 20 MHz.
No calibration or data storage is needed for DFC operation. It is
activated by one of two events:
• When the synthesizer is programmed, the rising edge of the
LATCHENABLE signal starts the DFC cycle
• When the SXENA signal level is changed from low to high,
which enables the synthesizer, the rising edge of the SXENA
signal starts the DFC cycle
Integrated Loop Filters
Both loop filters (for the UHF PLL and for the transmit PLL) are
fully integrated on-chip. Several adjustments can be made to the
PLL transfer functions.
Charge Pump Current Compensation for Constant PLL Bandwidth
The VCOs in the SKY74137 use the Skyworks DFC technique. The
nature of the DFC circuit increases the VCO control sensitivity
(KVCO) as the VCO frequency is increased. Without any
compensation, this leads to an increase in the PLL loop gain and
an increased loop bandwidth for higher frequencies.
In a classical PLL design, KVCO is typically regarded as a constant.
In this case, the loop gain decreases with increased frequency as
the division ratio of the loop is increased proportionally to
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PRELIMINARY DATA SHEET • SKY74137
frequency. Since it is desirable to keep the loop bandwidth
constant over the frequency range of interest, the SKY74137
includes a circuit that compensates the charge pump current to
keep the overall loop gain constant.
Charge pump current compensation for the UHF PLL can be
programmed to one of three settings (nominal, high, or low) or the
charge pump current can be programmed to a constant value
without compensation. The charge pump current settings and
compensation are set in the SX3 Register.
Crystal Oscillator
A 26 MHz crystal oscillator provides the reference frequency for
the synthesizer. As shown in Figure 5, the oscillator uses an
external 26 MHz crystal to generate an accurate reference
frequency. The reference frequency can be changed through
coarse-tuning with an integrated capacitor array or fine-tuning
with the integrated varactor diode.
The oscillator is coarse-tuned by switching in and out (using a
digital word programmed with the serial interface) the capacitor
network (CAP_A and CAP_B) located at the input of the integrated
buffer. The oscillator is fine-tuned by providing a tuning voltage to
the integrated varactor diode.
An output buffer is provided to drive the baseband circuitry. The
frequency of the output is determined by pin 19 (13MHZ_26MHZ).
When this pin is connected to ground, the output is 13 MHz; when
connected to VCC or left floating, the output is 26 MHz. The
oscillator core powers up when the CHIPENA signal (pin 27) is set
to logic 1.
Amplitude Loop
In the amplitude loop, the reference signal from the I/Q modulator
and the feedback signal from the IF VGA each pass through AM
detectors before their amplitude is compared at the error
extractor. The error is amplified by a baseband VGA and low-pass
filtered to produce the PA amplitude control signal. The power
level is autonomously controlled by the gain of the two VGAs once
the traditional VAPC signal for power control has been applied.
Phase Loop
In the phase loop, the reference signal from the I/Q modulator and
the feedback signal from the IF VGA each pass through limiters
before their phase is compared at the PFD. The phase-locked
transmit VCO then drives the PA with a signal containing only the
phase modulation.
Transmit VCOs
The on-chip transmit VCO and a doubler are designed to meet
GSM850, EGSM900, DCS1800, and PCS1900 requirements. The
transmit VCO uses the same DFC technique as the synthesizer
section to center the VCO frequency. The rising edge on TXENA
initializes the transmit DFC. The output buffers feed the signal to
the external PAs. Two transmit buffers are provided, one for the
low band VCO and the other for the high band VCO.
With GSM850 and EGSM900 operation, the VCO output is fed
directly to the low band transmit buffer. To save current in
DCS1800 and PCS1900 operation, the VCO is followed with a
doubler before the high band transmit output buffer.
The fractional-N synthesizer should be programmed and
operating before the transmit section can be activated. The timing
requirements are shown in Figure 6.
Transmit Section
The SKY74137 implements the entire Skyworks Polar Loop
transmit architecture on a single chip, including both amplitude
and phase loops. The transmitter is provided a coupled feedback
signal from the PA and downconverts it to an IF. Following an IF
VGA, this feedback signal is fed to both loops. The reference for
both loops is a transmit IF signal produced by an I/Q modulator.
SKY74137
To Synthesizer
Crystal
÷2
XBUF,
13 MHZ_26MHZ
Vc
CAP_A/CAP_B
S179c
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PRELIMINARY DATA SHEET • SKY74137
Figure 5. Crystal Oscillator Block Diagram
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PRELIMINARY DATA SHEET • SKY74137
Frac PLL
Prog
Frac Mod
Prog
Receive/Transmit
Prog
Data
Word
t1
t1> 0 and t2> 0
SXENA
t2
TXENA
S018
Figure 6. Transmit Timing Diagram
Low Drop-Out (LDO) Linear Voltage Regulators
The SKY74137 includes integrated LDO linear voltage regulators
to eliminate the need for a separate power management
integrated circuit or discrete voltage regulators. Each functional
block in the SKY74137 includes a separate, internal LDO voltage
regulator.
Modes of Operation
The SKY74137 offers several possible modes of operation
determined by the logic setting of five pin signals:
• CHIPENA (pin 27)
• VDIGENA (pin 34)
• SXENA (pin 26)
• TXENA (pin 2)
• RXENA (pin 12)
The SXENA, TXENA, and RXENA signals can also be programmed
using the serial interface.
can be programmed off. The three-wire bus is enabled and initial
programming may also take place.
NOTE: If VDIGENA is hardwired permanently to logic high
(VBAT), the power modes of the SKY74137 operate
identically to those of the SKY74117 RF Transceiver.
Following power up, the synthesizer, receiver, and transmitter
sections may be enabled by the SXENA, RXENA, or TXENA signals,
respectively, or by programming the three-wire bus.
NOTE: The CHIPENA signal, by itself, is sufficient to power up
the device. However, VDIGENA must be brought high
before the first sleep cycle.
When the CHIPENA signal is held low while the VDIGENA signal is
held high, the device is placed in sleep mode. This is a maximum
power-saving mode where the only the digital section of the
device has power while all LDOs for RF functions are shut down.
Therefore, even the LDO bypass currents are saved. During sleep,
the crystal oscillator shuts down. The device still holds its control
registers and can still be programmed by the three-wire bus.
All four VCC signals (pins 1, 13, 22, and 32) connect directly to
the battery. The battery and its charging supply must not exceed
4.5 V. The device remains completely powered off as long as the
CHIPENA and VDIGENA signals are held low. When powered off,
only the over-voltage protection circuits are operational and the
current draw is extremely low.
The sleep/wake cycle is controlled simply by setting CHIPENA low
or high. When the device wakes up, the crystal oscillator powers
back up unless it was previously programmed off. In this case, it
remains off.
In normal operation, both the CHIPENA and VDIGENA signals are
brought high simultaneously to power up the device (if only the
VDIGENA signal is held high, the device will not power up).
Precise timing is not required (i.e., either of the two signals may
reach a logic high first). Within 200 µs, a power-on reset occurs
that preloads all of the control registers with default values. The
LDOs for all sections of the device are enabled and the crystal
oscillator starts. If the crystal oscillator function is not desired, it
A typical enable timing sequence is provided in Figure 7, which
shows the various modes of operation and the relevant transition
between various states.
The device is completely powered down by setting both CHIPENA
and VDIGENA low. The precise order is not critical.
The band select function of the SKY74137 is accessed using the
serial interface (bits [17:16] of the T/R Register). Detailed register
descriptions are provided in the Skyworks Programming Guide,
*** TBD ***, document number TBD.
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PRELIMINARY DATA SHEET • SKY74137
Off
Tx, Rx, Sx Off
Sx
On
Tx
On
Tx
Off
Rx
On
Rx
Off
Tx, Rx, Sx Off
Sleep
VCC1
VCC2
VCC3
CHIPENA
Program SX Register 3
bit [11] = 0
"Wake"
occurs
VDIGENA
Program registers
if required
SXENA
TXENA
RXENA
S436a
Figure 7. Typical Enable Signal Timing Diagram Showing Modes of Operation
Package and Handling Information
Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipment according to IPC JSTD 033 guidelines. Instructions on the shipping container label
regarding exposure to moisture after the container seal is broken
must be followed. These instructions adhere to IPC J-STD 020A
guidelines for handling moisture sensitive devices. If these
instructions are not followed, problems related to moisture
absorption may occur when the part is subjected to high
temperature during solder assembly.
The SKY74137 is rated to Moisture Sensitivity Level 3 (MSL 3) at
260 °C. It can be used for lead or lead-free soldering. If the device
is attached in a reflow oven, the temperature ramp rate should
not exceed 5 °C per second. Maximum temperature should not
exceed 260 °C.
If the SKY74137 is manually attached, precaution should be taken
to ensure that the part is not subjected to a temperature
exceeding 260 °C for more than 10 seconds.
For additional details on both attachment techniques, precautions,
and recommended handling procedures, refer to the Skyworks
Application Note, PCB Design and SMT Assembly Guidelines for
RFLGA Packages, document number 103147. Additional
information on standard SMT reflow profiles can also be found in
the JEDEC Standard J-STD-020B.
Production quantities of this product are shipped in a standard
tape and reel format. For packaging details, refer to the Skyworks
Application Note, Tape and Reel, document number 101568.
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY74137 are provided in
Table 2. The recommended operating conditions are specified in
Table 3 and power consumption specifications are provided in
Table 4. Electrical specifications are provided in Tables 5 through
11.
Figures 8 through 11 illustrate typical baseband and LNA
measurements. Figure 12 shows a typical application circuit
diagram for the Helios II EDGE RF Subsystem (the SKY74137
Transceiver and SKY77331 PA). The phone board layout footprint
for the SKY74137 is provided in Figure 13. Package dimensions
for the 40-pin RFLGA are shown in Figure 14 and Figure 15
provides the tape and reel dimensions.
Electrostatic Discharge (ESD) Sensitivity
The SKY74137 is a static-sensitive electronic device. Do not
operate or store near strong electrostatic fields. Take proper ESD
precautions.
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PRELIMINARY DATA SHEET • SKY74137
Table 2. SKY74137 Absolute Maximum Ratings
Parameter
Minimum
Maximum
Units
Supply voltage (VCC)
–0.3
+4.5
V
Ambient operating temperature range
–40
+95
°C
Storage temperature range
–50
+125
°C
Input voltage range
GND
VCC
V
600
mW
Maximum power dissipation
Note:
Stresses above these absolute maximum ratings may cause permanent damage. These are stress ratings only and functional operation at these conditions is not implied. Exposure to
maximum rating conditions for extended periods may reduce device reliability.
Table 3. SKY74137 Recommended Operating Conditions
Parameter
Minimum
Typical
Maximum
Units
3.1
3.6
4.5
V
Power supply (VCC1, VCC2, VCC3, VCC4)
Operating junction temperature
–40
+110
°C
Operating ambient temperature
–30
+85
°C
10
dBm
LNA input level, RXEN = On
Table 4. Power Consumption (1 of 2)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Total supply current (VCC1, VCC2, VCC3, and VCC4):
Symbol
Test Condition
Min
Typical
Max
Units
ICC
Off mode
RXENA = low, SXENA = low,
TXENA = low, CHIPENA = low.
Program SX Register 3
(bit [11] = 0) if entering this
state from any other state.
26
60
µA
Sleep mode
RXENA = low, SXENA = low,
TXENA = low, CHIPENA = low.
SX Register 3, bit [11] = 1.
45
85
µA
Standby mode 1 (internal crystal oscillator and crystal
output buffer)
RXENA = low, SXENA = low,
TXENA = low, CHIPENA = high
4.0
mA
Standby mode 2 (external crystal oscillator and
internal crystal output buffer)
RXENA = low, SXENA = low,
TXENA = low, CHIPENA = high.
Program device to shut off
internal crystal oscillator.
3.0
mA
Standby mode 3 (external crystal oscillator only;
internal crystal output buffer is shut off)
RXENA = low, SXENA = low,
TXENA = low, CHIPENA = high.
Program device to shut off
internal crystal oscillator and
crystal output buffer.
1.0
mA
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PRELIMINARY DATA SHEET • SKY74137
Table 4. Power Consumption (2 of 2)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Total supply current (VCC1, VCC2, VCC3, and VCC4):
Test Condition
Min
Typical
Max
Units
ICC
Synthesizer active mode (GSM850/EGSM900)
RXENA = low, SXENA = high,
TXENA = low, CHIPENA = high.
Program device to low band.
35
mA
Synthesizer active mode (DCS1800/PCS1900)
RXENA = low, SXENA = high,
TXENA = low, CHIPENA = high.
Program device to high band.
35
mA
Receiver active mode (GSM850/EGSM900)
RXENA = high, SXENA = high,
TXENA = low, CHIPENA = high.
Program device to low band.
80
mA
Receiver active mode (DCS1800/PCS1900)
RXENA = high, SXENA = high,
TXENA = low, CHIPENA = high.
Program device to high band.
80
mA
Transmitter active mode (GSM850/EGSM900)
RXENA = low, SXENA = high,
TXENA = high, CHIPENA = high.
Program device to low band.
140
mA
Transmitter active mode (DCS1800/PCS1900)
RXENA = low, SXENA = high,
TXENA = high, CHIPENA = high.
Program device to high band.
140
mA
Table 5. SKY74137 Electrical Specifications – Receiver (1 of 3)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Input operating frequency:
GSM850
EGSM900
DCS1800
PCS1900
Test Condition
GSM850 receive band
EGSM900 receive band
DCS1800 receive band
PCS1900 receive band
Input impedance:
GSM850
EGSM900
DCS1800
PCS1900
ZIN
Receiver maximum voltage gain:
GSM850
EGSM900
DCS1800
PCS1900
GRXMAX
Receiver minimum voltage gain:
GSM850
EGSM900
DCS1800
PCS1900
GRXMIN
Receiver gain temperature variation:
GSM850
EGSM900
DCS1800
PCS1900
GTEMPVAR
Min
Typical
869
925
1805
1930
Max
Units
894
960
1880
1990
MHz
MHz
MHz
MHz
Ω
Ω
Ω
Ω
fC = 880 MHz
fC = 950 MHz
fC = 1840 MHz
fC = 1960 MHz
Highest gain mode
121
120
124
122
dB
dB
dB
dB
10
10
17
15
dB
dB
dB
dB
Lowest gain mode
TA = –20 °C to +85 °C
4.5
4.5
4.5
4.5
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dB
dB
dB
dB
PRELIMINARY DATA SHEET • SKY74137
Table 5. SKY74137 Electrical Specifications – Receiver (2 of 3)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Gain step:
GSM850
EGSM900
DCS1800
PCS1900
∆AV
Gain step accuracy:
GSM850
EGSM900
DCS1800
PCS1900
GSTEP
Gain variation versus frequency:
GSM850
EGSM900
DCS1800
PCS1900
GFREQ
Noise Figure:
GSM850
EGSM900
DCS1800
PCS1900
NFGAIN1
Noise Figure (temperature):
GSM850
EGSM900
DCS1800
PCS1900
NFTEMP
Noise Figure degradation in presence of
3 MHz blocker:
GSM850
NFBLOC
Test Condition
Min
Typical
Max
dB
dB
dB
dB
2
2
2
2
–0.75
–0.75
–0.75
–0.75
Over 869-894 MHz
Over 925-960 MHz
Over 1805-1880 MHz
Over 1930-1990 MHz
Units
+0.75
+0.75
+0.75
+0.75
dB
dB
dB
dB
2
2
2
2
dB
dB
dB
dB
dB
dB
dB
dB
2.5
2.5
3.0
3.0
TA = +85 °C
4.0
4.0
4.4
4.4
dB
dB
dB
dB
With –26 dBm input
blocker @ 3 MHz offset
dB
EGSM900
With –26 dBm input
blocker @ 3 MHz offset
dB
DCS1800
With –29 dBm input
blocker @ 3 MHz offset
dB
PCS1900
With –29 dBm input
blocker @ 3 MHz offset
dB
Input 2nd order intercept point:
GSM850
EGSM900
DCS1800
PCS1900
IIP2
DC shift in presence of blocker:
GSM850
AM Supp
Referred to LNA input
calibrated and measured
at middle of band.
40
40
40
40
dBm
dBm
dBm
dBm
55
55
55
55
With –34 dBm @ 6 MHz
offset and calibrated.
20
mV
EGSM900
With –34 dBm @ 6 MHz
offset.
20
mV
DCS1800
With –35 dBm @ 6 MHz
offset
20
mV
PCS1900
With –35 dBm @ 6 MHz
offset
20
mV
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PRELIMINARY DATA SHEET • SKY74137
Table 5. SKY74137 Electrical Specifications – Receiver (3 of 3)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
I/Q amplitude imbalance:
GSM850
EGSM900
DCS1800
PCS1900
TA = –20 °C to +85 °C
I/Q phase imbalance:
GSM850
EGSM900
DCS1800
PCS1900
TA = –20 °C to +85 °C
Min
Typical
–3
–3
–3
–3
3rd order input intercept point @ +25 °C:
GSM850
EGSM900
DCS1800
PCS1900
IIP3
3rd order input intercept point @ –20 °C:
GSM850
EGSM900
DCS1800
PCS1900
IIP3
Output offset voltage:
GSM850
F = 800 kHz/+1.6 MHz,
F = –800 kHz/–1.6 MHz
F = +800 kHz/+1.6 MHz,
F = –800 kHz/–1.6 MHz
Max
Units
1.0
1.0
1.0
1.0
dB
dB
dB
dB
+3
+3
+3
+3
degrees
degrees
degrees
degrees
–17
–17
–20
–20
–16
–16
–19
–19
dBm
dBm
dBm
dBm
–19
–19
–22
–22
–18
–18
–21
–21
dBm
dBm
dBm
dBm
TA = +25 °C
TA = +85 °C
200
220
mV
mV
EGSM900
TA = +25 °C
TA = +85 °C
200
220
mV
mV
DCS1800
TA = +25 °C
TA = +85 °C
200
220
mV
mV
PCS1900
TA = +25 °C
TA = +85 °C
200
220
mV
mV
20
20
20
20
mV
mV
mV
mV
5
5
5
5
mV
mV
mV
mV
Offset drift (long term):
GSM850
EGSM900
DCS1800
PCS1900
DCDRFT1
Offset drift (short term):
GSM850
EGSM900
DCS1800
PCS1900
DCDRFT2
100 ms after correction
577 µs after correction
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PRELIMINARY DATA SHEET • SKY74137
Table 6. SKY74137 Electrical Specifications – Baseband Filter
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Selectivity with baseband selectable active
filter at setting 5 (110 kHz)
Test Condition
Min
@ 3 MHz offset
@ 1.6 MHz offset
@ 600 kHz offset
@ 400 kHz offset
@ 200 kHz offset
TA = –20 °C to +85 °C
Typical
Max
Units
dB
dB
dB
dB
dB
>140
>130
67
55
16
3 dB corner frequency (setting 0)
FC 0
90
kHz
3 dB corner frequency (setting 1)
FC 1
100
kHz
3 dB corner frequency (setting 2)
FC 2
110
kHz
3 dB corner frequency (setting 3)
FC 3
120
kHz
3 dB corner frequency (setting 4)
FC 4
130
kHz
3 dB corner frequency (setting 5)
FC 5
140
kHz
3 dB corner frequency (setting 6)
FC 6
150
kHz
3 dB corner frequency (setting 7)
FC 7
160
kHz
Table 7. SKY74137 Electrical Specifications – Receiver Output Stage
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Differential output swing capacity
(pk/pk differential)
Output common mode voltage
Maximum current drive
Test Condition
Min
Typical
ROUT
Output capacitance
COUT
Units
VGA2 = 18 dB
2.5
V
VGA2 = 0 dB
0.3
V
TA = –20 °C to +85 °C
1.25
1.35
IOUT
Output resistance
Max
160
200
1.45
V
0.5
mA
240
Ω
1
pF
Table 8. SKY74137 Electrical Specifications – Transmitter (1 of 3)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
Units
16
20
24
kΩ
Transmitter: I/Q Modulator
Differential input impedance
ZIN
Input signal level
0.9
1
1.1
Vp-p
VCM
Differential
1.15
1.35
1.55
V
Output operating frequency, IF
IFOUT
70
200
MHz
Output noise power
NO
–128
–126
dBc/Hz
dBc/Hz
Input common mode voltage range
Input frequency 3 dB bandwidth
LO suppression
3
@ 10 MHz offset
@ 1.8 MHz offset
@ VCO output
Sideband suppression
–132
–130
MHz
30
35
dBc
30
35
dBc
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PRELIMINARY DATA SHEET • SKY74137
Table 8. SKY74137 Electrical Specifications – Transmitter (2 of 3)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
Units
Translational Loop
Transmit frequency (input from VCO)
FTX
800
2000
MHz
IF frequency
FIF
80
120
MHz
Transmitter output phase noise (includes
transmit VCO and LO PLL):
GSM850
NOPH
@ 400 kHz offset
@ 1.8 MHz offset
@ 10 MHz offset
@20 MHz offset
–120
–130
–152
–165
–118
–124
–150
–162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
EGSM900
@ 400 kHz offset
@ 1.8 MHz offset
@ 10 MHz offset
@20 MHz offset
–120
–130
–152
–165
–118
–124
–150
–162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
DCS1800
@ 400 kHz offset
@ 1.8 MHz offset
@ 10 MHz offset
@20 MHz offset
–120
–130
–152
–156
–120
–130
–152
–154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
PCS1900
@ 400 kHz offset
@ 1.8 MHz offset
@ 10 MHz offset
@20 MHz offset
–120
–130
–152
–156
–120
–130
–152
–154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Transmit phase error:
GSM850
EGSM900
DCS1800
PCS1900
TXPHERR
degrees rms
degrees rms
degrees rms
degrees rms
1.5
1.5
2.0
2.0
Low Band Translation Loop VCO
TA = –20 °C to +85 °C
Frequency Range
fC
800
930
Digital frequency centering resolution
eDFC
Digital frequency centering time
tDFC
From rising edge of TXENA
(13 MHz clock frequency)
12
Digital frequency centering voltage
VDCF
(Control voltage at end of
DFC/start of analog lock)
1.1
Analog frequency control range
fMAX – fMIN
0.5 < VCTL < 2.2
Absolute control sensitivity
KVCO
(0.9 V < VCTL and
1.9 V > VCTL)
2.5
Output harmonics
2nd harmonic
3rd harmonic
Phase noise
@ 400 kHz offset
@ 20 MHz offset
Output VSWR
With external 50 Ω match
Pushing
POUT
Output power temperature variation
V
7
–125
–164
MHz/V
–10
–10
dBc
dBc
–120
–162
dBc/Hz
dBc/Hz
2:1
4
±4
MHz/V
MHz
FOUT = 897.5 MHz with
external 50 Ω match
6
dBm
TA = –20 °C to +85 °C
±0.7
dB
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18
µs
MHz
VSWR 2:1
Output power
MHz
20
10
2
Pulling
MHz
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PRELIMINARY DATA SHEET • SKY74137
Table 8. SKY74137 Electrical Specifications – Transmitter (3 of 3)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
Units
1930
MHz
High Band Translation Loop VCO
TA = –20 °C to +85 °C
Frequency Range
fC
Digital frequency centering resolution
eDFC
1690
Digital frequency centering time
tDFC
From rising edge of TXENA
(13 MHz clock frequency)
12
Digital frequency centering voltage
VDFC
Control voltage at end of
DFC/start of analog lock
1.1
Analog frequency control range
fMAX – fMIN
0.5 < VCTL < 2.2
Absolute control sensitivity
KVCO
0.9 V < VCTL and
1.9 V > VCTL
6
Output harmonics
2nd harmonic
3rd harmonic
Phase noise
@ 400 kHz offset
@ 20 MHz offset
Output VSWR
With external 50 Ω match
Output power variation
V
10
–125
–158
MHz/V
–10
–10
dBc
dBc
–120
–155
dBc/Hz
dBc/Hz
2:1
4
±4
VSWR 2:1
POUT
µs
MHz
2
Output power
20
20
Pushing
Pulling
MHz
MHz/V
MHz
Fout = 1747.5 MHz with
external 50 Ω match
6
dBm
TA = –20 °C to +85 °C
±1
dB
Table 9. SKY74137 Electrical Specifications – Synthesizer (1 of 2)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
Units
Synthesizer
Prescaler operating input frequency
1000
Reference input frequency
13
Phase detector frequency
Reference oscillator level
1700
MHz
13
MHz
0.4
In-band phase noise
MHz
26
2.8
VPEAK
@ 10 kHz offset
–85
dBc/Hz
Charge pump leakage current
0.5 < VCP < 2.3
0.1
nA
Charge pump sink versus source mismatch
VCP = 1.4
5
%
Charge pump current versus voltage
0.5 < VCP < 2.3
10
%
Charge pump current versus temperature
VCP = 1.4,
TA = –20 °C to +85 °C
10
%
Frequency settling time
200
µs
3103
MHz
UHF VCO
Center frequency
fC
Digital frequency centering resolution
eDFC
Digital frequency centering time
tDFC
TA = –20 °C to +85 °C
2607
2
From rising edge of SXENA
or LATCHENABLE when
programming SX word (13
MHz clock frequency)
18
MHz
20
µs
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PRELIMINARY DATA SHEET • SKY74137
Table 9. SKY74137 Electrical Specifications – Synthesizer (2 of 2)
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
Minimum
Typical
Maximum
Units
UHF VCO (continued)
Digital frequency centering voltage
VDFC
Control voltage at end of
DFC/start of analog lock
Analog frequency control range
fMAX – fMIN
0.5 < VCTL < 2.2
Absolute control sensitivity
KVCO
Phase noise @ 1.5 GHz (3 GHz/2)
1.4
8
0.5 < VCTL < 2.2
10
@ 400 kHz offset
@ 3 MHz offset
–123
–140
V
20
MHz
–121
–137
dBc/Hz
dBc/Hz
MHz/V
Crystal Oscillator (26 MHz)
Operating frequency
26
Phase noise:
@ 100 Hz
@ 1 kHz
@ 10 kHz
Clock jitter
Spurious rejection
MHz
–98
–127
–145
dBc/Hz
dBc/Hz
dBc/Hz
16
ps
–15
dBc
Digital tuning (Note 1)
±20
±30
ppm
Analog tuning (Note 1)
±20
±25
ppm
Analog varactor voltage range
0.05
Analog varactor DC impedance
2.5
1
Supply voltage dependence
V
MΩ
0.5
ppm/V
Operating current (start) @ 26 MHz
2000
µA
Operating current (equilibrium) @ 26 MHz
2000
µA
Voltage swing @ crystal
1.5
Voltage swing @ buffer
1.0
Buffer output load
1.2
Vp-p
1.5
Vp-p
10
ms
10 pF ||
10 kΩ
Settles within ±1 ppm
Start-up time
Note 1: Using a crystal similar to NX4025DA.
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July 7, 2005 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200099A
PRELIMINARY DATA SHEET • SKY74137
Table 10. SKY74137 Electrical Specifications – Digital Interface
(TA = 25 °C, VCC = 3.6 V unless otherwise noted)
Parameter
Symbol
Test Condition
Min
Typical
Max
Units
Data to clock setup time
TCS
30
ns
Data to clock hold time
TCH
10
ns
Clock pulse width high
TCWH
30
ns
Clock pulse width low
TCWL
30
ns
Clock to load enable setup time
TES
30
ns
Load enable pulse width
TEW
50
ns
LE falling edge to clock rising edge
TEFC
30
ns
30
30
30
ns
ns
ns
RXENA setup time
TXENA setup time
SXENA setup time
High level input voltage
VIH
V
Low level input voltage
VIL
V
High level input current
IIH
RXENA, TXENA, DATAIN,
CLK, LATCHENABLE, PCO,
VCXO_EN ????, SXENA
–1
+1
µA
–1
+1
µA
10
pF
Low level input current
IIL
Digital input pin capacitance
CID
High level output voltage
VOH
PCO, IOH = –1.0 mA
Low level output voltage
VOL
PCO, IOLL = 1.0 mA
0.4
V
Digital output pin load capacitance
CLD
PCO
15
pF
V
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PRELIMINARY DATA SHEET • SKY74137
*** TBD ***
Figure 8. Typical GSM850 LNA Input Impedance
*** TBD ***
Figure 9. Typical EGSM900 LNA Input Impedance
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PRELIMINARY DATA SHEET • SKY74137
*** TBD ***
Figure 10. Typical DCS1800 LNA Input Impedance
*** TBD ***
Figure 11. Typical PCS1900 LNA Input Impedance
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Transmit Feedback
From PA Coupler
VCC
Receive Enable
PCS1900 Input
From T/R Switch
DCS1800 Input
From T/R Switch
EGSM900 Input
From T/R Switch
GSM850 Input
From T/R Switch
Transmit Enable
PAC Enable
PA Coupler Out
PA Low Band
Out to T/R Switch
PA High Band
Out to T/R Switch
C8
100 pF
C4
15 pF
C3
15 pF
C2
22 pF
C1
22 pF
16
15
14
13
12
11
IN
IN
IN
IN
2
5
2
5
2
5
2
5
COUP_OUT
GND
DCS/PCS OUT
GND
GSM OUT
GND
GND
GND
GND
10
RSVD2
SAW4
3
4
SAW3
3
4
SAW2
3
4
SAW1
3
4
EN
DCS/PCS IN
BS
RSVD1
VBATT
VAPC
GSM IN
×
×
L8
6.8 nH
L7
6.8 nH
L6
15 nH
L5
15 nH
1
2
3
4
5
6
7
VCC
C102
470 pF
C7
100 pF
11
10
9
8
7
6
5
4
3
2
1
40
XTAL
VCC2
12
1800LNA_P
1800LNA_N
900LNA_P
900LNA_N
850LNA_P
850LNA_N
VPC
TXENA
VCC1
Band Select
39
13
TXHB
RXENA
8
TXLB
VCC4
9
38
14
37
36
35
34
15
17
× ×
C9
120 nF
16
18
SKY74137
QP/TX_QP
TXRFin
+ C100
10 μF
VDIGENA
C101
10 nF
×
33
32
19
RX_IP
CLK
SXENA
CHIPENA
RX_QM
RX_QP
RX_IM
R2
10 kΩ
R1
39.2 kΩ, 1%
20
XTAL
VCC2
DATAIN
LATCHENABLE
VCC3
SKY77331
QM/TX_QM
VAPC
GND
GND
GND
GND
GND
GND
IM/TX_IM
COMPP
OUT
GND
IP/TX_IP
COMPN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
LOMON
24
LPFADJ
13MHZ_26MHZ
(or XBUF)
XTUNE
VBAT
21
22
23
24
25
26
27
28
29
30
31
×
×
×
×
4
1
XTAL1
C10
22 pF
3
2
C12
100 nF
C13
1 nF
+ C11
10 μF
Power Control
Buffer Out
Crystal Tune
S661
Synthesizer Supply
Chip Enable
Synthesizer Enable
Clock
Latch Enable
Data In
VCC
LDO Enable
Receive/Transmit I+
Receive/Transmit I–
Receive/Transmit Q–
Receive/Transmit Q+
PRELIMINARY DATA SHEET • SKY74137
Figure 12. Typical Helios II EDGE RF Subsystem Application Circuit (SKY74137 and SKY77331)
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PRELIMINARY DATA SHEET • SKY74137
TBD
Figure 13. Phone Board Layout Footprint For a 6 x 6 mm RFLGA Package
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PRELIMINARY DATA SHEET • SKY74137
6.04 ± 0.10
Solder Mask
Pin 1 Indicator
Pin 1 Indicator
0.500
Exposed Metal
R1.500
6.04 ± 0.10
0.30 ± 0.05
Detail A
0.38 ± 0.08
Top View
Bottom View
Solder Mask
Exposed Metal
0.38 ±0.05
Mold
Package Edge
1.00 ± 0.10
Substrate
0.040 REF
0.30 ±0.020
0.30 ± 0.05
0.00 ±0.050
Side View
Detail A
S311
All dimensions are in millimeters
Figure 14. SKY74137 40-Pin RFLGA Package Dimensions
2.00 ± 0.05
4.00
8.00
∅1.55 ± 0.05
0.30 ± 0.05
B
5.50 ± 0.05
A
1.75 ± 0.10
6.30
A
5o Max.
12.00 ± 0.30
Pin #1
Indicator
B
∅1.50 Min.
1.70
6.30
B
5o Max.
Notes:
1. Carrier tape: black conductive polystyrene
2. Cover tape material: transparent conductive PSA
3. Cover tape size: 9.3 mm width
4. All dimensions are in millimeters
A
C1222
Figure 15. SKY74137 40-Pin RFLGA Tape and Reel Dimensions
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July 7, 2005 • Skyworks Proprietary and Confidential information • Products and Product Information are Subject to Change Without Notice • 200099A
PRELIMINARY DATA SHEET • SKY74137
Ordering Information
Model Name
SKY74137 RF Transceiver
Manufacturing Part Number
Product Revision
SKY74137-xx
Copyright © 2004, 2005 Skyworks Solutions, Inc. All Rights Reserved.
Information in this document is provided in connection with Skyworks Solutions, Inc. (“Skyworks”) products. These materials are provided by Skyworks as a service to its customers and may be
used for informational purposes only by the customer. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its documentation, products,
specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts,
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The following are trademarks of Skyworks Solutions, Inc.: Skyworks®, the Skyworks logo, and Breakthrough Simplicity®. Product names or services listed in this publication are for identification
purposes only, and may be trademarks of Skyworks or other third parties. Third-party brands and names are the property of their respective owners. Additional information, posted at
www.skyworksinc.com, is incorporated by reference.
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