PRELIMINARYTECHNICAL DATA
=
EvaluationBoardDocumentation
ADE7752EnergymeteringIC
EVAL-ADE7752EB
PreliminaryTechnicalData
FEATURES
Evaluation Board can be used to implement a fully functional
Three-Phase Energy Meter (Watt-Hour Meter).
Easy connection of various external transducers via
screw terminals.
Easy modification of signal conditioning components
using PCB sockets.
LED indicators on logic outputs CF, NEGP and IRQ.
Optically isolated data output connection to PC parallel port.
Optically isolated frequency output (CF) to BNC.
External Reference option available for
on-chip reference evaluation.
GENERAL DESCRIPTION
The ADE7752 is high accuracy electrical active power
measurement IC for three-phase applications with a pulse
output. This output is intended to be used for calibration
purposes. The ADE7752 incorporates ADCs, reference
circuitry, and all the signal processing required to perform
active power and energy measurement.
The ADE7752 supplies average real power information on
the low frequency outputs F1 and F2. These logic outputs
may be used to directly drive an electromechanical counter.
The evaluation board provides screw connectors for easy
connection to an external counter. The NEGP logic output
goes high when negative active power is detected on any of the
three phases input. This causes an LED on the evaluation
board to switch on.
The ADE7752 evaluation board and this documentation,
together with the ADE7752 data sheet provides a complete
evaluation platform for the ADE7752.
The evaluation board has been designed so that the ADE7752
can be evaluated in the end application, i.e., Watt-Hour
Meter. Using the appropriate transducers on the current
channel (e.g., CT) the evaluation board can be connected to
a test bench or high voltage (240V rms) test circuit. On-board
resistor dividers networks provide the attenuation for the line
voltages. This application note also describes how the current
transducers should be connected for the best performance.
The evaluation board requires two external 5V power supplies (one is required for isolation purposes) and the appropriate current transducers.
FUNCTIONAL BLOCK DIAGRAM
AGND
VDD
DGND
V+
+5V
V-
IAP
IAN
IBP
IBN
Filter
Network
ADE7752
ICP
ICN
VN
VCP
VN
VBP
74HC08
Filter
Network
&
Attenuation
CF NEGP
Isolated Frequency
output
VN
VAP
Optional External
AD780
2.5V Reference
BNC
BNC
CF
CF
F1
F2
External
Clock in
PROTOTYPE
AREA
REV. PrB 06/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
PRELIMINARYTECHNICAL DATA
EVAL-ADE7752EB
ANALOG INPUTS (P4, P5, P6, P7, P8 AND P11)
Using a CT as the current transducer
Voltage and current signals are connected at the screw
terminals P4-P6 and P7-P8 and P11 respectively. All analog
input signals are filtered using the on-board anti-alias filters
before being presented to the analog inputs of the ADE7752.
The default component values which are shipped with the
evaluation board are the recommended values to be used with
the ADE7752. The user can easily change these components,
however this is not recommended unless the user is familiar
with sigma-delta converters and also the criteria used for
selecting the component values for the analog input filters See ADE7752 datasheet.
Figure 2 shows how a CT can be used as a current transducer
in one phase of a 3-phase 4-wire distribution system (Phase
A). In a three phase distribution system Phase A, Phase B and
Phase C are nominally 120° phase difference to each other.
Each phase usually requires a connection of this type for
current sensing.
I max = 40A
CT
JP5
R9
R10
P4 1
JP2
100Ω
JP1
C5
33nF
R7
P4 2
100Ω
SH2A
R6
JP3
1kΩ
JP6
R8
C8
33nF
1kΩ
IAP
Phase A
100Ω
1kΩ
JP25
JP6
33nF
355mV
rms
TP4
100Ω
SH2A
8Ω
JP1
IAN
1kΩ
33nF
Full Scale
differential input = 0.5V
Figure 2 — CT connection to Current Channel
The CT secondary current is converted to a voltage by using
a burden resistance across the secondary winding outputs.
Care should be taken when using a CT as the current
transducer. If the secondary is left open, i.e., no burden is
connected, a large voltage could be present at the secondary
outputs. This can cause an electrical shock hazard and
potentially damage electronic components.
Warning!
Using a CT without a burden resistor
can lead to electrical shock.
The anti-alias filters should be enabled by opening jumpers
JP5, JP6, JP11, JP12, JP17 and JP18—see Figure 2.
Most CTs will have an associated phase shift of between 0.1°
and 1° at 50Hz/60Hz. This phase shift or phase error can lead
to significant energy measurement errors, especially at low
power factors. However this phase error can be corrected by
adding some capacitors in parallel to C6 and C7.
ADE7752
JP4
TP2
JP2
P4, P5 and P6 are two-way connection blocks which allow
ADE7752's current inputs of phase A, B and C respectively
to be connected to current transducers. Figure 1 shows the
connector P4 and the filtering network which is provided on
the evaluation board.
The resistors SH1A, SH2A, SH1B, SH2B, SH1C and
SH2C are by default not populated. They are intended to be
used as burden resistors when CTs are used as the current
transducers—see using a CT as a the current transducer.
The RC networks R9/C5, R7/C8, R15/C9, R13/C12, R21/
C13, R19/C16 are used to provide phase compensation when
a Current Transformer is being used as the current transducer
with the ADE7752—see using a Current Transformer as the
current transducer. These RC networks are easily disabled by
placing JP4, JP1, JP10, JP7, JP16 & JP13 and removing C5,
C8, C9, C12, C13 and C16 (socketed).
The RC networks R10/C6, R8/C7, R16/C10, R14/C11,
R22/C14 and R20/C15 are the anti-alias filters which are
required by the on-chip ADCs. The default corner frequency
for these LPFs (Low Pass Filters) is selected as 4.8kHz (1kΩ
& 33nF). These filters can easily be adjusted by replacing the
components on the evaluation board. However before adjusting the component values the user should first review the
ADE7752 datasheet.
JP5
1:1800
Current sense inputs (P4, P5 and P6)
SH1A
R11
ADE7752
JP4
SH1A
8Ω
TP2
IAP
The maximum analog input range on the Current channel of
the ADE7752 is 0.5V peak.
C6
33nF
TP4
IAN
C7
33nF
Figure 1 — Current Channel on the ADE7752 evaluation
board
–2–
REV. PrB 06/02
PRELIMINARYTECHNICAL DATA
PRELIMINARY TECHNICAL DATA
EVAL-ADE7752EB
Voltage sense inputs
The trim pot allows the signals on the voltage channels to be
scaled so as to calibrate the frequency on CF to some given
constant, e.g., 1600 imp/kWhr. This is especially appropriate when calibrating the ADE7752. Some examples are given
later. Because of the relatively large signal on this channel
and the small dynamic range requirement, the voltage channels can be configured in a single-ended configuration.
Figure 3 shows a typical connection for the line voltage when
using the trim pot for calibration. In this case, R47, R44 and
R43 should be changed to 500Ω to assure the same cut-off
frequency of the anti-aliasing filter as for the current channel.
ADE7752
JP27
P7 2
JP32
R40
JP28
JP25
P7 1
Neutral
JP38
Phase A
The voltage inputs connections on the ADE7752 evaluation
board can be directly connected to the line voltage sources.
The line voltages are attenuated using a simple resistor
divider network before it is presented to the ADE7752. The
attenuation network on the voltage channels is designed such
that the corner frequency (3dB frequency) of the network
matches that of the RC (anti-aliasing) filters on the current
channels inputs. This is important, because if they do not
match there will be large errors at low power factors. Figure
3 below shows how the attenuation network may be used with
trim pot.
1kΩ
JP3
R48
R49
499kΩ
499kΩ
Attenuation
Network
TP13
VN
C1
33nF
JP36
C4
33nF
100 - 250 V rms
R47
500Ω
JP37 TP17
R3 500Ω
JP49
VAP
200 - 300 mV
rms
Figure 3 — Phase A Voltage Channel attenuation
network using Trim pot
The maximum signal level permissible at VAP, VBP and
VCP is 0.5V peak for the ADE7752. Although the
ADE7752 analog inputs can withstand ±6V without risk
of permanent damage, the signal range should not
exceed ±0.5V with respect to AGND for the ADE7752
for specified operation.
Note that the analog input VN is connected to AGND via
the anti-alias filter R40/C1 using JP28. Jumper JP27
should be left open.
ADE7752 EVALUATION BOARD SET UP
Configuration
The ADE7752 evaluation board can be configurated for the different mode of operation of the ADE7752. The connection
of the 2 positions jumpers (Px) are described as Right or Left. This is defined when one looks at the board with the label
EVAL-ADE7752 at the front bottom left.
TABLE I : Configuration of ADE7752
JUMPER
Left
Right
DESCRIPTION
P3
)*5 = High )*5 = Low Left position: Pin 17 is connected to a pull up resistor
Right position: Pin17 is connected to a pull down resistor
P12
S1=High
S1=Low
Left position: Pin 22 is connected to a pull up resistor
Right position: Pin22 is connected to a pull down resistor
P14
S0=Low
S0=High
Left position: Pin21 is connected to a pull down resistor
Right position: Pin 21 is connected to a pull up resistor
P16
SCF=Low
SCF=High
Left position: Pin18 is connected to a pull down resistor
Right position: Pin 18 is connected to a pull up resistor
Other jumpers are present on the ADE7752 evaluation board. Their actions are described in the following table.
REV. PrB 06/02
–3–
PRELIMINARYTECHNICAL DATA
EVAL-ADE7752EB
TABLE II : JUMPER SETTINGS
JUMPER
OPTION
DESCRIPTION
JP1-JP7-JP13
Closed
This will short out R7, R13 and R19 respectively. The effect is to disable the phase
compensation filter on the analog inputs IAN, IBN and ICN respectively. Default
Closed.
JP2-JP8-JP14
Closed
This will connect the analog input IAP, IBP and ICP respectively to ground. Default
Open.
JP3-JP9-JP15
Closed
This will connect the analog input IAN, IBN and ICN respectively to ground. Default
Open.
JP4-JP10-JP16
Closed
This will short out R9, R15 and R21 respectively. The effect is to disable the phase
compensation filter (for shunts) on the analog inputs IAN, IBN and ICN respectively.
Default Closed.
JP5-JP11-JP17
Closed
This will short out R10, R16 and R22 respectively. The effect is to disable the anti-alias
filter on the analog inputs IAP, IBP and ICP respectively. Default Open.
Open
Enable the anti-alias filter on IAP, IBP and ICP respectively.
Closed
This will short out R8, R14 and R20 respectively. The effect is to disable the anti-alias
filter on the analog inputs IAN, IBN and ICN respectively. Default Open.
Open
Enable the anti-alias filter on IAN, IBN and ICN respectively.
JP19
Closed
This will connect the Analog and Digital ground planes of the PCB. Default Closed.
JP20
Closed
This will connect an external reference 2.5V (AD780) to the ADE7752
Open
This will enable the ADE7752 on-chip reference.
JP21
Closed
This connects the VDD and +5V (buffers) supply for the evaluation board together.
Default Closed.
JP23-JP24-JP25
Closed
This will short the attenuation network on the voltage channels. Default Open
JP26
Closed
This will connect the optical isolator ground to the evaluation board ground (DGND). If
full isolation between the evaluation board and PC is required, this jumper should be left
open
JP27
Closed
This will short out R40. The effect is to disable the anti-alias filter on the analog input
VN. Default Open
JP28
Closed
This will connect the analog input VN to ground. Default Closed.
JP29-JP35-JP38
Closed
This will connect the analog inputs VAP, VBP and VCP to ground respectively. Default
Open
JP30-JP33-JP36
Closed
This will short out trim pots R1, R2 and R3 respectively. Default closed.
JP31-JP34-JP37
JP47-JP48-JP49
Closed
This will short out disconnect Analog input VAP, VBP and VCP respectively from the
ADE7752. Default Closed
JP32
Closed
This will short out disconnect Analog input VN from the ADE7752. Default Closed
JP43
A
This connects the buffered logic output CF to BNC J3 connector via an optical isolator.
B
This connects the buffered logic output CF to the LED CR2.
JP6-JP12-JP18
–4–
REV. PrB 06/02
PRELIMINARYTECHNICAL DATA
PRELIMINARY TECHNICAL DATA
EVAL-ADE7752EB
SETTING UP THE EVALUATION BOARD AS AN
ENERGY METER
Figure 5 shows a typical set up for the ADE7752 evaluation
board. In this example a kWh meter for a 4 wire, three phase
distribution system is shown. Current Transformers are used
to sense phases' current and are connected as shown in Figure
5. For a more detailed description on how to use a CT as a
current transducer see the Current Sense Inputs section of this
documentation. The line voltage is connected directly to the
evaluation board as shown. Note JP23, JP24 and JP25 should
be left open to ensure that the attenuation networks are not
bypassed. Also note the use of two power supplies.
The second power supply is used to power the optical
isolation. With JP26 left open, this will ensure that there is no
electrical connection between the high voltage test circuit and
the frequencies outputs. The power supplies should have
floating voltage outputs.
Setting up the evaluation board for the ADE7752
The configuration of the jumpers on the ADE7752 evaluation
board for operation with the ADE7752 are detailed in Figure
5. The selection of the outputs frequencies of CF, F1 and F2
is done by configuring SCF, S1 and S0 with jumpers P16,
P12 and P14 respectively. The mode of summation of the
three active energies (arithmetic sum or sum of the absolute
values) can also be selected on the evaluation board with
Jumper P3. Table III details the action of each jumper.
TABLE III : ADE7752 frequency setting
At maximum current (40 A) the power seen by the meter will
be 26.4 kW. This will produce a frequency of 0.733 Hz on
the logic outputs F1 and F2 when these outputs are calibrated
to 100 imp/kWhr (100 imp/hr = 0.0277 Hz, 0.02777 x 26.4
= 0.733 Hz). From Table III in the ADE7752 datasheet, the
closest frequency to 0.733 Hz in the half scale ac inputs
column is for F1-5 = 4.77 Hz. Therefore this frequency is
selected by setting S0 = 1 and S1 = 0. The choice of CF
frequencies in this mode (see Table IV of the ADE7752
datasheet are 16 times F1 or 160 times F1. For this example
16 times F1 is selected by setting SCF = 1.
Since the voltage on the current inputs (IAP/IAN, IBP/IBN
and ICP/ICN) are fixed, the only possible way of calibrating
(adjusting) the output frequency on F1 and F2 is by varying
the voltage on the voltage channels. This is carried out by
varying the attenuation of the line voltage using the trim pots.
First we can calculate the voltage required on the voltage
channels in order to calibrate the frequency on F1 and F2 to
100 imp/kWhr. The ADE7752 datasheet gives the equation
which relates the voltage on the current channels and voltage
channels to the output frequency on F1 and F2.
Freq =
6.82 × (VAN × I A + VBN × IB + VCN × IC ) × F 1 − 5
VREF 2
(1)
With a burden resistor of 7.6 Ω, the current channels' levels
for 5 A is 5 A / 1800 X 2 X 7.6 = 0.042 V rms. The output
frequency at 5A on F1 and F2 should be 0.02777 Hz (100
imp/kWhr) x 3.3 (3 x 220 V x 5 A) = 0.0917Hz.
Signal State
Jumper position
SCF
1
P16 - RIGHT
0
P16 - LEFT
1
P12 - LEFT
From Equation 1 the voltage on voltage channels should be
set to 139.8 mV rms. The attenuation network as shown in
Figure 3 is used to attenuate 220 V to 139.8 mV.
0
P12 - RIGHT
R41 = R42 = R45 = R46 = R48 = R49 =786 kΩ,
1
P14 - RIGHT
0
P14 - LEFT
R43= R44 = R47 = R10 = R8 = R14 = R16 = R20 = R22
= 500Ω
1
P3 - LEFT arithmetic sum
0
P3 - RIGHT Sum of absolute values
S1
S0
)*5
and trim pots = 500 Ω.
If CTs have a turn ration of 1:1800, the burden resistance of
the CTs can be placed on the evaluation board at SH1A,
SH2A, SH1B, SH2B, SH1C and SH2C.
The meter is intended to be used with a line - neutral voltage
of 220 V and a maximum current per phase of 40 A. The
frequency outputs F1 and F2 can be used to drive a mechanical counter. These outputs will be calibrated to provide
100imp/kWhr. The logic output CF can be used for calibration purposes and is shown connected to a frequency counter
via the opto-isolator in Figure 5.
REV. PrB 06/02
–5–
PRELIMINARYTECHNICAL DATA
EVAL-ADE7752EB
+
5.000 V
Phase A
P4
IAP
CT
SH2A
IAN
P5
V-
P2
P10
P1
JP1 = CLOSED
JP2 = OPEN
JP3 = OPEN
JP4 = CLOSED
JP5 = OPEN
JP6 = OPEN
SH1A
V+
DGND
JP19 = CLOSED
JP21 = CLOSED
Phase B
ADE7752 CONFIGURATION
P3 = RIGHT or LEFT
P12 = RIGHT or LEFT
P14 = RIGHT or LEFT
P16 = RIGHT or LEFT
RIGHT: ABS=0 Sum of absolute value
LEFT: ABS=1 Artithmetic sum
RIGHT: S1=0
LEFT: S1=1
RIGHT: S0=1
LEFT: S0=0
RIGHT: SCF=1
LEFT: SCF=0
IBP
JP7 = CLOSED
JP8 = OPEN
JP9 = OPEN
JP10 = CLOSED
JP11 = OPEN
JP12 = OPEN
SH1B
CT
SH2B
IBN
P6
ICP
JP13 = CLOSED
JP14 = OPEN
JP15 = OPEN
JP16 = CLOSED
JP17 = OPEN
JP18 = OPEN
SH1C
CT
SH2C
ICN
P8
JP27
JP32
R40
VN
JP28
C1
JP27 = OPEN
JP28 = CLOSED
JP32 = CLOSED
P9
JP23
JP30
JP29
VCP
JP23 = OPEN
JP29 = OPEN
JP30 = OPEN
JP31 = CLOSED
JP47 = OPEN
R43 = 500Ω
VBP
JP24 = OPEN
JP35 = OPEN
JP33 = OPEN
JP34 = CLOSED
JP48 = OPEN
R44 = 500Ω
C2
R42
JP31
R43 R1
R41
JP47
P11
JP24
C3
JP35
JP33
R46
JP34
R44 R2
R45
JP48
1.0666 Hz
JP25
P7
JP36
Load
C4
R49
JP37
R47 R3
R48
JP38
NEUTRAL
VDD
AGND
Phase C
Source
+
-
+5V
5.000 V
JP49
VAP
JP25 = OPEN
JP38 = OPEN
JP36 = OPEN
JP37 = CLOSED
JP49 = OPEN
R47 = 500Ω
NEUTRAL
Figure 5 - Typical set up for the ADE7752 evaluation board
–6–
REV. PrB 06/02
PRELIMINARYTECHNICAL DATA
PRELIMINARY TECHNICAL DATA
EVAL-ADE7752EB
EvaluationboardBOM
Designator
Value
Description
R1-R3
500Ω, 10%, 1/2W
Trim pot Resistor, 25 turns. BOURNS Part No. 3299W-501
R4, R24-25, R27-R31
10kΩ, 5%, ¼W
Resistor, no special requirements
R5, R7, R9, R13, R15,
100Ω, 5%, ¼W Resistor, no special requirements
R19, R21, R32
R6, R11-12, R17-18,
51Ω, 5%, ¼W
Not placed unless external clock is being used
1kΩ, 0.1%, ¼W
±15 ppm/°C Resistor, good tolerance, used as part of the analog filter
R23, R52
R8, R10, R14, R16, R20,
R22, R40, R43-44, R47
network.These resistors are not soldered, but are plugged into PCB
pin sockets for easy modification by the customer. Low drift
WELWYN RC55 Series, FARNELL part no. 339-179
R25
10Ω, 5%, ¼W
Resistor, no special requirements
R38-39
20Ω, 5%, ¼W
Resistor, no special requirements
R41-42, R45-46, R48-49
499kΩ, 0.1%, ¼W
Pin socketed, ±15 ppm/°C Low drift, WELWYN RC55 Series.
Farnell part no. 338-484
R26,R53-54, R57-59,R62 820Ω, 5%, ¼W
Resistor, no special requirements
R69
0Ω, 10%, ¼W
C1-16
33nF, 10%, 50 volt
X7R Capacitor, part of the filter network. These resistors are not
soldered, but are plugged into PCB mount sockets for easy modification by the customer. SR15 series AVX-KYOCERNA, FARNELL
part no. 108-948C5,
C17
220pF
PANASONIC ECQ-P1H221JZ
C18-19, C21-23
10uF, Tantalium
Power supply decoupling capacitors, 10%, 16V
C25, C39
22pF, ceramic
Gate oscillator load capacitors, FARNELL part no. 108-927
C24, C26,C30-31,C33-36 100nF, 25V
Power supply decoupling capacitors, 10%, X7R type, AVXKYOCERNA, FARNELL part no. 108-950
CR1-2
LED
Low current, Red, FARNELL part no. 637-087
J2-3
BNC connector
Straight square, 1.3mm holes, 10.2mm x 10.2mm
FARNELL part no. 149-453
JP1-21, JP23-38, JP47-49 2 Pin header
2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02
JP43A-B
2 Pin header x 2
2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02U1
P3, P12, P14, P16
3 Pin header x 2
2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02U1
A1
ADE7752
Supplied by Analog Devices Inc.
U1-2
74HC08
Quad CMOS AND gates
U3
HCPL2232
HP Optical Isolator
U7
AD780
2.5V reference, Supplied by Analog Devices Inc.
XTAL
10 MHz
Quartz Crystal, HC-49(US)
P1-2, P4-8, P10-11
screw terminal
15A, 2.5mm cable screw terminal sockets. WEILAND part no.
25.161.0253
P9
screw terminal
15A, 2.5mm cable screw terminal sockets. WEILAND 25.161.0353
REV. PrB 06/02
–7–
PRELIMINARYTECHNICAL DATA
Evaluationboardschematic(rev.A)
EVAL-ADE7752EB
–8–
REV. PrB 06/02
IAP
IAN
IBP
IBN
P7
P11
P8
P6
P5
P4
1
2
1
JP2
JP3
JP8
JP9
JP14
JP15
2
1
2
SH1A
R11
2
1
C3
C2
C4
R9
R17
R15
R3
R2
R1
R40
C16
R19
R21
2
2
2
1
2
2
2
2
2
2
JP36
R49
R48
R45
R46
R42
R41
JP27
R13
R7
JP16
C13
2
2
2
1
2
2
JP37
JP49
JP48
1
1
U7
ICN
ICP
1
C30
JP20
C22
TP14
TP12
2
C31
VAP
TP17
EVAL-ADE7752
VBP
TP16
JP34
1
JP33
VCP
TP15
VN
JP31
2
1
1
1
JP47
JP32
1
TP6
TP5
TP4
TP2
IBN
IBP
IAN
IAP
TP13
C15
1 JP18
1 JP17
1 JP12
1 JP11
1 JP6
2
2
2
R20
R14
R8
1 JP5
2
2
R22
C14
C11
R16
C10
C7
2
R10
2
1 JP30
2
1 JP13
1
C12
1 JP7
1 JP10
C9
C8
1 JP1
1 JP4
C21
A1
AGND
TP19
JP19
C24
2
AGND
01-
1
VDD
DGND
TP18
007906
-
P1
R25
R57
XTAL2
ABS_B
TP20
TP9
REVP
TP3
P16
2
1
TP1
0
1
F1
CF
R24
R26
R30
R4
1
P14
COMPONENT SIDE
08-007906 REV A
SCF
0
3
F2
TP7
TP8
S0
P3
REV
3
R6
2
1
2
1
SH2A
R23
SH3A
SH1B
R18
R58
R28
R29
2
1
1
C19
0
U1
R52
R5
U2
C33
DGND
1
P12
TP11
C26
J2
JP21
CFOUT
CR2
R54
EXTCLK
S1
0
1
C18
2
1
2
REVP
CR1
U3
JP26
R59
C6
R69
C25
ICP
ICN
VN
VCP
GND
VBP
VAP
GND
TP10
SH2B
R12
2
JP28
JP29
JP35
JP38
2
1
2
11
2
1 1
2
JP23
JP24
JP25
1
2 2
1
C1
R43
R44
R47
C39
1
2
R31
1
2
1
JP43B
R27
3
+5V
2
P10
R62
3
2
1
JP43A
–9–
R53
C35
C36
R32
C34
P2
R38
C23
R39
V+
V-
P9
F2
ANALOG DEVICES
WILMINGTON MFG
CFOUT
CFOUT
J3
F1
PRELIMINARY TECHNICAL DATA
3
REV. PrB 06/02
1
C5
PRELIMINARYTECHNICAL DATA
EVAL-ADE7752EB
PCB layout - Component Placement
SH3B
PRELIMINARYTECHNICAL DATA
EVAL-ADE7752EB
PCB layout - Component Side
–10–
REV. PrB 06/02
PRELIMINARYTECHNICAL DATA
PRELIMINARY TECHNICAL DATA
EVAL-ADE7752EB
PCB layout - Solder Side
EDIS TIUCRIC
609700-80
REV. PrB 06/02
A VER
–11–