CMOS TRANSMISSION GATE CIRCUITS
I. OBJECTIVES
a) To understand the operating principle of transmission gate.
b) To determine the on and off resistances of the gate.
c) To understand the mode of use of the transmission gates to obtain an amplifier with a digital adjustment
of the gain and a passive integrator with a digital controlled network of capacitors.
ΙΙ. COMPONENTS AND INSTRUMENTATION
In this experiment, you will use the 4066 integrated circuit from Fig.1. that includes 4 CMOS
transmission gates. Fig.1 presents the connection diagram of the 4066 integrated circuit. In Fig.2 the internal
structure and the symbol of a transmission gate are presented. The connection diagram for the 741 op-amp
can be found in Voltage Comparators with Operational Amplifier experiment.
VDDVCAVCD D D C C
14 13 12 11 10 9 8
1
2
3 4 5 6 7
VDD,VSS: positive and negative supply voltages.
A, A;
B, B; C, C; D, D: input/output and output/input for the
transmission gates: A, B, C, D.
VCA,VCB,VCC,VCD: the control voltages for the 4 transmission gates.
A A B B VCBVCCVSS
Fig.1. IC 4066- connection diagram
VDD
TP
INPUT
INPUT
OUTPUT
OUTPUT
Tn
CONTROL
vCo
-VSS
a)
CONTROL
INPUT
TG
OUTPUT
INPUT
OUTPUT b)
Fig.2.CMOS transmission gate.
a) Internal structure; b) Symbol
To supply the circuit you need a double dc regulated power supply. Because you apply and measure dc
and ac voltages you need a signal generator, a dual channel oscilloscope and a voltmeter.
III. PREPARATION
1.P. CMOS TRANSMISSION GATE (TG)
1.1.P. ON AND OFF STATES
The transmission gates from MMC 4066 integrated circuit (IC) are in on state for high control voltages
and in off state for low control voltages.
A.
• What does the output voltage vO(t) of the transmission gate look like for a sinusoidal input voltage, vI(t)
with 3V amplitude and 1KHz frequency, if the control voltage of the gate is vCo=5V? What if vCo=-5V? The
IC which contains the gate has the supply voltages: VDD=5V; VSS=-5V.
• Does the load resistance connected at the output affect the output voltage? If it is so, in what way and in
what state (on/off state)?
B.
• The IC is supplied with ±5V. What does vO(t) look like for vI(t) sinusoidal voltage with 7V amplitude,
vCo=5V?
1.2.P EQUIVALENT RESISTANCES OF THE TRANSMISSION GATE
Because the transmission gate is not ideal, between the input/output terminals there is an equivalent
resistance greater than 0 in the on state, ron, and less than infinite in the off state, roff .
• How do you determine ron and roff if you know for each state of the gate the input voltage, the output
voltage and the load resistance?
2.P. AMPLIFIER WITH DIGITAL ADJUSTMENT OF THE GAIN
• For the circuit in Fig.3, what is the value of the equivalent resistance, RAB, between the points A and B,
for the next combinations of the voltages that control the states of the two transmission gates?
I
II
III
IV
vCo1
vCo2
5V
-5V
5V
- 5V
5V
5V
-5V
-5V
• What is the value of the voltage gain, Av and how does vO(t) look like, for each case mentioned above, if
vI(t) is a sinusoidal voltage with the 200mV amplitude and 1KHz frequency? The relation between vO and vI
is:
v O = Av v I = −
R AB
vI
R1
3.P. PASSIVE INTEGRATOR WITH
NETWORK OF CAPACITANCES
A
DIGITAL
CONTROLLED
• For the circuit in Fig.4, what is the equivalent capacitance Ceq between the points A and B for the next
combinations of the voltages that control the transmission gates?
I
II
III
IV
vCo1
vCo2
5V
-5V
5V
-5V
5V
5V
-5V
-5V
• What is the time constant for each of these situations?
• What does vO(t) look like if vI(t) is a rectangular voltage between 0 and 5V with 100Hz frequency?
IV. EXPLORATIONS AND RESULTS
1. CMOS TRANSMISSION GATE
1.1. ON AND OFF STATES
Exploration
A.
• The assembly is supplied with a differential voltage (VDD=5V; VSS =-5V; ground=0V) from a dual dc
regulated voltage supply.
• Choose gate D from the four possible transmission gates denoted A, B, C and D (Fig.6).
• At the input of the gate In/Out, apply the voltage vO(t)=3sin(2π1000t)[V][Hz]
Attention: be sure that the operational output (OUT) is not connected to the load resistance.
• At the output of gate D, Out/In, connect the load resistance RL2=1KΩ (J11 closed).
• At the control input of the gate (VcoD) apply a high level voltage by connecting it to VDD (vCo=5V).
• Visualise simultaneously on the oscilloscope (Y–t mode) the input and output voltages (vi(t) and vo(t)).
• At the control input of the gate, apply a low level voltage by connecting VSS (vCo=-5V).
• Visualise simultaneously on the oscilloscope (Y–t mode) the input and the output voltages (vI(t) and
vO(t)) .Repeat the above steps for RL1=100Ω (J10 closed, J11 open).
Results
• Draw the waveforms for the input and the output voltages for vCo=5V, vCo=-5V and for RL2=1KΩ,
RL2=100Ω.
B.
• With the high level control voltage vCo=5V and the load resistance RL=1KΩ, visualise on the oscilloscope
vI(t) and vO(t).
• Increase the amplitude of vI until vO is distorted.
Results
• For what values of the amplitude of vI is the output voltage distorted?
1.2. EQUIVALENT RESISTANCES OF THE TRANSMISSION GATE
For the chosen transmission gate, apply at the input a sinusoidal signal with 1KHz frequency and the
amplitude smaller than 5V.
Exploration
A. ron
• vCo=5V; the load resistance RL1=100Ω
• With an ac voltmeter or with the oscilloscope measure the amplitudes of vI and vO.
Results
• The values of the amplitudes of vI and vO.
• Compute ron considering the voltage divider formed by ron and RL1.
B. roff
• vCo=-5V; the load resistance RL3=470KΩ (J12 closed, J10 open, J11 open).
• With the oscilloscope measure the amplitudes of vi and vo.
Results
• The values of the amplitudes of vI and vO and the value of the load resistance.
• Compute roff .
2.AMPLIFIER WITH DIGITAL ADJUSTMENT OF THE GAIN
Exploration
Build the circuit shown in Fig.3. The transmission gates used in this circuit are A and B. Disconnect all
the jumpers and connect : J14 with J15, J5 with J6, J8 with J9, the operational output (OUT) to the load
resistance, J11 closed, and J2 closed (to connect R2 with R3).
• The assembly is supplied with a differential voltage (VDD=5V; VSS=-5V; ground=0V)
• vI=100sin(2π1000t)[mV][Hz]
• Visualise the output from Vo.
• At the control terminals of the two transmission gates (VcoA and VcoB) apply the following combinations
of voltages :
I
II
III
vCoA
vCoB
5V
-5V
-5V
5V
5V
-5V
• Visualise on the oscilloscope vO(t) and vI(t) for each case mentioned above.
Results
• Draw the waveforms for vI(t) and vO(t), for the three cases mentioned above.
• What is the value of the voltage gain for each case; AV=vO/vI?
vCoB
vCoA
A
TGA
TGB
R2
R3
B
R1
3,9k
6k
+
33k
vI
vO
1k
RL
Fig.3. Amplifier with digital controlled gain
3. PASSIVE INTEGRATOR WITH A DIGITAL CONTROLLED NETWORK
OF CAPACITORS
Exploration.
• Build the circuit shown in Fig.4. Disconnect all the jumpers and make new connections: J13 with J14, J3
with J4, J7 with J8 and J1 closed (to short-circuit the R2).
• Visualise the output from VO1.
• The assembly is supplied with a differential voltage (VDD=5V;VSS=-5V;
ground= 0V)
• vI(t) is a rectangular signal between 0 and 5V, with 100Hz frequency, obtained from the signal generator.
• Visualise vO(t) and vI(t) for the follwing combinations of the two voltages which control the transmission
gates:
I
II
III
vCoA
vCoB
5V
5V
-5V
5V
-5V
-5V
Results
• Draw the waveforms for vO(t) and vI(t) for the three cases mentioned above.
R
3,9K
A
vCoA
vCoB
TGA
TGB
vI
C1
C2
68nF
2,2nF
B
Fig. 4. Integrator with digitally controlled capacitors network
vO
REFERENCES
1. Oltean, G., Electronic Devices, Editura U.T. Pres, Cluj-Napoca, ISBN 973-662-220-7, 2006
2. Sedra, A. S., Smith, K. C., Microelectronic Circuits, Fifth Edition, Oxford University Press, ISBN: 0-19514252-7, 2004
3. http://www.bel.utcluj.ro/dce/didactic/ed/ed.htm
Fig. 5. Experimental assembly