®
OPA
OPA
2130
130
OPA
130
OPA130
OPA2130
OPA4130
OPA
4130
OPA
2130
OPA
413
0
Low Power, Precision
FET-INPUT OPERATIONAL AMPLIFIERS
FEATURES
● LOW QUIESCENT CURRENT: 530µA/amp
OPA130
● LOW OFFSET VOLTAGE: 1mV max
● HIGH OPEN-LOOP GAIN: 120dB min
● HIGH CMRR: 90dB min
Offset Trim
1
8
NC
–In
2
7
V+
+In
3
6
Output
V–
4
5
Offset Trim
8
V+
7
Out B
6
–In B
5
+In B
● FET INPUT: IB = 20pA max
● EXCELLENT BANDWIDTH: 1MHz
● WIDE SUPPLY RANGE: ±2.25 to ±18V
8-Pin DIP, SO-8
● SINGLE, DUAL, AND QUAD VERSIONS
DESCRIPTION
OPA2130
The OPA130 series of FET-input op amps combine
precision dc performance with low quiescent current.
Single, dual, and quad versions have identical specifications for maximum design flexibility. They are ideal
for general-purpose, portable, and battery operated
applications, especially with high source impedance.
OPA130 op amps are easy to use and free from phase
inversion and overload problems often found in
common FET-input op amps. Input cascode circuitry
provides excellent common-mode rejection and
maintains low input bias current over its wide input
voltage range. OPA130 series op amps are stable in
unity gain and provide excellent dynamic behavior
over a wide range of load conditions, including high
load capacitance. Dual and quad designs feature
completely independent circuitry for lowest crosstalk
and freedom from interaction, even when overdriven
or overloaded.
Single and dual versions are available in 8-pin DIP
and SO-8 surface-mount packages. Quad is
available in 14-pin DIP and SO-14 surface-mount
packages. All are specified for –40°C to +85°C
operation.
Out A
–In A
1
A
2
+In A
3
V–
4
B
8-Pin DIP, SO-8
OPA4130
Out A
1
–In A
2
A
14
Out D
13
–In D
D
+In A
3
12
+In D
V+
4
11
V–
+In B
5
10
+In C
B
C
–In B
6
9
–In C
Out B
7
8
Out C
14-Pin DIP
SO-14
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1995 Burr-Brown Corporation
SBOS053
PDS-1298B
Printed in U.S.A. May, 1998
SPECIFICATIONS
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
OPA130PA, UA
OPA2130PA, UA
OPA4130PA, UA
PARAMETER
CONDITION
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature(1)
vs Power Supply
Channel Separation (dual and quad)
MIN
Operating Temperature Range
VS = ±2.25V to ±18V
INPUT BIAS CURRENT(2)
Input Bias Current
vs Temperature
Input Offset Current
VCM = 0V
VCM = 0V
NOISE
Input Voltage Noise
Noise Density, f = 10Hz
f = 100Hz
f = 1kHz
f = 10kHz
Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range, Positive
Negative
Common-Mode Rejection
VCM = –13V to +13V
INPUT IMPEDANCE
Differential
Common-Mode
VCM = –13V to +13V
OPEN-LOOP GAIN
Open-loop Voltage Gain
FREQUENCY RESPONSE
Gain-Bandwidth Product
Slew Rate
Settling Time: 0.1%
0.01%
Overload Recovery Time
Total Harmonic Distortion + Noise
VO = –13.8V to +13V
RL = 2kΩ, VO = –13V to +12V
(V+)–2
(V–)+2
90
120
120
G = 1, 10V Step, CL = 100pF
G = 1, 10V Step, CL = 100pF
G = 1, VIN = ±15V
1kHz, G = 1, VO = 3.5Vrms
OUTPUT
Voltage Output, Positive
Negative
Positive
Negative
Short-Circuit Current
Capacitive Load Drive (Stable Operation)
POWER SUPPLY
Specified Operating Voltage
Operating Voltage Range
Quiescent Current (per amplifier)
RL = 2kΩ
RL = 2kΩ
(V+)–2
(V–)+1.2
(V+)–3
(V–)+2
±2.25
IO = 0
TEMPERATURE RANGE
Operating Range
Storage
Thermal Resistance, θJA
8-Pin DIP
SO-8 Surface-Mount
14-Pin DIP
SO-14 Surface-Mount
TYP
MAX
UNITS
±0.2
±2
2
0.3
±1
±10
20
mV
µV/°C
µV/V
µV/V
+5
See Typical Curve
±2
±10
pA
±20
pA
30
18
16
16
4
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fA/√Hz
(V+)–1.5
(V–)+1.2
105
V
V
dB
1013 || 1
1013 || 3
Ω || pF
Ω || pF
135
135
dB
dB
1
2
5.5
7
2
0.0003
MHz
V/µs
µs
µs
µs
%
(V+)–1.5
(V–)+1
(V+)–2.5
(V–)+1.5
±18
10
V
V
V
V
mA
nF
±15
±530
–40
–40
100
150
80
110
±18
±650
V
V
µA
+85
+125
°C
°C
°C/W
°C/W
°C/W
°C/W
NOTES: (1) Guaranteed by wafer test. (2) High-speed test at TJ = 25°C.
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
®
OPA130, 2130, 4130
2
ELECTROSTATIC
DISCHARGE SENSITIVITY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V+ to V– .................................................................... 36V
Input Voltage .................................................... (V–) –0.7V to (V+) +0.7V
Output Short-Circuit(1) .............................................................. Continuous
Operating Temperature ................................................. –40°C to +125°C
Storage Temperature ..................................................... –40°C to +125°C
Junction Temperature ...................................................................... 150°C
Lead Temperature (soldering, 10s) ................................................. 300°C
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
NOTE: (1) Short-circuit to ground, one amplifier per package.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE
PACKAGE
DRAWING
NUMBER(1)
Single
OPA130PA
OPA130UA
8-Pin Plastic DIP
SO-8 Surface-Mount
006
182
–40°C to +85°C
–40°C to +85°C
Dual
OPA2130PA
OPA2130UA
8-Pin Plastic DIP
SO-8 Surface-Mount
006
182
–40°C to +85°C
–40°C to +85°C
Quad
OPA4130PA
OPA4130UA
14-Pin Plastic DIP
SO-14 Surface-Mount
010
235
–40°C to +85°C
–40°C to +85°C
TEMPERATURE
RANGE
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
®
3
OPA130, 2130, 4130
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
POWER SUPPLY AND COMMON-MODE REJECTION
vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
120
110
0
120
φ
–90
60
40
–135
PSR, CMR (dB)
80
20
G
0
10
100
1k
10k
100k
1M
80
70
60
CMR
+PSR
50
40
30
20
10
0
–180
–20
1
–PSR
100
90
–45
CL = 100pF
Phase Shift (°)
Voltage Gain (dB)
100
10
10M
100
1k
Frequency (Hz)
10
10
Channel Separation (dB)
Voltage Noise
160
Current Noise (fA/√Hz)
Voltage Noise (nV/√Hz)
100
100
140
120
100
Current Noise
1
1
1k
10k
100k
Dual and quad devices.
G = 1, all channels.
Quad measured channel
A to D or B to C—other
combinations yield improved
rejection.
RL = 10kΩ
80
1M
10
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
INPUT BIAS CURRENT
vs INPUT COMMON-MODE VOLTAGE
10
10k
1k
VCM = 0V
100
Input Bias Current (pA)
Input Bias and Input Offset Current (pA)
100
1M
CHANNEL SEPARATION vs FREQUENCY
1k
1k
10
100k
Frequency (Hz)
INPUT VOLTAGE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
1
10k
IB
IOS
10
1
5
0.1
0
0.01
–75
–50
–25
0
25
50
75
100
–15
125
–5
0
5
Common-Mode Voltage (V)
Ambient Temperature (°C)
®
OPA130, 2130, 4130
–10
4
10
15
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
Quiescent Current Per Amp (mA)
140
AOL, CMR, PSR (dB)
130
Open-Loop
Gain
120
PSR
110
CMR
0.65
40
0.60
35
IQ
0.55
30
–
ISC
0.50
25
0.45
20
+
ISC
0.40
15
0.35
100
–75
–50
–25
0
25
50
75
100
10
–75
125
–50
–25
0
25
50
75
Ambient Temperature (°C)
Temperature (°C)
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
15
Short-Circuit Current (mA)
QUIESCENT CURRENT AND SHORT-CIRCUIT CURRENT
vs TEMPERATURE
AOL, CMR, PSR vs TEMPERATURE
100
125
20
Percent of Amplifiers (%)
Percent of Amplifiers (%)
18
10
5
16
14
12
10
8
6
4
2
0
Offset Voltage (µV)
Offset Voltage Drift (µV/°C)
TOTAL HARMONIC DISTORTION + NOISE
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE
vs FREQUENCY
0.1
8.00
7.50
7.00
6.50
6.00
5.50
5.00
4.50
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
700
600
500
400
300
200
0
100
–100
–200
–300
–400
–500
–600
–700
0
30
Output Voltage (Vp-p)
THD + Noise (%)
25
0.01
G = +10
0.001
RL = 10kΩ
RL = 2kΩ
G = +1
Maximum output voltage
without slew-rate induced
distortion
15
10
VS = ±5V
5
0.0001
100
VS = ±15V
20
VS = ±2.25V
0
1k
10k
100k
10k
Frequency (Hz)
100k
1M
Frequency (Hz)
®
5
OPA130, 2130, 4130
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, and RL = 10kΩ, unless otherwise noted.
SMALL-SIGNAL STEP RESPONSE
G = 1, CL = 1000pF
50mV/div
50mV/div
SMALL-SIGNAL STEP RESPONSE
G =1, CL = 100pF
5µs/div
500ns/div
LARGE-SIGNAL STEP RESPONSE
G = 1, CL = 100pF
SETTLING TIME vs GAIN
100
5V/div
Settling Time (µs)
0.01%
10
0.1%
1
5µs/div
±1
±10
±100
Gain (V/V)
SMALL-SIGNAL OVERSHOOT
vs LOAD CAPACITANCE
OUTPUT VOLTAGE SWING vs OUTPUT CURRENT
15
80
G = +1
70
13
–55°C
12
11
60
Overshoot (%)
Output Voltage Swing (V)
14
+125°C
+25°C
10
–10
–11
+125°C
+85°C
–12
–13
±5
±10
±15
G = –1
0
10pF
±20
Output Current (mA)
G = ±5
100pF
1nF
Load Capacitance (F)
®
OPA130, 2130, 4130
30
10
–15
0
40
20
+25°C
–55°C
–14
50
6
10nF
100nF
APPLICATIONS INFORMATION
V+
Trim Range: ±5mV typ
OPA130 series op amps are unity-gain stable and suitable
for a wide range of general-purpose applications. Power
supply pins should be bypassed with 10nF ceramic capacitors or larger.
10nF
100kΩ
7
1
2
OPA130 op amps are free from unexpected output phasereversal common with FET op amps. Many FET-input op
amps exhibit phase-reversal of the output when the input
common-mode voltage range is exceeded. This can occur in
voltage-follower circuits, causing serious problems in
control loop applications. OPA130 series op amps are free
from this undesirable behavior. All circuitry is completely
independent in dual and quad versions, assuring normal
behavior when one amplifier in a package is overdriven or
short-circuited.
5
3
10nF
OPA130
4
6
OPA130 single op amp only.
Use offset adjust pins only to null
offset voltage of op amp—see text.
V–
FIGURE 1. OPA130 Offset Voltage Trim Circuit.
INPUT BIAS CURRENT
OPERATING VOLTAGE
The input bias current is approximately 5pA at room temperature and increases with temperature as shown in the
typical performance curve “Input Bias Current vs Temperature.”
Input stage cascode circuitry assures that the input bias
current remains virtually unchanged throughout the full
input common-mode range of the OPA130. See the typical
performance curve “Input Bias Current vs Common-Mode
Voltage.”
OPA130 series op amps operate with power supplies from
±2.25V to ±18V with excellent performance. Although
specifications are production tested with ±15V supplies,
most behavior remains unchanged throughout the full
operating voltage range. Parameters which vary significantly with operating voltage are shown in the typical
performance curves.
OFFSET VOLTAGE TRIM
Offset voltage of OPA130 series amplifiers is laser trimmed
and usually requires no user adjustment. The OPA130
(single op amp version) provides offset voltage trim connections on pins 1 and 5. Offset voltage can be adjusted by
connecting a potentiometer as shown in Figure 1. This
adjustment should be used only to null the offset of the op
amp, not to adjust system offset or offset produced by the
signal source. Nulling offset that is not produced by the
amplifier will change the offset voltage drift behavior of
the op amp.
®
7
OPA130, 2130, 4130
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright  2000, Texas Instruments Incorporated
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