NEC's LOW POWER
UPB1008K
GPS RF RECEIVER
FEATURES
• LOW POWER CONSUMPTION: 52 mW
• DUAL-CONVERSION IQ DOWN CONVERTER1:
Reference frequency: REFin = 27 MHz
• PSEUDO-BASEBAND WITH 2-BIT DIGITIZED OUTPUT
• ON-CHIP LNA, ON-CHIP FREQUENCY SYNTHESIZER,
IF AGC AMPLIFIER:
with 45 dB typical range of adjustable gain
• SMALL 36 PIN QFN PACKAGE:
Flat lead style for better RF performance
D
BLOCK DIAGRAM
AGC
UE
PIN 1 –
OSC
Note:
1. Based on eRide's proprietary GPS DSP architecture
UPB1008K
Dividers
LNA
IQ DEMO
1stMIX
ADC
PD
1/2
IN
ADC
DESCRIPTION
APPLICATIONS
NEC's UPB1008K is a Silicon RFIC especially designed for
handheld low power/low cost GPS receivers. The IC combines an LNA, followed by a double-conversion RF/IF
downconverter block and a PLL frequency synthesizer on one
chip. The second IF Freqency is a pseudo- baseband signal
into a on-chip 2-bit A/D converters.The device can operate on
a supply voltage as low as 2.7 V, and is a housed in a small 36
pin QFN (Quad, Flat, No-lead) package, resulting in a very low
power consumption and reduced board space.
NEC's stringent quality assurance and test procedures ensure the highest reliability and performance.
NT
• E911 ENABLED MOBILE PHONE
• IN-VEHICLE NAVIGATION SYSTEMS
• LOW POWER HANDHELD GPS RECEIVER
• PC/PDA+GPS INTEGRATION
SC
O
• ASSET TRACKING
RF APPLICATION DIAGRAM
IF filter
AGC
ISign
LNA
2-bit
ADC
IMag
2-bit
ADC
QSign
QMag
RF SAW
TANK
/2
DI
Loop
Filter
/4
/6
/7
BASEBAND I C
1st Mixer
Nyquist Filters
/2
I/Q
Balance
PLL Frequency
Counters
/8
/2
REFin
27 MHz
Regulator Circuitry
Reference
Clock
California Eastern Laboratories
UPB1008K
ADVANCED GPS COMPLETE SOLUTION
AUTOMOTIVE
e YELLOW PAGES
ASSET
TRACKING
PERSONAL GPS
NETWORK
TRACKING
D
e 911
eRide NAVIGATION
SOFTWARE & DRIVERS
GAIN
CONTROL
TIME
FREQ
UART
UE
TEMP
eRide
SMART SERVER
ADC
OPUS
ACQUISITION
STATE
MACHINE
PLL
TRACKING
ADC
UPB1008K
eRide WORLDWIDE
REFERENCE STATION
NETWORK
IN
Opus 1
ADVANCED GPS COMPLETE SOLUTION
SC
O
NT
"NEC Corporation and eRide, Inc. have teamed to provide an advanced positioning solution delivering high GPS performance,
accuracy, integration and architecture flexibility. The chip set combines CEL's UPB1008K receiver IC with eRide's Opus One SOC
(System-on-a-Chip) Baseband ASIC and is suitable for standard GPS products as well as Cellular Handset applications. Also provided
are scalable client navigation software and drivers, plus location-aiding data from eRide's Smart Server. Together, they offer a
complete hardware/infrastructure solution.
The chip set's design allows it to operate independently of wireless interface standards - and independently of the host product's CPU
and Operating System. This unique approach to system integration makes it easy to deploy the chip set into an wireless application,
in any wireless network. A "Universal Hardware" solution, the design promises lower manufacturing costs and, ultimately lower cost
to the consumer.
The chip set's advanced positioning architecture offers unmatched sensitivity providing fast, accurate positioning architecture offers
unmatched sensitivity providing fast and accurate position fixes, even when indoors or in deep in urban canyons."
HIGH PERFORMANCE GPS OMNI MODE
LI, C/A code receiver
Performance
Indoor
Outdoor
Time to First Fix w/ aiding
Time to First Fix w/o aiding
Accuracy
Sensitivity
5-7sec
10-20sec
10-25m cep
-155dBm
in 1sec dwells
1-3sec
3-5sec
2-5m cep
-142dBm
in two 10msec dwells
DI
Superior performance in high reflection indoor environments and in urban canyon types of outdoor environments
POWER DISSIPATION
First Fix
400 mW
Tracking
200-300 mW
Stand By
30 mW
UPB1008K
ELECTRICAL CHARACTERISTICS (TA = 25°C, VCC = 3.0 V, unless otherwise specified)
VCC
ICC_PD
PARAMETERS AND CONDITIONS
Total Circuit Current, No Signals
UNITS
mA
MIN
14
TYP
18
MAX
23.5
Supply Voltage
V
2.7
3.0
3.3
Power down current, PIN 13 = VIL
µA
–
1
10
RF Block Circuit Current (pin 3), No signal
µA
0.4
VCO Block Circuit Current (pin 7), No signal
mA
4.1
ICC pll
PLL Block Circuit Current (pin 9), No signal
mA
2.7
ICC bb
Baseband Block Circuit Current (pin 23), No signal,
open load
mA
2.5
ICC if
ICC lna
IF Block Circuit Current (pin 28) , No signal
mA
Pre-Amplifier Open Connector Current (pin 36),
No signal
mA
0.5
0.7
5.6
7.2
3.6
4.7
3.4
4.3
UE
ICC rf
ICC lo
D
SYMBOLS
ICC
2.7
3.7
4.7
1.0
1.4
1.8
LNA/RF DOWNCONVERTER
(fRFin = 1575.42 MHz, f1stLOin = 1400 MHz, PLO = -10 dBm, f1stIF = 175 MHz, Pin 13: VIL = 3 V, ZL differential = 32Ω & ZS = Γopt)
ALO-RF
UNITS
MIN
TYP
MAX
dB
18
23
28
–
–
–
–
IN
NFLNA_MIX
P1dBLNA_MIX
ZLNAin
ZMIXout
ALO-IF
PARAMETERS AND CONDITIONS
Power conversion gain from 2nd LNA/mixer to 1st IF,
PRFin = -50 dBm
Noise Figure of 2nd LNA/mixer(SSB), Input matched
1 dB Compression refer to source, Input matched
RF Input Impedance of LNA
IF Output Impedance of Mixer
Local Signal Leak to IF, f1stLOin=1400 MHz,
PLO = 0 dBm
Local Signal Leak to RF, f1stLOin=1400 MHz,
PLO = 0 dBm
dB
dBm
Ohm
Ohm
dBm
–
5
-38
31
32
-35
dBm
–
-50
–
NT
SYMBOLS
CGLNA_MIX
PLL
–
–
–
SYMBOLS
PARAMETERS AND CONDITIONS
UNITS
MIN
TYP
MAX
ICPOH
ICPOL
fPD
PLL Charge Pump High Side Current @ VCPout = VCC/2
PLL Charge Pump Low Side Current @ VCPout = VCC/2
Phase Comparison Frequency
µA
µA
MHz
–
–
–
200
-200
13.5
–
–
–
UNITS
MIN
TYP
MAX
mVpp
MHz
V
dBc/Hz
50
–
0.8
57
200
27
1.5
62
–
–
2.2
–
CRYSTAL OSCILLATOR/REVERENCE AMPLIFIER BLOCK
PARAMETERS AND CONDITIONS
SC
O
SYMBOLS
VREFin
fREF
VT
C/N
Reference input minimum level
Input Frequency of Reference Input
VCO Control Voltage, PLL Locked
VCO C/N, 1kHz, Loop band width = 5 kHz
AGC AMPLIFIER, I-Q DEMODULATOR, and ADC BLOCK(f1stIFin = 175 MHz, Zin = 600Ω)
SYMBOLS
CGAGC/MIX
AAGC/MIX
1 dB compression input to AGC amplifier,
set voltage gain = 30 dB
DI
P1dBAGC
PARAMETERS AND CONDITIONS
Maximum voltage conversion gain of AGC amplifier/
I-Q mixer, Pin = -60 dBm, VAGC = 0.5 V, Unmatched
Minimum voltage conversion gain of AGC amplifier/
I-Q mixer, Pin = -60 dBm, VAGC = 2.0 V, Unmatched
AGC control range, VAGC = 0.5 V to 2 V
VAGC
AGC control voltage
BW
3dB Mixer Bandwidth
IQ BalanceControl Voltage, Gain(Ich) = Gain (Qch)
VIQ-C
AIQ-C
IQ Balance Control Gain Range, VIQ-C = 0 to 3 V
Duty
Ich Mag Bit Output Pulse Duty, P1stIFin = -84 dBm
Ich
VAGC = 0.5 V, VIQ-C = 0 V
Duty
Qch Mag Bit Output Pulse Duty, PIF2in = -88 dBm
Qch
VAGC = 0.5 V, VIQ-C = 0 V
BASEBAND AMPLIFIER BLOCK (ZS = 2kΩ & ZL = 2 kΩ)
SYMBOLS
PARAMETERS AND CONDITIONS
VBBOH
Baseband output logic high, CL = 10 pF
VBBOL
Baseband output logic low, CL = 10 pF
UNITS
dB
MIN
–
TYP
30
MAX
–
dB
–
-15
–
dB
25
45
–
dBm
–
-45
–
V
0.5
–
2.0
MHz
V
dB
%
–
–
4.0
50
10
2.1
6.5
–
–
2.8
–
–
%
50
–
–
UNITS
V
V
MIN
2.0
0
TYP
–
–
MAX
–
0.5
UPB1008K
RECOMMENDED
OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS1,2 (TA = 25°C)
PARAMETERS
Supply Voltage4
Total Power Dissipation3
Operating Temperature
Storage Temperature
Total Circuit Current4
UNITS
VCC
mW
°C
°C
SYMBOLS
VCC
TOP
fRFin
fREFin
f1stLO
RATINGS
3.6
361
-40 to +85
-55 to +150
Notes:
1. Operation in excess of any one of these parameters may result
in permanent damage.
2. More than two items must not be reached simultaneously.
3. TA = +85°C, mounted on a 50 x 50 x 1.6 mm double-sided
copper clad epoxy glass PWB.
4. TA = 25°C
PARAMETERS
Supply Voltage
Operating Temperature
RF Input Frequency
Reference Frequency
1st LO Oscillating
Frequency
1st IF Input Frequency
2nd LO Input Frequency
Power Down Control
Voltage "High"
Power Down Control
Voltage "Low"
UNITS MIN
V
2.7
°C
-40
MHz
MHz
TYP
3.0
+25
1575
27
MAX
3.3
+85
D
SYMBOLS
VCC
PD
TOP
TSTG
ICC_total
f1stIFin
1400
175
175
UE
f2ndLOin
VIH
MHz
MHz
MHz
V
2
VCC
V
0
0.5
IN
VIL
APPLICATION CIRCUIT
1:16
0.1uF
SAW
OUT
NT
15pF
IN
INb
VCC
OUTb
15pF
36
VCC
VCC
SC
O
43K
.1pF
GND1na
300
34
33
31
30
100nF
29
28
AGC
1
27
21FoutI
3.3nH
6.8nH
SAW
MATCHING
FILTER
NETWORK
LNAin
150pF
1stMIX
2
VCC
12pF
VCCrf
NE662MO4
LNA
3
26
25
21Foutb
DCoffsetI
100nF
100nF
GNDIo
1stLO-OSC1
4
24
DCoffsetb
VCC
1/2
5
23
VCCbb
12pF
1stLO-OSC2
12pF
22
OSC
VCCIo
100nF
Vth
1/4
6
VCC
1/2
I_mag
2Bit ADC
21
7
I_sign
I_mag
1/6.375
100nH
PDout
8
20
PD
3.3nH
Vccdig
19
Q_mag
uPB1008K
1.2K
VCC
Vagc
10
11
12
13
14
15
16
17
18
PD
100nF
150pF
1OOnF
GNDbb
DCoffsetQ
21FoutQb
21FoutQ
PD
Ic_cntl
100nF
GNDdig
0.01uF
Refin
22pF
Q_mag
CP
15K
15K
I_sign
Q_sign
1/2
9
D0
Q_sign
2Bit ADC
DCoffsetQb
3.3nH
DI
RF_in
VAGC
IFin2
IFin1
GNDanalog
32
VCC
VCCanalog
IQ_DEMO
12pF
35
Mixout2
Vref
LNAbias
1.2nH
Mixout1
200
0.1uF
ic_cntl
REFin
UPB1008K
PIN FUNCTIONS
Pin No.
Symbol
1
GNDlna
Function and Application
Internal Equivalent Circuit
3
Ground pin of LNA
36
2
Input pin of low noise amplifier. It is a
single-ended open collector design.
Capacitive coupling is required; external
matching will improve gain or NF.
VCC
r=6.5k
D
LNAin
Bias
2
Regulator
GND
VCCrf
Supply voltage pin of LNA, RF mixer and VCO
voltage regulator.
4
GNDlo
Ground pin of 1st LO Oscillator circuit and RF
Mixer.
5
6
1stLO-OSC1
1stLO-OSC2
UE
1
3
7
r = 410
3
GNDdig
c=1.8p
Bias
4
9
ESD
Source
PFD
Source Control
FROM PFD
8
Sink Control
ESD
Sink
Supply voltage pin of digital portion of the chip.
11
Input pin of reference frequency buffer. This pin
should be equipped with external 27 MHz
oscillator (e.g. TCXO).
9
r=20k
r=20k
idc=9.7u
ESD
Ground pin of digital portion of the chip.
DI
11
idc=941u
GND
10
ESD
r=500
r=500
r=50k
REFin
r=4.4k
Regulator
This is a current mode charge pump output.
For connection to a passive RC loop filter for driving
external varactor diode of 1stLO-OSC.
SC
O
10
VCCdig
Supply voltage pin of oscillator circuit for
1st LO Oscillator and RF mixer
PFD
9
PDout
5
r=4.4k
VCC
IN
8
VCClo
r=300
6
NT
7
c=1.8p
r=300
Pin 5 & 6 are base pins of the differential
amplifier for 1st LO oscillator. These pins
require an LC (varacator) tank circuit to
oscillate at around 1400 MHz.
r=30k
idc=22u
11
c=5.4p
UPB1008K
PIN FUNCTIONS
Symbol
12
I/Q Balance
Control
Function and Application
Internal Equivalent Circuit
28
The voltage on this pin controls the Q channel
IF Amplifier Gain. Gain control of ±2 dB can be
achieved for 0~3 V.
Leave open-circuited if not used.
idc=23.5u
idc=23.5u
D
Pin No.
Iref
CCCS
r=200k
Qgain
–2dB
UE
+2dB
r=12k
12
r=7.1k
r=7.1k
r=7.1k
0V
3V
1.5 V
V
r=7.1k
32
PD1
IN
13
VCC
Standby mode control.
Low=whole chip OFF & High=Whole chip ON.
ESD
ESD
r=2k
ESD
r=2k
15,(26)
To channel amp
r=2k
14,(27)
idc=86u
idc=86u
ESD
ESD
32
DC offset compensation pin for C arm. A low pass
capacitor shunt to Pin 17 is required.
DC offset compensation pin for Q-bar arm.
A low pass capacitor shunt to Pin 16 is required.
28
ESD
r=4k
ESD
17,(24)
r=20k
c=9p
16,(25)
idc=84u
idc=84u
ESD
32
ESD
To offset amp
r=4k
r=150k
DC offset Qb
r=2k
r=150k
17
28
From 2nd Mixer
DC offset Q
11
Differential ouptut pins of quadrature demodulator
Q output. Adding a lowpass shunt capacitor
between these pins will define the IF Bandwidth.
DI
16
r=28k
ESD
From 2nd Mixer
2IFout-Q
2IFout-Qb
SC
O
14
15
NT
13
UPB1008K
PIN FUNCTIONS
18
19
20
21
22
23
GNDbb
Qmag
Qsign
Isign
Imag
VCCbb
Function and Application
Internal Equivalent Circuit
Ground pin of CMOS output driver.
Digitized Q signal. Magnitude bit of 2-bit ADC output.
Digitized Q signal. Sign bit of 2-bit ADC output
Digitized I signal. Sign bit of 2-bit ADC output.
Digitized I signal. Magnitude bit of 2-bit ADC output.
Supply voltage pin of CMOS output driver.
23
r=21.5
D
Symbol
From Comparator
Pin No.
r=21.5
r=5k
ESD
UE
19, (20,21,22)
ESD
18
2IFout-Ib
2IFout-I
28
29
VCC if
VAGC
See pin 14 & 15 schematic
30
-15
1.5
2
SC
O
0.5
28
r=4k
r=2k
r=4k
Bias
From VAGC
Ground pin of analog portion of the chip.
r=2k
Regulator
ESD
ESD
r=4k
r=4k
31
30
ESD
ESD
r=1.42k
r=1.42k
32
7
Differential output pins of RF mixer. This is an emitter
follower output buffer, provide a 50Ω output load.
ESD
34
ESD
c=1.67p
33
r=4k
Mixout2
Mixout1
32
VAGC (V)
From Mixer
33
34
r=3k
ESD
Differential input pins of 1st IF AGC amplifier
DI
IF-in1
IF-in2
GNDanalog
To AGC Amp
29
AGC amp out
30
31
32
r=300
ESD
Typical AGC
Gain Response
0
28
r=40
26
27
r=44k
DCoffsetI
See pin 16 & 17 schematic
Regulator
ESD
r=4k
25
DC offset compensation pin for I-bar arm.
A low pass capacitor shunt to Pin 25 is required.
DC offset compensation pin for I arm.
A low pass capacitor shunt to Pin 24 is required.
Differential output pins of quadrature
demodulator I output. Adding a lowpass shunt
capacitor between these pins will define the
IF bandwidth.
Supply voltage pin of analog portion of the chip.
Gain control voltage pin of IF amplifier. This voltage
performs reverse control,(i.e., VAGC up → gain down).
If this pin is left open, then it is default at
maximum gain.
IN
DCoffsetIb
NT
24
c=1.67p
ESD
r=111
r=111
4
UPB1008K
PIN FUNCTIONS
Pin No.
Symbol
35
Vref
Function and Application
Internal Equivalent Circuit
Base-emitter junction voltage wth respect to ground.
May be used for biasing an external discrete
transistor. Regulation will develop PTAT current.
3
r=500
Bias
D
VCC
ESD
Regulator
GND
UE
35
r=40k
ESD
4
LNAbias
LNA output pin. External bias (VCC) and matching
for gain is required.
DI
SC
O
NT
IN
36
1
See pin 2 schematic
UPB1008K
Vref
Mixout1
Mixout2
GNDanalog
IFin2
IFin1
VAGC
VCC if
35
34
33
32
31
30
29
28
D
LNA bias
36
INTERNAL BLOCK DIAGRAM
1
27
2ndIFoutl
LNAin
2
26
2ndIFoutlb
VCCrf
3
25
DCoffsetl
GNDLO
4
24
DCoffsetlb
23
VCCbb
22
Imag
21
Isign
20
Qsign
19
Qmag
/2
1stLO-OSC1
UE
GND LNA
/4
5
Vth
/2
1stLO-OSC2
6
VCCLO
7
PDout
8
PD
VCCdig
9
/2
2-bit
ADC
IN
/6/7
2-bit
ADC
8
17
18
DCoffsetQb
GNDbb
16
DCoffsetQ
6.2±0.2
Package Outline QFN-36
6.0±0.2
Actual size
6.0±0.2
6.2±0.2
6.2±0.2
6.0±0.2
6.4
6.0
3.8
0.5
Pin 36
Pin 1
4 -CO.5
0.22±0.05
0.55±0.2
6.2±0.2
+0.10
36 Pin plastic QFN
0.14 -0.05
Package
UPB1008K-A
SC
O
Part Number
OUTLINE DIMENSIONS (Units in mm)
6.0±0.2
1.0 MAX
14
2IFoutQ
15
13
PD
ORDERING INFORMATION
DI
2IFoutQb
12
I/Q Balance
11
GNDdig
NT
10
REFin
Vth
0.5
Caution:
The island pins located on the corners are needed to fabricate
products in our plant, but do not serve any other function.
Consequently the island pins should not be soldered and should
remain non-connection pins.
Life Support Applications
These NEC products are not intended for use in life support devices, appliances, or systems where the malfunction of these products can reasonably
be expected to result in personal injury. The customers of CEL using or selling these products for use in such applications do so at their own risk and
agree to fully indemnify CEL for all damages resulting from such improper use or sale.
05/27/04
A Business Partner of NEC Compound Semiconductor Devices, Ltd.
D
4590 Patrick Henry Drive
Santa Clara, CA 95054-1817
Telephone: (408) 919-2500
Facsimile: (408) 988-0279
UE
Subject: Compliance with EU Directives
CEL certifies, to its knowledge, that semiconductor and laser products detailed below are compliant
with the requirements of European Union (EU) Directive 2002/95/EC Restriction on Use of Hazardous
Substances in electrical and electronic equipment (RoHS) and the requirements of EU Directive
2003/11/EC Restriction on Penta and Octa BDE.
IN
CEL Pb-free products have the same base part number with a suffix added. The suffix –A indicates
that the device is Pb-free. The –AZ suffix is used to designate devices containing Pb which are
exempted from the requirement of RoHS directive (*). In all cases the devices have Pb-free terminals.
All devices with these suffixes meet the requirements of the RoHS directive.
This status is based on CEL’s understanding of the EU Directives and knowledge of the materials that
go into its products as of the date of disclosure of this information.
Lead (Pb)
Mercury
< 1000 PPM
Concentration contained
in CEL devices
-A
Not Detected
< 1000 PPM
Not Detected
< 100 PPM
Not Detected
SC
O
Cadmium
Concentration Limit per RoHS
(values are not yet fixed)
NT
Restricted Substance
per RoHS
Hexavalent Chromium
< 1000 PPM
Not Detected
PBB
< 1000 PPM
Not Detected
PBDE
< 1000 PPM
Not Detected
-AZ
(*)
If you should have any additional questions regarding our devices and compliance to environmental
standards, please do not hesitate to contact your local representative.
DI
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content of its products represents knowledge and belief as of the date that it is provided. CEL bases its knowledge and belief on information
provided by third parties and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better
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suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for
release.
In no event shall CEL’s liability arising out of such information exceed the total purchase price of the CEL part(s) at issue sold by CEL to
customer on an annual basis.
See CEL Terms and Conditions for additional clarification of warranties and liability.