Full-chip simulation
in smart-power IC’s
ROBUSPIC Workshop
A. Baguenier,
ESSDERC ’06 – Montreux,Switzerland
Friday 22nd of September
ESSDERC ’06, Montreux
ROBUSPIC Workshop
A. Baguenier – Slide
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Outline
On The Way To Trillion Dollar Markets
Electrical Third generation simulation technology
Reliability simulation flow
Behavioural languages
Classical errors
Unused solver features
Conclusion
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ROBUSPIC Workshop
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On The Way To $Trillion Dollar Markets
Margin pressures. Increased competition.
Globalization
Time To Market
Productivity
Design
Design Start
Start Trends
Trends (%)
(%)
IC
IC Dev.
Dev. Costs
Costs ($M)
($M)
100
25
25
20
20
15
15
10
10
55
.18µ .13µ 90nm 65nm
ESSDERC ’06, Montreux
Complexity
Design
Design Team
Team Composition
Composition
450
450
ROW
60
Japan
Europe
20
North America
350
350
250
250
HW
SW
150
150
50
50
‘00
‘02
‘04
‘06
‘08
ROBUSPIC Workshop
‘10
.18u
65nm
.18u .13u
.13u 90nm
90nm 65nm
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On The Way To
Trillion Dollar Markets
It takes a global design chain
Device Mfg.
Design Chain
Spec and
Verification Plan
PCB Design
SW Design
PCB Mfg:
Silicon/SW/PCB
Integration & Testing
System Design & Verification
Chip
Spec
Architecture
Design
Implementation
IC/Package Mfg
AMS or Digital IC Design
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ROBUSPIC Workshop
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Verification Challenges
in Nanometer Designs
Design Issues
Verification Need
Larger designs with more analog &
mixed-signal content
Capacity & performance with minimal
accuracy trade-off for analog
Inter-connect nanometer effects,
capacitive cross-coupling & inductance
Accurate simulation of crosstalk noise
and other signal integrity problems
Critical timing delays due to RC and
cross-coupling capacitance
Seamless post-layout simulation flow
with throughput to handle larger data
Degradation in timing and failures
due to IR drop at low supplies
Accurate simulation of IR drop effects
with capacity to handle large designs
Mixed-signal designs with tighter
interaction between analog & digital
Ability to accurately simulate digital &
analog components as a system
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Smart Power IC
=> Many different voltages
0 to
1Kv
0 to
1Kv
0 to
1Kv
0 to 12v
Different tolerances for each blocs. Local option setting
Multi- rate simulation in the control Unit
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ROBUSPIC Workshop
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Simulator Generations
FirstGeneration
Generation
First
Spectre
Spectre
SPICE
SPICE
SecondGeneration
Generation
Second
ThirdGeneration
Generation
Third
FastSPICE
FastSPICE
Ex:UltraSim
UltraSim
Ex:
Technology
Technology
Technology
Technology
Technology
Technology
CompactModels
Models
Compact
SparseMatrix
MatrixSolver
Solver
Sparse
UniformTime
TimeStep
Step
Uniform
NewtonRaphson
Raphson
Newton
SimplifiedModels
Models
Simplified
MatrixPartitioning
Partitioning
Matrix
EventDriven
Driven
Event
MultiRate
Rate
Multi
RCReduction
Reduction
RC
Hierarchy
Hierarchy
Isomorphism
Isomorphism
AdaptivePartitioning
Partitioning
Adaptive
Applications
Applications
Applications
Applications
Applications
Applications
BlockDesign
Design
Block
Analog/MS/RF
Analog/MS/RF
Prelayout
Prelayout
Tran,AC,
AC,Noise
Noise
Tran,
50Kdevice
devicecapacity
capacity
50K
ESSDERC ’06, Montreux
LargeBlock
BlockDesign
Design
Large
MS/Digital/Memory
MS/Digital/Memory
Pre-/Postlayout
Pre-/Postlayout
Tran
Tran
10Mdevice
devicecapacity
capacity
10M
ROBUSPIC Workshop
FullChip
Chip
Full
MS/Digital/Mem/RF
MS/Digital/Mem/RF
Pre-/Postlayout
Pre-/Postlayout
Tran
Tran
1B+device
devicecapacity
capacity
1B+
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Event Driven Simulation /
Partitioning
FastSPICE
Conventional SPICE
A
X1
X2
One Partition
One Matrix
.
.
.
.
. 
G1 .
.
.
.
. 
 . G2 .
.
. G3 .
.
.
. 
.
.
. G4 .
.
. 
.
.
.
. G5 .
. 
.
.
.
.
. G6 . 
 .
.
.
.
.
. G7
ESSDERC ’06, Montreux
X1
X2
Partition A
Partition B
Event Driven: Partition (Matrix) B is
evaluated only if event at net A
happens
Matrix A
. 
G1 .
 . G2 . 
 .
. G3
ROBUSPIC Workshop
Matrix B
.
. 
G4 .
. 
 . G5 .
 .
. G6 . 
 .
.
. G7
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Multi Rate Simulation
Low frequency partitions
fin
PFD
High frequency partitions
CP
VCO
f/N
••
••
••
Highfrequency
frequencypartitions
partitionsrequire
requiresmall
smalltime
timesteps
steps
High
Lowfrequency
frequencypartitions
partitionsallow
allowbigger
biggertime
timesteps
steps
Low
MultiRate
Rateenables
enablesdifferent
differenttime
timestep/speed
step/speedfor
forpartitions
partitions
Multi
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Representative Transistor
Models
DigitalMOSFET
MOSFETModel
Model
Digital
••
••
20Xfaster
fasterthan
thanBSIM3
BSIM3
20X
Accuratefor
fordigital
digitalbehavior
behavior
Accurate
(speed,power)
power)
(speed,
Optimizedfor
forspeed
speed
•• Optimized
AnalogTable
TableModel
Model
Analog
••
••
••
••
5Xfaster
fasterthan
thanBSIM3
BSIM3
5X
Accuratefor
fordigital/analog/RF
digital/analog/RF
Accurate
circuits
circuits
Optimizedfor
foraccuracy/speed
accuracy/speed
Optimized
Nonlinearcharge
chargepreserving
preserving
Nonlinear
model
model
ESSDERC ’06, Montreux
We do the same for other MOS devices, for
examples:
MOS9, MOS11, PSP, etc….
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Hierarchical Isomorphic
Simulation
X1
Split due to
input change
X2
X3
Adaptive
Partitioning
Subcircuitsseeing
seeingthe
thesame
sameinput
inputare
aresimulated
simulated
•• Subcircuits
byone
onerepresentative
representative(1
(1partition
partitionfor
for1000
1000
by
inverters)
inverters)
Hierarchycan
canbe
bekept
keptas
aslong
longas
asthere
thereare
are
•• Hierarchy
circuitssharing
sharingsame
samerepresentative
representative
circuits
instancesof
ofsame
samesubcircuit
subcircuitsee
seedifferent
different
•• IfIfinstances
inputsignals,
signals,new
newrepresentative
representativeisiscreated
created
input
(splitpartition)
partition)
(split
ESSDERC ’06, Montreux
X2
X3
0V
0V
XINV<999:0>
X1
ROBUSPIC Workshop
XINV<345:0>
3V
XINV<999:346>
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MOSFET Modelling
Spice Model
D
G
I,Q
S
• Analytical model (Spice equations)
used for IV and QV
B
V
Automatic simplification
Example for pure digital bloc
D
B
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D
G
B
S
S
B
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Customized Partitioning
Digital Appl.
Analog/High Precision Appl.
Aggressive Partitioning
ADC
DAC
PLL
VCO
Conservative Partitioning
Bitline
Memory Appl.
Wordline
Aggressive Partitioning
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IR Drop and Ground
Bounce
– Impacts timing and leads to failed silicon.
– IR Drop (ground bounce) increases clock skew.
• Hold time violations
– IR Drop (ground bounce) increases signal skew.
• Setup time violations
– EM is based on average current density.
– Grids have become so complex that current flow is not necessarily
intuitive.
VDD = 1.20V
VDD = 1.1V
CLK
VDD = 1.17V
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Virtuoso UltraSim
Power
-Net Solver Example
Power-Net
•
Mixed-Signal Design
– 3 supply voltages
– 80% parasitic on power-net
Element Count
MOS
DIODE
R
C
Total
10K
256
249K
3.5k
268K
Simulation time
5 ns transient
Platform
2.6 GHz Linux
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UltraSim
UltraSim
Power-Net Solver
2 hrs
36.6 min
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Electromigration (EM)
Transistor
netlist
n4
n3
Transistor current
calculation
n2
Vectors
n1
n8
n5
n6
n7
Power-Grid
Database
Electromigration
analysis
EM
Plotting
– Use VoltageStorm to analyze EM on power grids.
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Reliability A Growing
Concern
• HCI and NBTI Severely Impact Design
– Wasted performance with excessive guard bands
– Yield reduction due to immediate failures
• Must be Addressed With Design Solutions
• What is Reliability Simulation
– Simulating the design to check the probability that a system
will perform its functions over the required lifetime in the
defined operating conditions without failure
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Hot Carrier Effects
• Emax at drain corner causes hot carrier generation
• Hot carriers cause Isub, Igate and oxide damages
S
D
G
For NMOS
& PMOS
Ig
n+
n+
n+
Isub
Isub
P-well
ESSDERC ’06, Montreux
Oxide
Damage
Impact
Ionization
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NBTI a 0.13 Micron CMOS
Crisis
• Negative Bias Temperature
Instability (NBTI)
–
–
–
–
For PMOS at high temperature
Driven by high vertical field
Just appearing in tox < 5nm
Even for zero Vds & long channel
devices
S
G
D
p+
p+
• Causes immediate failures
– Also degrades performance & yield
of PMOS devices
N-sub
Isu
b
Vdd
Mainly PMOS
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Reliability Simulation
Flow With UltraSim
• Built-In support for HCI and
NBTI
• Provides reliability
information
–
–
–
–
Device aging information
Lifetime degradation
Fresh simulation results
Aged model simulation
results
• The age reliability of the
RF performance of CMOS
radio chips are validated
prior to high volume
manufacturing see ref[1]
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RelPro+
BSIMPro+
Reliability
Spec
Reliability
Parameters
Models
Netlist
UltraSim
• Device Age Information
• Lifetime degradation
• Fresh vs. Aged waveform
Comparison
ROBUSPIC Workshop
Fresh vs. Aged
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AMS Top Level Tool Flow
Simulation
Strategy Dev
System Level IP
From System/IC Flow
VSDE
(ADE)
To AMS Block Creation Flow
To RFIC Flow
HDL Sim
AMS Designer
RC Parasitics
From Chip Integration Flow
Mixed Level Simulation
AMS Designer
Spectre
Ultrasim
NC
Hierarchy
Editor
Uses UltraSim in AMS simulation
Transistor Level Block Descriptions
From AMS Block Creation Flow
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Calibrated HDL Models
From AMS Block Creation Flow
ROBUSPIC Workshop
RFIC Content
From RFIC Flow
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Facing Reality
• Verilog-AMS or VHDL-AMS?
– Different languages have different strengths
– We are not starting from scratch
– Different people like different languages
The Ultimate Solution?
• ADA was the ultimate programming language
• VHDL was the ultimate HW description language
• SystemC was supposed to replace all other
languages
• PSL was supposed to be the ultimate assertion
language
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The Wrong Reasons
It’s Fun!
• Emotional
• Religious
• Controversial
Verilog-AMS or VHDL-AMS ?
Languages Are NOT The
Main Issue
• They are a means to an end
• They enable methodologies
• They interface to the engines
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What Is The Main Issue?
Getting first silicon (and software)
out the door,
shipping to customers,
clean
and on-time
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VHDL
-AMS
VHDL-AMS
• To insure the model compatibility some companies
decide to not use SPICE primitive but convert each
SPICE primitive example diode, bjt, bsim3 model to a
VHDL-AMS code
• Is it a good direction to be simulator independent?
• In VHDL-AMS some key statements do not provide
the error limit specification
– wait on aRealQuantity'above(SomeRealSignal);
• Do you start your model coding using the 1076.1.1
IEEE Standard VHDL Analog and Mixed-Signal
Extensions—Packages for Multiple Energy Domain Support
final version ?....
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VHDL
-AMS & Verilog
-AMS
VHDL-AMS
Verilog-AMS
• Third generation simulators may have limitations for VHDL-AMS
or Verilog-AMS model:
– The automatic simplification may not apply on a BSIM3 coded in
VHDL-AMS or Verilog-AMS model
– The VHDL-AMS model implementation is not optimized for speed,
like C++ internal model codes.
– The partitioning… yes or may be ….
• For new devices model development Verilog-AMS language
seem the best languages, because of ADMS.
– Be aware that ADMS support a limited subset of Verilog-AMS.
– Study it before staring the model coding.
• Conclusion:
– You should not spend time to recreate the same SPICE model in
Verilog-AMS & VHDL-AMS
– I suggest to keep the SPICE primitive for fast simulation
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Classical errors
1.
Modeling error
1.
Capacitor modeling, Model discontinuity, function differential (avoid nim, max, abs….)
2.
3.
Check the Weff & Leff of your devices.
Look to the voltage of the grounds. Floating grounds may slowdown
your simulation. (no connection to the electrical solver ground)
4. An oscillator in time domain simulation starts because of the
integration error created by your solver!
– Different integration methods, Different simulator can provide
different starting behavior.
5. Check the elements cut by the simulator.
6. Check the nodes cut by the simulator.
7. If you have a power up sequence, you should start the digital stimuli
after the supply is established.
8. If you are using parasitic back annotation , turn on the RC reduction.
9. Do not reduce the parasitic from the power sensing function.
10. When you save the currents, the system of equations is different in the
electrical solver.
11. Reliability check which Vgs & Vds bias are the worst condition for HCI
& NBTI issues.
12. Read the simulator log files.
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Unused Solver features
capability
• Use envelope analysis to speed up the SMPS
simulation.
• Use periodic steady state, for SMPS working at
constant frequency.
• Use the SpectreRF PXF for switching test case and
stability testing for the feedback system, open loop
analysis.
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Simulation Results Analysis
•
•
•
With the new generation of software like AMS Designer simulator which
include a FastSpice solver.
Designers are able to speed up simulation: example a Complex Power
Management circuit simulated in a SPICE like simulator during 3 months
versus a 2 days simulation time in Ultrasim.
For Smart power IC the current vectors are important for understanding
the circuit behavior in addition to the voltages.
•
•
More and more designers run simulation and save all currents.
The result databases exceeding 30 giga bytes, now , become usual.
•
How to display such database results?
•
One solution for displaying such huge data base above 30Giga is to use
CPU very good in IO performance.
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Interesting CPU
• The Sun Sun Fire V40z Server using Dual Core AMD
Opteron
4 Dual Core AMD Opteron(tm) Processor 880 2390.780MHz, 32Giga of RAM
You open a 30Giga simulation result database for 6 levels of hierarchy (V and I)
and plot 20 electrical signals in less than 15 minutes..
The CPU IO performance is a key…
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Conclusion
• Power IC designs Flows are available.
• Some improvements are still required in reliability
modeling, PDK creation, and usage.
• Designer education, on behavioral modeling, and
tools usage remain.
• Simulation technology continuous improvements are
required for speed, capacity and huge data base
display performance.
• E language seems to be the future for System on
chip verification.
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Acknowledgements
Many thanks to…
• Christian Maier, (Robert Bosch) for the Bosch
contributions to Robuspic WP4
• Renaud Gillon (AMI Semiconductor ) for the AMIS
contributions to Robuspic WP4
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References
• [1]: Mark Ruberto, RFIC Design Group, Wireless Products
Division, Intel Israel Design Center, Haifa, Israel, 2005 IEEE
Radio Frequency Integrated Circuits Symposium, Consideration
of Age Degradation in the RF Performance of CMOS Radio
Chips for High Volume Manufacturing
• [2]: The Future Verification Environment: The Multi-Language
Approach, Cadence Design Systems presentation.
• [3]: ADMS - Automatic Device Model Synthesizer, Laurent
Lemaitre’, SPS – Motorola, IEEE 2002 CUSTOM INTEGRATED
CIRCUITS CONFERENCE
• [4] Virtuoso® UltraSim Simulator User, Cadence Design
Systems.
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Thank you
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