SESSION DR3: Power Management Circuits
4:50 P.M.~ 5:50 P.M., Monday, April 27
Mezzanine A+B
Co-Chairs:
Po-Hung Chen, National Chiao Tung University, Taiwan
Yu-Te Liao, National Chiao Tung University, Taiwan
4:50 P.M.
DR31 All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction
Yi-Ping Kuo1, Po-Tsang Huang1, Chung-Shiang Wu1, Yu-Jie Liang1, Ching-Te Chuang1, Yuan-Hua Chu2,
and Wei Hwang1
1
National Chiao Tung University, Taiwan
2
Industrial Technology Research Institute, Taiwan
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven
sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output
voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current
variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a
timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage
within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the
PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is
implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple
reduction by 81H. Moreover, ns-order voltage transition time and the best lowest FOM of 0.76 pA∙s can be realized.
5:10 P.M.
DR32 A Low-Noise High-Efficient Buck Converter with Noise-Shaping Technique
Jiann-Jong Chen, Ping-Hua Wu, Ta-Wei Chao, Yi-Tsen Ku, Yuh-Shyan Hwang, and Cheng-Chieh Yu
National Taipei University of Technology, Taiwan
In this paper, a buck converter is designed with a noise-shaping technique to reduce noise and uses synchronous
rectification to increase power efficiency. The measured results show the peak noise level less than -84.5dBm at
2MHz and achieve 85H to 93.5H power efficiency with output voltage between 1.8V to 2.5V and a load current
range from 50mA to 200mA. The buck converter is fabricated with TSMC 0.35μm CMOS DPQM process. The chip
area is 1.417mm*1.239 mm.
5:30 P.M.
DR33 A Wireless Power Transmission Subsystem with Capacitor-Less High PSR LDO and Thermal Protection
Mechanism for Artificial Retina Application
Yen-Fu Chen and Kea-Tiong Tang
National Tsing Hua University, Taiwan
This paper presents a wireless power transmission subsystem with high power supply rejection (PSR) low dropout
(LDO) regulator and thermal protection mechanism for artificial retina application. The proposed subsystem
performs the functions of rectification, regulation and thermal detection. It can provide a stable DC source for
implanted devices, and the subsystem only need a small rectification capacitor. The proposed LDO achieve high
PSRR performance of 46 dB at 10 MHz without external capacitor. Moreover, the system contains the thermal
protection mechanism to prevent cells from being damaged. The power controller is also adopted in the system to
feedback control the received power by adjusting resonant capacitance. It can avoid receiving excessive power to
enhance the power transmission efficiency and avoid device being damaged. The proposed subsystem is fabricated
with the TSMC 0.18 um CMOS process and occupies area of 556 um X 700 um. It achieves high power convention
efficiency of 73 % under output voltage of 3.3 V and load current of 5 mA.
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