Physics 3150/5190 Electronics
Lab Manual
University of Virginia
Fall 2013
Instructor: Cass Sackett
I met Steve Wozniak when I was 13, at a friend’s garage. He was
about 18. He was, like, the first person I met who knew more
electronics than I did at that point. We became good friends,
because we shared an interest in computers and we had a sense of
humor.
– Steve Jobs
CONTENTS
CONTENTS
Contents
1 Test and Measurement Tools
1.1 ELVIS . . . . . . . . . . . . . . . . .
1.2 Power Supplies . . . . . . . . . . . .
1.3 Virtual DMM . . . . . . . . . . . . .
1.4 Measuring Current . . . . . . . . . .
1.5 Ohm’s Law . . . . . . . . . . . . . .
1.6 Violating Ohm’s Law . . . . . . . . .
1.7 Electrical Safety . . . . . . . . . . . .
1.8 Resistor Properties . . . . . . . . . .
1.9 Potentiometer . . . . . . . . . . . . .
1.10 Oscilloscope and Function Generator
1.11 Scope Triggering . . . . . . . . . . .
1.12 RC Circuit . . . . . . . . . . . . . . .
1.13 Transformer . . . . . . . . . . . . . .
1.14 Reporting . . . . . . . . . . . . . . .
1.15 Clean Up . . . . . . . . . . . . . . .
2 Impedance and Transfer Functions
2.1 Voltage Divider . . . . . . . . . . .
2.2 DMM Impedance . . . . . . . . . .
2.3 Scope Impedance . . . . . . . . . .
2.4 Cascading Circuits . . . . . . . . .
2.5 RC Filter . . . . . . . . . . . . . .
2.6 Bode Analyzer . . . . . . . . . . .
2.7 Filtering Signals . . . . . . . . . . .
2.8 Cascaded Filter . . . . . . . . . . .
3 Diodes
3.1 Current vs. Voltage .
3.2 Diode Drop . . . . .
3.3 Power Diodes . . . .
3.4 Rectifiers . . . . . . .
3.5 Filtering and Ripple
3.6 Zener Diodes . . . .
3.7 Diode Clamps . . . .
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4 Transistors
4.1 IV Relations . . . . . . . . .
4.2 Transistor Switch . . . . . .
4.3 Emitter Follower . . . . . .
4.4 Common-Emitter Amplifier
4.5 Field Effect Transistors . . .
4.6 FET Switch . . . . . . . . .
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31
31
33
33
35
36
37
CONTENTS
4.7
CONTENTS
FET Follower . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Op
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Amps I
Installation . . . . . . . . . .
Open-Loop Test . . . . . . . .
Inverting Amplifier . . . . . .
Non-inverting Amplifier . . .
Follower . . . . . . . . . . . .
Summing Amplifier . . . . . .
Current Sources . . . . . . . .
Current to Voltage Converter
Logarithmic Amplifier . . . .
6 Op
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Amps II
Output Capacity . .
Offset Voltage . . . .
Bias Current . . . . .
Johnson Noise . . . .
Slew Rate . . . . . .
Frequency Response
Integrator . . . . . .
Differentiator . . . .
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7 Feedback and Control
7.1 LED Driver . . . . . . . . . . . .
7.2 Photodiode . . . . . . . . . . . .
7.3 Summing Amplifier and Set Point
7.4 System Response . . . . . . . . .
7.5 Feedback . . . . . . . . . . . . . .
7.6 Servo Performance . . . . . . . .
7.7 Servo Analysis . . . . . . . . . . .
8 Feedback and Control II
8.1 Proportional Control .
8.2 Integral Control . . . .
8.3 PI Control . . . . . . .
8.4 PID Control . . . . . .
8.5 Transient Response . .
9 Logic Gates
9.1 Transistor Gates
9.2 Integrated Gates
9.3 Logic Levels . . .
9.4 Logic Families . .
9.5 CMOS Logic . . .
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38
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41
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77
CONTENTS
9.6
9.7
9.8
9.9
9.10
CONTENTS
Combinatorial Logic . . .
Three-State Logic . . . . .
Multiplexer . . . . . . . .
Monostable Multivibrator
Logic Races . . . . . . . .
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78
78
79
80
81
10 Sequential Logic
10.1 D-type Flip Flop . . . . . . .
10.2 State Machines . . . . . . . .
10.3 Switch Debouncing . . . . . .
10.4 RAM . . . . . . . . . . . . . .
10.5 Memory-Based State Machine
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11 Counters and Oscillators
11.1 Binary Counter . . . . . .
11.2 LED Display . . . . . . .
11.3 Binary-Coded Decimal . .
11.4 Timer . . . . . . . . . . .
11.5 Quartz Crystal Oscillators
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12 DAC/ADC
12.1 Comparator . . . . . . . . .
12.2 Schmitt Trigger . . . . . . .
12.3 The AD7569 DAC/ADC . .
12.4 Negative Supply . . . . . . .
12.5 DAC . . . . . . . . . . . . .
12.6 ADC . . . . . . . . . . . . .
12.7 Nyquist Sampling Theorem
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99
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101
102
103
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104
105
13 Microcontrollers
13.1 The mbed Microcontroller . . .
13.2 Digital Inputs and Outputs . .
13.3 Arbitrary Waveform Generator
13.4 LCD Display . . . . . . . . . .
13.5 Voltmeter . . . . . . . . . . . .
13.6 Communication with PC . . . .
13.7 Multi-Channel Analyzer . . . .
13.8 Wrap Up . . . . . . . . . . . . .
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119
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120
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A Excel Plots
A.1 Creating a Chart .
A.2 Modifying a Chart
A.3 Fitting Data . . . .
A.4 Excel 2007 . . . . .
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121
CONTENTS
CONTENTS
C LF411 datasheet
123
D AD7569 datasheet
137
6
1
Test and Measurement Tools
This exercise is intended to familiarize you with the measurement tools we will
be using throughout the course, specifically the ELVIS system, the digital multimeter, and the oscilloscope. It also serves to remind you how resistors and
capacitors work.
This lab will require two days.
Reading: HH sections 1.01–1.15, Appendix A (pgs. 1–28, 1045–1049)
1.1
ELVIS
We will be doing most of our work on the NI ELVIS II system, which consists of
a breadboard, several built-in interfaces to the computer, and a set of software
tools running on the computer that duplicate the functions of some common
test instruments.
Take a moment to orient yourself with the board. The large white square
in the middle is the breadboard proper, where you will set up your circuits by
pressing leads into the small holes. The numbered rows are connected internally
in horizontal groups of five, while the ‘+’ and ‘-’ buses are connected vertically
down the whole board. Note that another manufacturer’s breadboard might be
connected differently, even if they look the same. It is always a good idea to
check which contacts are connected when working with a new breadboard. Let
us do that now with the ELVIS board.
A convenient instrument for this purpose is the Fluke 73III Digital Multimeter (DMM). The DMM can measure voltages, currents and resistances. Here
we will be interested in resistance, so turn the selector knob the DMM to the
resistance (Ω) setting. Plug a pair of test probes into the red (V -Ω-diode) input
and the black (COM) inputs of the DMM. Use a pair of short hook-up wires
from your wire box to reach two contacts you want to check, and then hook the
leads of the DMM to the exposed ends of the wires. The resistance should be
zero if the contacts are connected, or infinite (reading ‘O.L’ for overload) if they
are not. Are the contacts are connected as described above? Are the different
columns labeled ‘+’ connected together?
The smaller white rectangles on the edges are interface connections. Each
row is hooked up to a device that can interact with the computer, or to one of
the connectors on the edge of the board. We will often use the block in the lower
left corner, which provides access to the built-in power supplies and connectors.
The connectors on the left edge of the box itself are measurement inputs to
the virtual DMM and and oscilloscope. The knobs on the right side of the box
allow manual adjustment of some of the virtual instruments, but we will not
7
1.2 Power Supplies
1 TEST AND MEASUREMENT TOOLS
often have occasion to use them. The contact blocks on the right side of the
breadboard are for digital measurements, which we will use in the second half
of the course.
The board has two power switches. The one in the back controls the whole
unit. It is easiest to turn this switch on at the beginning of class and leave it on
throughout the lab session. The second switch, near the upper right corner of
the board, controls the power supplies for your circuitry. It is best to turn that
off when assembling a circuit and then turn it on for testing, to avoid damaging
circuit components during assembly.
1.2
Power Supplies
The ELVIS breadboard has several dc power supplies. Locate the +5 V and
±15 V supply contacts on the breadboard. To verify that they do supply these
voltages, use the voltmeter function on your DMM. Turn the selector knob to
the dc volts (V̄ ) setting. Keep the probes in the red and black inputs, and hook
the red probe to the supply contact and the black probe to ground. (Note that
there are several ground connections on the board; they are all the same.) The
display will indicate the measured voltage. Record each in your report, and
note any discrepancies from expectation.
ELVIS also has a pair of variable-voltage supplies that will be useful. They
are controlled from the computer. First, find the ELVIS Instrument Launcher
icon on the desktop or Start Menu. Start the Launcher and then double-click
to start the Variable Power Supply (VPS) virtual instrument. In the resulting
window, set the positive supply output to 10 V and press Run. Then locate the
positive VPS contact on the breadboard and measure its voltage (again relative
to ground); you should see 10 V. Similarly, set the negative supply to -10 V
and check it. Measure both supplies across a full range of values, and make a
chart in your report showing the measured vs. set voltages. How accurate are
the VPS set points? Are there any voltage regions where the accuracy is poor?
(Hint: the answer to the second question is yes, and it will be useful for you to
know where these regions are.)
1.3
Virtual DMM
The ELVIS system provides a virtual DMM you can use in addition to the
Fluke. To start it, run the DMM instrument from the launcher and press Run
in the DMM window. The input connections are located on the left side of the
ELVIS box, and you can use them to hook up probe leads just like on the Fluke.
Compare the readings of the Fluke and the ELVIS DMMs for various settings
on the VPS supplies. Record your measurements in your report. How well do
the Fluke DMM and ELVIS DMM agree?
8
1 TEST AND MEASUREMENT TOOLS
1.4 Measuring Current
300 mA
COM
Figure 1.1: Using the DMM current meter.
1.4
Measuring Current
The DMM can also serve as a current meter. To test this, set up the circuit
of Fig. 1.1, using the Fluke DMM inputs indicated. You can obtain the 1 kΩ
resistor from the component cabinets in the back of the lab. Note that when
using a DMM as a current meter, it is up to you to make sure that the current
rating (here 300 mA) is not exceeded. If you do exceed the limit, you will blow
an internal fuse and have to fix it.
Power up the circuit and measure the current that flows. The DMM selector
knob should be set to dc amps (Ā). Make the same measurement with the ELVIS
DMM. How well do the Fluke and ELVIS DMMs agree? Try reducing the VPS
to 1 V and compare readings.
Note that a voltmeter and current meter are used differently. A voltmeter
is place in parallel with the test circuit and (ideally) no current flows into it.
A current meter is placed in series with the test circuit and (ideally) there is
no voltage drop across it. It is important to understand and remember this
distinction.
1.5
Ohm’s Law
Devise and set up a circuit to simultaneously measure the voltage and current
across a 1 kΩ resistor, using your Fluke and ELVIS DMMs. Describe the circuit
in your lab report. Take several points and create a plot to verify that V = IR;
see Appendix A for advice regarding plot creation and formating.
The slope of your line gives the resistance value; calculate this value using
a linear fit and list it in your report. You can also check the resistance value
using the ohmeter setting of your DMM. How do the two values compare?
Instead of taking current vs. voltage data by hand, you can use the ELVIS
two-wire IV Analyzer instrument. Place the resistor between the DUT+ and
DUT- contacts, near the top of the lower left block. (Here DUT stands for
‘Device Under Test.’) Open up the 2-wire instrument and set the sweep to run
from -10 V to +10 V, with a sensible increment. Press Run and admire the
nice straight line. To transfer the data to your report, first save the data by
pressing the Log button. Pick a file name and save it on the desktop or in a
9
1.6 Violating Ohm’s Law
1 TEST AND MEASUREMENT TOOLS
convenient folder. Then open the file using Notepad (or a similar program) and
cut and paste the data into your Excel report. Add this data as a new series to
the chart you previously made by hand and compare.
1.6
Violating Ohm’s Law
Many devices do not follow Ohm’s Law, including an ordinary incandescent
lamp. Obtain two 6.3 V/150 mA lamps from the supply cabinet. The lamp
resistance is a little too low to measure with the IV Analyzer, so wire two lamps
in series to make a larger resistance. Set the analyzer to run from 0 to 1 V
with a 0.1 V increment, and make sure the gain is set to Low. (High gain is
useful for low-current devices.) If the analyzer complains that you’ve exceeded
the current limit, reduce the final voltage. Import the data and plot it in your
report. Why do you suppose that Ohm’s law is not obeyed here?
1.7
Electrical Safety
Use an ohmmeter to measure to the resistance of your body by holding one lead
in each hand. You should obtain a value in the MΩ range. Compare different
places on your skin, and measure the effect of wetting your skin with saliva.
List your results in your report.
You can be injured by electrical current. You can typically feel a mA or
so, while about 100 mA can be lethal. Given the resistances you measured,
what is the voltage would be required to generate a lethal current? Your result
may be confusing, since you are probably aware that 120 Vac power from a
wall socket can be dangerous. The resolution is that your body is not a ohmic
resistor. As the voltage increases, the resistance can drop significantly as your
skin resistance breaks down. The values you measured with the ohmmeter are
not, therefore, usually relevant for safety concerns.
A good rule to follow is to be careful with any electrical device that can
supply more than 3 mA current at more than 30 V voltage. If either the current
or voltage are definitely below these values, no special precautions are needed.
We should not be encountering any dangerous voltages in this class.
Besides the direct effect on your body, high currents can cause electrical
components to get very hot. This is unlikely to be lethal, but you can receive a
painful burn if you incautiously touch a hot resistor with your finger. A good
rule here is to turn off your circuit power if you start to smell a burning odor.
Let everything cool off for a minute before working on it.
1.8
Resistor Properties
Obtain a 470 Ω and a 330 Ω resistor, and use your DMM to measure the
individual resistances and the total resistance of the two in parallel and in
series. Do the results agree with calculations?
10
1 TEST AND MEASUREMENT TOOLS
Figure 1.2: Measure the power capacity of a resistor.
1.9 Potentiometer
Figure 1.3: Potentiometer configuration. The connection point for pin
B moves as the knob is rotated.
The resistors we use are rated for a power dissipation of 0.25 to 0.5 W. Test
this using a 39 Ω resistor in the circuit of Fig. 1.2. Start with the VPS voltage
low, and slowly turn it up until you smell a burning odor, see smoke, or notice
the resistor start to char. Turn off the board power once this occurs. Noting the
voltage used, what power cause the resistor to overheat? Discard the overheated
resistor once you are done, and try to avoid doing this in the future.
1.9
Potentiometer
A potentiometer (or ‘pot’) is a variable resistor that can be adjusted by turning
a knob. Obtain a 10k pot from the supply cabinet. It has three terminals, as
illustrated in Fig. 1.3. A small screwdriver or a potentiometer driver is useful
for adjusting the knob. Using your DMM, determine which pin corresponds to
which terminal; there is typically no way to tell which terminal is which just by
looking. What are the maximum and minimum resistance values achievable?
How many full turns of the knob does it take to go from one extreme to the
other?
1.10
Oscilloscope and Function Generator
We now turn to the measurement of time varying, or ac, signals. You can
produce an ac signal using the ELVIS function generator. Find and open the
FGEN virtual instrument on your computer. Select a sine wave signal, set the
frequency to 50 Hz and the amplitude to 1 Vpp, and press the Run button.
The signal can be output in two places, as determined by the Signal Routing
setting. The circuit board output is produced at a contact row on the lower left
block of the breadboard. The edge connector output appears on one of the BNC
connectors at the left of the board unit. Only one is available at a time, and
usually the circuit board output is more convenient. Find this, and measure the
voltage between it and ground using your DMM. On the dc voltage setting, the
meter should read zero. What does the ac voltage (Ve ) setting read, and does it
makes sense given the function generator amplitude?
Much more information about an ac signal can be obtained using an os11
1.10 Oscilloscope and Function Generator
1 TEST AND MEASUREMENT TOOLS
Figure 1.4: Oscilloscope controls.
cilloscope. This is a complex instrument, but one that you shall be relying on
throughout the course. If you are unfamiliar with oscilloscopes, you should read
through Appendix A of Horowitz and Hill.
Figure 1.4 shows a picture of your oscilloscope front panel. To monitor the
signal with the scope, use a BNC cable with test lead clips. Plug the cable end
in to the Channel 1 input (#6 on the left).
The black test clip is attached to the shield of the BNC cable and thence to
ground through the oscilloscope. Attaching it to ground in your circuit is good
practice because it provides better shielding and noise reduction, but the lead is
grounded whether you hook it up or not. If you attach it to an arbitrary point
in your circuit it will ground that point, which is probably not what you meant
to do. Note that this is quite different from the behavior of a DMM, where the
red and black terminals are both floating with respect to ground.
Here, attach the clip to your breadboard ground with a wire. Hook the red
clip to the FGEN output. Turn the scope on (#1), set the sensitivity (#9) to
1 V/div, and the time base to 1 ms/div, using the rocker switch (#18). Make
sure the trigger source (#21) is set to Ch 1 and the trigger mode (#22) to
AUTO. Set the function generator to output a 5 Vpp, 500 Hz sine wave, and
run it. You should see the waveform displayed on your scope. Try adjusting
the trace position (#11) and trigger level (#23). The horizontal trace position
can be changed using the Variables knob (#16) when the “H POS” indicator is
selected using the Selector switch (#15).
Note that the scope defaults to an input setting for a 10× probe, as can be
seen on the screen display of the amplitude calibration. We will introduce these
probes in the next lab. For now, change the setting to a 1× probe by holding
12
1 TEST AND MEASUREMENT TOOLS
1.11 Scope Triggering
down the Selector switch and rotating the Variables knob.
The Selector switch can also be used to provide vertical and horizontal screen
cursors, which are useful for making measurements with the scope. Press the
Selector switch down until the Measure indicator is lit. The quantity to be
measured is printed in the top line of the CRT display. Set the measurement to
∆V , so that two horizontal cursors are displayed. Pressing the Cursor button
(#17) selects which cursor is active, and rotating the Variables knob (#16)
adjusts the position of the active cursor. Adjust the cursors to sit at the top
and bottom of the waveform, and read off the peak-to-peak amplitude. Does it
agree with the function generator setting and with the volts per division scale
calibration?
Press the Selector switch again to measure ∆T and check the period of the
waveform. Then select the Freq measurement, for which the oscilloscope should
automatically measure the signal frequency. Record your observations.
Try changing the frequency, amplitude, waveform, and DC offset of the function generator. Make sure that you can adjust the scope to compensate. If you
have difficulty obtaining a steady trace, try readjusting the trigger level knob
(#23). In general, do the the observed signals agrees with the settings? Does
anything special happen at high frequencies? What is the highest frequency
you can produce?
The two small buttons next to the Volt/Div knobs, (#7) and (#8), control
the input coupling to the scope. In DC mode, the scope displays the voltage
directly. In AC mode, the signal is coupled through a high pass filter, which
blocks the dc signal component. This is useful when you are looking at a small
ac signal on top of a large dc offset, but confusing if you are trying to look at a
dc signal and don’t realize the scope is in AC mode. (You will almost certainly
make this mistake at some point during the semester.) When the GND button
is pushed in, the input is ignored and a flat trace at 0 V is displayed. This is
useful for locating the 0 V level, but can again be confusing if the button is
pushed and you don’t realize it. Explore both of these buttons and make sure
you understand their functions.
1.11
Scope Triggering
To use a scope effectively, you need to understand how triggering works. You
might think of the scope as a graphing voltmeter, where the vertical position on
the screen shows the level of the input voltage. The horizontal position, time, is
generated by simply sweeping the measurement spot horizontally at fixed rate.
To see this, turn the function generator frequency down to 1 Hz, and turn the
Time/Div down to 0.5 s. You should then see the measurement point slowly
scanning across the screen, moving up and down as the input varies. If you now
turn the function generator up to 1 kHz, the vertical oscillations become too
fast to see. Conversely, if you leave the function generator at 1 Hz and turn the
scope up to 1 ms/div, then the measurement point moves sideways too quickly
to see, and the vertical motion during any one sweep is tiny. Instead, you see
13
1.11 Scope Triggering
1 TEST AND MEASUREMENT TOOLS
what looks like a horizontal line moving up and down.
Triggering the scope has to do with telling it when to start the horizontal
scan. If you turn the function generator to 1 kHz and the scope to 1 ms/div,
then you should see a steady sine wave trace. This is only possible if the scope
starts each scan at the same point in the oscillation. It does this using the
trigger level. Think of the trigger level as an invisible horizontal line across
the screen. After the scope finishes one trace, it waits until the input signal
crosses that line, and then it starts another one. You can see where the line is
by looking at the vertical position at the left side of the trace. Try adjusting
the trigger level and observe how the starting position changes. What happens
if you move the trigger level above or below the range of the input? What does
the Slope button (#24) do?
The trigger mode (#22) sets the behavior when the trigger level is outside
the input voltage range. Only two options, AUTO and NORM are generally
useful. In AUTO mode, the scope will wait a short time for a trigger to occur,
but if none is received, it will automatically start a trace. The waiting time is
termed the holdoff, and it can be set with the Selector button and the Variables
knob. In NORM mode, the scope will start a trace only when it gets a trigger.
To see this effect, switch to NORM mode and observe what happens when you
adjust the trigger level to a voltage outside the signal range. Explain what you
observe in your report. Can you think some reasons it is useful to have both
modes available?
The trigger source (#21) determine what signal the scope uses for triggering.
Ch 1 and Ch 2 refer to the two input channels, while Ext refers to the EXT
input (#27) that we’ll explore shortly. Line has the scope trigger off the 60 Hz
power line, which is useful if you’re looking at a power line signal (or noise
induced by the power lines).
The external trigger input (#27) is useful when your signal has a varying
amplitude or offset. If you use such a signal to trigger, you will need to continually adjust the trigger level to keep the scope working. To deal with this,
most function generators provide a Sync output, which is synchronized signal
with fixed amplitude and offset. ELVIS has a Sync output located next to the
FGEN socket. Get another test clip and observe this signal on channel 2 of the
scope, by applying the signal to the Ch 2 input (#6, on the right) and setting
the vertical mode (#13) to DUAL. You should observe that the Sync provides
a fixed square wave at the signal frequency. Change the trigger source to Ch
2 and observe that the scope remains triggered no matter how you vary the
function generator signal.
The Sync signal is useful, but not itself interesting to look at. To avoid tying
up one of the scopes input channels, use the Ext input (#27) and set the trigger
source to EXT DC. This has the scope take its trigger from the Sync, but it
doesn’t display it on the screen. This is useful to keep the scope triggered when
you have two varying signals of interest (typically the input and output of your
circuit).
14
1 TEST AND MEASUREMENT TOOLS
1.12 RC Circuit
Figure 1.5: RC circuit.
1.12
RC Circuit
The RC circuit consists of a resistor and capacitor in series, as seen in Fig. 1.5.
It finds a variety of uses in electronics. Here you will use an oscilloscope to
observe its dynamic response. Set up the circuit, and drive it with a 1 kHz
square wave from your function generator. Put the drive signal on the scope
channel 1 and the output on channel 2, so you can see both input and response.
The response should be an exponential wave form
Vout = A + Be−t/RC
starting with each input transition. Measure the exponential time constant by
determining the time required to decay by 1/e ≈ 63%, and verify that it agrees
with expectation. You can check the the value of R with your ohmmeter, and
of C using the ELVIS DMM. (Note that you need to use the DUT contacts
on the breadboard to measure C.) You can also measure R and C using the
component tester at the back of the lab.
Try driving the circuit with a triangle wave and a sine wave, and briefly
describe what you see in your report. With the sine wave, observe what happens
as you
√ increase the drive frequency. At what frequency is the amplitude reduced
by 2 from its input value?
1.13
Transformer
The last piece of equipment we will explore in this exercise is a transformer.
This is enclosed in a gray box labeled “6.3 V/1 A.” There are two styles of box:
one has white, black and green outputs while the other has blue and brown. The
green output is earth ground, while the other pair are the transformer outputs.
The two outputs are symmetric and interchangeable.
The transformer provides a sine wave signal at 60 Hz which will be occasionally required when the function generator is already being used for another
purpose. Observe its output on your scope. What happens if you set the trigger input to Line? What is the amplitude of the transformer signal, and is it
consistent with the 6.3 V label?
15
1.14 Reporting
1 TEST AND MEASUREMENT TOOLS
Figure 1.6: Combining the transformer with a dc signal. Note that the 110 Vac
connection is made by plugging the transformer box into a wall socket.
The transformer output is floating with respect to ground, in much the same
way that terminals in a battery are. Because of this, it can be added to another
signal by simply placing the two sources in series. Figure 1.6 shows an example.
Construct this circuit and observe the output on the oscilloscope. Verify that
the output is the sum of the transformer and VPS signals.
1.14
Reporting
You should have been recording your data, observations, and question answers in
your Excel spreadsheet as you proceeded through the lab. Take a moment now
to look over it and make sure it is clearly organized, that all reported values have
units and appropriate significant digits, that your graphs are labelled correctly,
and that your text answers are readable. At the top of the report, indicate the
lab number and the names of the students participating. Once you are satisfied,
save a copy and email it to the instructor.
1.15
Clean Up
After each lab, return all components to the correct cabinet drawers, remove
all wires from the breadboard and store them in your wirebox, and return any
tools you used to the toolbox.
16
2
Impedance and Transfer Functions
The concepts of impedance and transfer functions are are essential for a clear
understanding of analog electronic circuits. This exercise will explore these ideas
in both dc and ac contexts, and discuss simple applications in voltage dividers
and filters.
This lab will require two days.
Reading: HH Sections 1.16–1.24 (pgs. 28–44)
2.1
Voltage Divider
The voltage divider, Fig. 2.1(a), is a simple but deceptively important circuit.
Its basic use is to reduce a voltage, according to
Vout =
R2
Vin .
R1 + R2
Construct a voltage divider with the values shown. Measure Vout and check that
it agrees with the formula. Use your DMM to measure R1 , R2 and Vin so that
you can make the comparison with some precision. When the input and output
voltages of a circuit can be related in the form Vout = GVin , the proportionality
constant G is known as the transfer function.
The voltage divider introduces the important concepts of input and output
impedance. To understand output impedance, consider the Thevenin equivalent
circuit of Fig. 2.1(b). This shows that from the point of view of the output,
the divider circuit can be considered as an ideal voltage source at Veff followed
by an effective resistance Zout . When no current is flowing out of the circuit,
Vin = 15 V
R1 = 10k
Zout
Vout
Veff
Vout
R2 = 4.7k
(b)
(a)
Figure 2.1: (a) Voltage divider circuit. (b) Thevenin equivalent circuit.
17
2.2 DMM Impedance
2 IMPEDANCE AND TRANSFER FUNCTIONS
there is no voltage drop across Zout , so Vout = Veff , which here must equal
R2 Vin /(R1 + R2 ). So the measurement of the preceding paragraph tells you Veff .
In reference to Fig. 2.1(b), if the output terminal is attached to ground (a
‘short circuit’), a current Iout (short) = Veff /Zout will flow. Test this by shorting
your circuit to ground through your current meter. Record the resulting output
current, and use it to calculate the output impedance
Zout = Veff /Iout (short).
Compare your measurement to the expected value for a voltage divider Zout =
R1 k R2 .
In general, if a current Iout is extracted from a circuit, the Thevenin model
indicates that the output voltage will be Vout = Veff − Iout Zout . Test this by
hooking a 6.8 kΩ resistor from the output to ground, and measure the resulting
output current and voltage. Compare to the Thevenin model prediction.
Considering instead the input to the circuit, the input impedance Zin is just
the net resistance seen from the input of the circuit (Vin ) to ground. It can
typically be measured directly using an ohmmeter. For a voltage divider with
no load, Zin is evidently R1 + R2 . What is the Zin for your divider circuit with
the 6.8 kΩ load resistor? Compare a measurement and calculation.
2.2
DMM Impedance
Like any other circuit, your DMM has a finite input impedance, which it is
useful to know. To measure it, construct Fig. 2.2 using a Fluke DMM on the
voltmeter setting. Because of the finite input impedance, some current will flow
through the 10 MΩ resistor, and the meter will not read 10 V. Equivalently, the
resistor forms a voltage divider with Zin for the DMM, and the voltmeter reads
the divided voltage,
Zin
VDMM =
10 V.
Zin + 10 MΩ
Use this measurement to determine Zin for the meter. Compare to what you
get for the ELVIS DMM.
Figure 2.2: Measuring the DMM impedance. The DMM should be on the
voltmeter setting.
18
2 IMPEDANCE AND TRANSFER FUNCTIONS
2.3 Scope Impedance
Could you alternatively measure Zin for one DMM using the ohmmeter of
the other? What happens if you try?
If you made a voltage divider circuit with R1 = 1 MΩ, R2 = 2 MΩ, and
Vin = 10 V, what reading would you expect to see if you measured the output
with a Fluke DMM?
Devise a method to measure the input impedance of a current meter, and
determine its value for both the Fluke and ELVIS meters. In what situation
could the finite impedance of the current meter cause a measurement error?
2.3
Scope Impedance
Oscilloscopes also have a finite input impedance. The situation here is more
complicated because ac signals are involved, so the scope input impedance is
complex and frequency dependent. The input is typically modeled as a resistor
in parallel with a capacitor, as in Fig. 2.3(a). For dc signals, the capacitor
impedance is infinite so Zin → R. You can therefore measure this easily using
your DMM. What do you obtain?
Obtaining the capacitance is harder. We can’t simply use a capacitance
meter, because the presence of the resistor will spoil the measurement. Instead,
set up the circuit of Fig. 2.3(b). Here channel 1 monitors the input voltage, while
Channel 2 reads the divided voltage Vin Zin /(1 MΩ + Zin ). At high frequencies,
the capacitor will dominate so Zin → (iωC)−1 . Assuming this is true at a
frequency of 100 kHz, measure the Ch 1 and Ch 2 amplitudes and deduce the
value of C.
Because of the decreasing Zin , the oscilloscope’s input impedance can be a
significant load at high frequencies. This effect can be reduced by using a 10×
scope probe (see Appendix A of the text). The probe contains a voltage divider
that reduces the signal level by a precise factor of 10. This can itself be useful
when observing signal levels otherwise too high for the scope to display. The
main advantage, however, is that the divider also increases the input impedance
Input
1M
Scope, Ch 2
R
C
Scope, Ch 1
100 kHz
(a)
(b)
Figure 2.3: (a) Model for oscilloscope input impedance. (b) Circuit for measuring oscilloscope impedance.
19
2.4 Cascading Circuits
2 IMPEDANCE AND TRANSFER FUNCTIONS
by about the same factor. Replace the scope cable with a 10× probe and
measure the dc and ac impedance again. Note the values obtained in your
report. Calculate and compare the frequencies where the magnitude of the
scope impedance reaches 10 kΩ, both with and without the 10× probe.
When using a probe, you can set the oscilloscope input calibration appropriately so that the scale readings compensate for the probe attenuation. Recall
that this is done by holding down the Selector switch and rotating the Variables
knob.
2.4
Cascading Circuits
The concepts of input and output impedance are particularly useful when you
want to hook two or more circuits together. If the output impedance of the first
circuit is much smaller than the input impedance of the second, then effects of
the two circuits are independent of each other.
For instance, suppose you want to divide a signal by 3, and then by 3 again.
You can do this using a pair of 1:3 voltage dividers, as long as you ensure that
the second divider’s Zin is large compared the first divider’s Zout . Design and
assemble a pair of dividers to do this to an accuracy of at least 10% at each stage.
To avoid drawing too much current, don’t use resistors with R < 100 Ω, and
bear in mind that you will need to measure the output with a voltmeter, which
has in input impedance of its own. Describe your circuit and its performance
in your report, noting both the intermediate (÷3) and the final (÷9) output
voltages.
2.5
RC Filter
The RC circuit of Fig. 2.4 can be considered as a voltage divider, with the
resistance R2 replaced by the frequency-dependent impedance Z2 = 1/iωC.
The output voltage can then be immediately expressed as
Vout =
Z2
1
Vin .
Vin =
R 1 + Z2
1 + iωRC
Figure 2.4: RC filter circuit.
20
2 IMPEDANCE AND TRANSFER FUNCTIONS
2.6 Bode Analyzer
Again this defines a transfer function G(ω) via Vout = G(ω)Vin , but here and in
general, G is a function of frequency. This means that it is only directly useful
for sinusoidal signals, where ω is well-defined.
Here the magnitude
1
|G| = √
1 + ω 2 R2 C 2
is nearly 1 for small ω, but decreases like ω −1 for large ω. This circuit can
therefore be used as a low pass filter. The cutoff frequency at which the filtering
action begins is fc = (2πRC)−1 . The attenuation |G| can be measured with an
oscilloscope, since |G| = |Vout |/|Vin | where |Vn | represents the amplitude of signal
n.
If G is expressed as |G|eiφ , the phase φ represents a phase shift between the
input and output. For the RC circuit,
φ = − tan−1 (ωRC).
The phase shift can be measured by comparing the time delay ∆t between
zero crossings of the input and output wave forms: If the input signal varies as
cos(ωt) and the output as cos(ωt+φ), then the input will cross zero at ωt1 = π/2
while the output crosses zero at ωt2 + φ = π/2. Solving for φ yields φ = −ω∆t
for ∆t = t2 − t1 . (Note that φ is negative when the output lags the input.) This
formula gives a value in radians; in degrees, use φ = −360f ∆t for frequency f
in Hz.
Set up a low pass filter using R = 10k and C = 10 nF. Use the oscilloscope
to measure the attenuation and phase shift of a sine wave at frequencies of 10,
100, 300, 1000, 3000, 10k, and 100k Hz. Plot the attenuation and phase vs.
frequency. Note that the scope coupling can be in either ac or dc mode for
these measurements, but the coupling for both channels must be the same to
avoid introducing spurious phase shifts.
Because of the large range in frequency and amplitude, it is generally more
convenient to make plots on a log scale. Conventionally, the amplitude of the
transfer function |G| is measured in decibels (dB), given by g = 20 log10 (|Vout /Vin |).
Make another pair of plots for your data with the gain in dB and phase shift in
degrees vs. log(f ). This representation of a transfer function is termed a Bode
plot.
For comparison, use Excel to calculate the theoretical values for g and φ,
and add them to your Bode plot.
2.6
Bode Analyzer
Bode plots are a powerful tool for analyzing circuit performance, but they can
be tedious to measure. The ELVIS Bode Analyzer instrument can simplify this
process. Find the analyzer instrument on the computer and open it. Set the
Stimulus Channel to Scope Ch 0, and the Response Channel to Scope Ch 1.
Leave the function generator hooked up to your circuit, but close (or at least
turn off) the FGEN tool.
21
2.7 Filtering Signals
2 IMPEDANCE AND TRANSFER FUNCTIONS
Make the following connections to use the analyzer tool:
1. Use a cable to connect the function generator output to the Scope 0
connector on the side of the breadboard. This is how the instrument measures
Vin .
2. Hook Vout from the circuit to the Scope 1 connector. This provides a
measurement of Vout .
Use the Bode tool to take a measurement from 10 Hz to 100 kHz. It should
generate a plot similar to the data you took by hand. Save the log file and
import it into Excel, and add the data to your previous graph. The graph will
be clearest if you use lines for the ELVIS data and points for the data you took
by hand. Note any disagreements you observe.
Swap the resistor and capacitor, and use the analyzer to observe how the
Bode plot changes. What kind of filter is the circuit now? Plot this data in
your report.
2.7
Filtering Signals
Filters are mostly used for eliminating noise, so to see them in action we need
to create a noisy signal. This can be achieved by adding a high frequency signal
from the function generator to the 60 Hz signal from the transformer, using the
circuit of Fig. 2.5. (Recall the similar circuit you studied in the first lab.) The
1k resistor limits the current flow to a few mA. Assemble the circuit and observe
the output on the scope. Depending on the time scale setting, you should see
either a 60 Hz signal with high-frequency “noise” or a 20 kHz signal with a
fluctuating offset.
Suppose first that the low frequency signal is of interest. Pass the composite
signal through a low-pass filter with C = 10 nF and R = 10 kΩ and describe
the output. Does the filter successfully isolate the low-frequency component?
What is the amplitude of the residual high frequency component, and does that
amplitude agree with expectations?
in
out
out
Figure 2.5: Composite signal generator.
Figure 2.6: Cascaded filters.
22
2 IMPEDANCE AND TRANSFER FUNCTIONS
2.8
2.8 Cascaded Filter
Cascaded Filter
If you want to attenuate high frequency signals more effectively than the circuit
of Fig. 2.4 achieves, you can cascade two filters, as in Fig. 2.6. Design such a
filter with a cut-off frequency of about 1.5 kHz. There are many ways to achieve
this, but the design will be simple if you ensure that the input impedance of
the second filter is much larger than the output impedance of the first filter. In
that case, the attenuations of the two filters will simply multiply. (Compare to
the experiment with cascaded dividers from Section 2.4.) Describe your circuit
in your report.
Put your circuit together and measure its Bode plot with the analyzer. Include the data in your report. Compare to what you saw for the filter of Fig. 2.4.
Note that when the phase φ drops below -180◦ , the Bode analyzer wraps the
phase around to +180◦ . This makes the plot hard to read, but you can fix it by
manually subtracting 360◦ from the appropriate points in Excel.
Run the composite signal of Fig. 2.5 through the double filter. Describe your
observations, and compare to your single filter results.
23
2.8 Cascaded Filter
2 IMPEDANCE AND TRANSFER FUNCTIONS
24
3
Diodes
A diode is perhaps the simplest non-linear circuit element. To first order, it acts
as a one-way valve. It is important, however, for a wide variety of applications,
and will also form the starting point for understanding transistors.
This lab will require one day.
Reading: HH Sections 1.25–1.31 (pgs. 44-53)
3.1
Current vs. Voltage
Semiconductor theory predicts that the current through a diode is given by
I = Is [exp(V /V0 ) − 1] ,
where V is the voltage across the diode, Is is a current scale, and V0 is a voltage
scale on the order of kT /e for absolute temperature T , Boltzmann constant k
and electron charge e. We can verify this prediction using the ELVIS 2-wire
analyzer.
Obtain a 1N914 diode from the supply cabinet. Note that one end of the
diode is marked with a bar; this end is the cathode (see Fig. 3.1). Place the
diode into the DUT contacts, with the cathode end in the negative terminal.
Run the analyzer from -10 V to 10 V with a 0.5 V step and low gain. The
analyzer will quit at some point when the current becomes too high; that is
fine. Describe the response you do see in your report.
Getting a more detailed plot takes some extra work, because of the large
range of currents involved. In particular, the low gain setting on the analyzer
doesn’t give an accurate value for small currents, but the high gain setting
doesn’t let the current grow large enough to see everything we want. So to get
a clear picture, break the plot into three sections: First, run the analyzer from
-10 V to 0 V with 1 V steps and high gain. Export this data and paste into your
report. Second, run the analyzer from 0 V to 0.5 V with a 0.1 V increment and
Figure 3.1: The diode circuit element.
25
3.2 Diode Drop
3 DIODES
high gain. Paste this data into your report as well. Finally, run the analyzer
from 0.5 V to 1.0 V with a 0.05 V increment and low gain. The scan may stop
early, that’s fine. Paste this data along with the others in your report, and plot
all three together on one graph.
To compare to the theory prediction, we need to know Is and V0 . To get
these, make another plot with just the third section of data, where V > 0.5 V.
In this range, the current should scale as I = Is exp(V /V0 ) since the exponential
will be much larger than one. So if you plot ln I vs V , it should appear as a
more-or-less straight line. Use Excel to fit this line, and from the fit parameters
determine Is and V0 . Record these in your report. Is V0 on the order of kT /e
as expected?
Now that you have Is and V0 , construct a theoretical prediction for I(V )
and plot it along with the full range of your data. How well does the prediction
agree?
3.2
Diode Drop
Most often, it is not necessary to use the full theoretical model for the diode.
Instead, we can approximate the IV relation as
(
0 if V < VD
I=
∞ if V > VD
for a value VD known as the diode drop. In practice this means that if you
try to apply a voltage larger than VD , enough current will flow that the applied
voltage will be reduced to VD (or until the diode breaks, if the source can output
a large enough current.) Clearly this is an imprecise model, since the IV curve
you measured above is not actually a step function. However, the curve is quite
steep and the diode drop model is often adequate. Estimate the diode drop
here by determining the voltage drop at which I = 1 mA. (You can do this by
reading it off your plot, rather than by measuring it directly.) How much would
this change if a current of 2 mA or 5 mA were used instead? This uncertainty
indicates the level of accuracy of the diode drop model, typically a few tenths
of a volt. If more precision is required, the better model should be used.
The diode drop can also be measured using the diode setting on your DMM.
What value does it give for the 1N914 diode? Based on your previous measurements, what current does this correspond to?
3.3
Power Diodes
According to its datasheet, the 1N914 diode can conduct a forward current of
about 75 mA before it overheats and breaks. Larger diodes can carry much
larger currents. For instance, the 1N4001 diode is rated for 1 A. There is a
tradeoff to using higher power diodes, however, because they generally have
a slower response. The limit to a diode’s response speed is primarily due to
26
3 DIODES
3.4 Rectifiers
DUT+
DUT-
Figure 3.2: Circuit for measurement of diode capacitance.
the effective capacitance of the diode junction, and higher power diodes have
a larger capacitance. This causes high-frequency signal components to ‘leak’
through the junction as if it weren’t there.
This capacitance can’t be measured directly because of the forward conduction. The circuit of Fig. 3.2 solves this problem by measuring a pair of diodes
in series. Wire up this circuit using 1N914 diodes. Given your measurement of
the pair, what is the capacitance of a single diode? Now set up the circuit using
1N4001 diodes instead, and again determine the single-diode capacitance. How
do the two diodes compare?
3.4
Rectifiers
A common use for diodes is rectification, in which an ac signal is converted to
dc. For instance, rectification is needed to convert an ac power line to a dc
power supply. Fig. 3.3 shows the simplest type of rectifier, often referred to as
a half-wave bridge. Assemble this circuit using Rload = 2.2 kΩ. Observe the
output on your scope. Are the amplitude and polarity of the peaks what you
expect? Can you see the effect of the diode drop?
The full-wave bridge of Fig. 3.4 is more efficient (and thus more common)
than the half-wave bridge. Before building anything, think through the circuit
and describe in your report what you expect the output signal to look like.
Then wire up the circuit (again with Rload = 2.2 kΩ) and see if you got it right.
6.3 Vac
120 Vac
1N4001's
out
load
Figure 3.3: Half-wave bridge.
Figure 3.4: Full-wave bridge.
27
3.5 Filtering and Ripple
3.5
3 DIODES
Filtering and Ripple
We can reduce the remaining ac component in the output of a rectifier using a
capacitor as a filter. Place a 15 µF capacitor in parallel with the load resistor in
Fig. 3.4. Notice that this type of capacitor is polar, meaning that the terminal
marked with a negative sign should be held at a more negative voltage than
the positive terminal. Be sure to orient the capacitor in your circuit correctly.
What is the resulting dc output voltage? The output should also have a small
ac ‘ripple;’ what is the peak-to-peak amplitude of this ripple? What changes if
you change the 2.2 kΩ load resistor to 1 kΩ?
The ripple in the output should have a characteristic ‘sawtooth’ shape. We
can understand where it comes from with a simple model:
During each ac cycle, the capacitor is alternately charged by the supply
and then discharged through the load. In the limit of small ripple amplitude,
the voltage is nearly constant during the discharge, so the discharge current is
nearly constant as well and is simply given by Idischarge = V /Rload for dc output
voltage V . The ripple amplitude can then be estimated using
Idischarge = C
dV
∆V
≈C
dt
∆t
where ∆V is the variation in V (the ripple amplitude) and ∆t is the discharge
time. You can measure both ∆V and ∆t using your scope. Using your values
for R, C, V and ∆t, what ripple amplitude ∆V is predicted, and how does
it compare to your observations? You can use either the 1 kΩ or 2.2 kΩ load
resistor, as you prefer, but note your choice.
Replace the 15 µF capacitor with a 470 µF capacitor, and again compare
the ripple to the prediction. This circuit should now be a respectable dc power
supply. However, a real power supply would include a voltage regulator to
improve its stability in response to changing loads. Diodes can be used for this
purpose as well, as explained below.
3.6
Zener Diodes
Obtain a 1N746A (or an equivalent 3.3 V) zener diode from the cabinet, and
install it in the IV analyzer with the cathode on the DUT- terminal. If you try
to run the analyzer from -10 V to 10 V, you will immediately get an error. Run
it instead from 0 V to 1 V. Are there any obvious differences from the 1N914
diode?
Now reverse the diode so that the cathode is in the DUT+ terminal, and
run the analyzer from 0 V to 10 V on the low gain setting. How is the result
different from what you would expect with the 1N914 diode with the leads
similarly reversed? The conduction observed at around 3 V is termed reverse
breakdown. All diodes will exhibit reverse breakdown if a large enough reverse
voltage is applied. For regular diodes, this voltage is normally 50 V or more,
but in a zener diode, it is designed to be a specified low value.
28
3 DIODES
3.7 Diode Clamps
Figure 3.5: Voltage reference using zener diode.
An important use for a Zener diode is as a voltage reference. For example,
wire up the circuit of Fig. 3.5 and measure the output voltage with a VPS setting
of 10 V. Due to the nonlinearity of the diode, the output is relatively insensitive
to the input voltage and the output current. To demonstrate this, change the
input supply voltage to 8 V and note the output change. Also, attach a 1 kΩ
resistor from the output to ground as a load. Based on the observed voltage
drop, what is the output impedance of the regulator circuit?
This type of circuit is useful any time you need a fixed reference voltage.
A fancier version with a temperature stabilized zener diode is available as the
LM399 integrated circuit.
3.7
Diode Clamps
Another use of diodes is for circuit protection. Various configurations of diodes
can limit a signal to a specified range, and thus prevent accidental damage to
more sensitive and expensive components.
For instance, the the circuit of Fig. 3.6(a) prevents the output signal from
exceeding 5 V. Construct the circuit and drive it with a 10 Vpp sine wave from
the function generator. Observe the output on your scope as you vary the DC
offset from -5 to +5 V. Does the clamp perform as claimed?
Two other types of voltage clamp are shown in Figs. 3.6(b), and 3.6(c). You
don’t need to build these circuits, but think about them and explain what they
do in your report.
Vin
Vout
Vin
Vout
Vin
Figure 3.6: (a) 5 V clamp. (b) Zener clamp. (c) Limiter.
29
Vout
3.7 Diode Clamps
3 DIODES
30
4
Transistors
Transistors are the basic building blocks of active electronics. Unlike passive
elements, transistor circuits can provide positive gain. This gain can be in the
voltage, the current, or the power of a signal.
This lab will require two days.
Reading (Bipolar transistors): HH sections 2.01-2.07, (pgs. 62–77)
Reading (Field effect transistors) : HH sections 3.01-3.03, 3.11-3.12 (pgs. 113–
121, 140–151)
4.1
IV Relations
This exercise will focus on the 2N3904 npn transistor, shown in Fig. 4.1. Locate
and obtain one from the supply cabinet. Before anything else, check that it is
functioning correctly using the diode-test setting on your DMM. The transistor
should look like a pair of diodes as shown, with a diode drop of about 0.6 V. If
it does not, discard it and try another.
The transistor is a 3-terminal device, and is therefore more complicated
to characterize than a 2-terminal device like a diode. The important aspects,
however, can be observed using the circuit of Fig. 4.2. The idea is to measure
Vb and Vc as functions of Vin . Ohm’s law and the resistor values Rb and Rc
can then be used to determine the base current Ib and collector current Ic . To
facilitate this, accurately measure Rb , Rc , and the output voltage of the 5-V
supply prior to constructing the circuit.
2N3904
E B
C
Package
Diagram
Testing
Figure 4.1: Package and schematic of a 2N3904 npn transistor.
31
4.1 IV Relations
4 TRANSISTORS
Figure 4.2: Circuit for measuring IV characteristics of a transistor. Use the
ELVIS and Fluke DMMs for the measurements.
Assemble the circuit using the ELVIS variable power supply as the input.
Record Vb and Vc as Vin is varied between 0 and 12 V. Along with knowing Vin
and the supply voltage, this lets you calculate the currents Ib and Ic via Ohm’s
law. (Recall, however, that the VPS supply is inaccurate near V = 0. You’ll
want to check Vin there with a meter.) Take enough data to get a fairly even
spread of Ib values; this will probably require more points near Vin = 1 V than
required near Vin = 0 V or 10 V. Use your data to prepare three plots: (a) Ib
vs. Vb , (b) Ic vs. Ib , and (c) Vc vs. Ib .
The first plot should show that the base-emitter junction behaves essentially
like a forward-biased diode. This relation is used to determine the magnitude
of the base current, and also implies that, in conduction, the emitter voltage is
always about a diode drop lower than the base voltage.
The second plot illustrates that the transistor provides current gain: you
should see that for small Ib , the collector current satisfies Ic ≈ βIb . What value
of β does your transistor exhibit? At larger Ib the curve should flatten out,
which could be represented by β decreasing. This effect is termed saturation.
The third plot also relates to the saturation effect. As the collector current
increases, the collector voltage decreases due to the drop across Rc . This is
the reason that the transistor gain saturates: at large base current, there is
not enough voltage at the collector to maintain the Ic = βIb relation. When
Vc is as small as it can get, we say that the transistor is completely saturated.
The minimum voltage is then the saturation voltage Vces . What is Vces for your
transistor?
This argument suggests that the saturation current would be larger if Rc
were smaller or if the 5 V supply voltage were larger, since in either case Vc
would be larger for a given Ic . This is correct. However, the 2N2904 can only
handle currents of up to 200 mA before overheating and breaking. Transistor
circuits should always include appropriate current-limiting resistors to prevent
damage. What is the smallest Rc usable here that would still limit Ic to a safe
value?
32
4 TRANSISTORS
4.2 Transistor Switch
5V
SYNC output
of FGEN
0.5 Hz
2N3904
6.3 V/150 mA
lamp
(a)
(b)
Figure 4.3: (a) Attempting to turn a lamp on and off using a function generator.
(b) Using a transistor as an electrically controlled switch.
4.2
Transistor Switch
One simple transistor application is a switch. Here the linear amplification
behavior is ignored, and the transistor is operated in only two modes: either
with Ib = Ic = 0 (‘off’), or with Ib large enough to saturate the transistor (‘on’).
This configuration allows a small base current to switch a large collector current
on and off.
To explore this, consider Fig. 4.3(a), which illustrates an attempt to turn
a lamp on and off using the function generator SYNC output. Recall that the
SYNC output consists of a square wave signal that switches between 0 V and 5
V.
Start by verifying that 5 V is sufficient to illuminate the lamp, by installing
the lamp between the 5 V power supply terminal and ground. Then construct
the circuit of (a). Does the lamp turn on? The lamp requires a current of at
least 75 mA to illuminate. How do you suppose that compares to the amount
of current that the SYNC output can provide?
Figure 4.3(b) shows how this problem can be solved using a transistor. Only
a small base current is required to control the transistor, while the 5 V supply
provides plenty of current to run the lamp. Wire up this circuit and verify that
it works. Why is it better to put the lamp on the collector terminal, rather than
the emitter? (Think about the base voltage required in either case.)
4.3
Emitter Follower
The switch circuit in the previous section can be considered as a current gain
device, since it allows a small current from the function generator to control a
large current through the lamp. A more explicit type of current amplifier is the
emitter follower. A follower is, in general, a device that boosts the current that a
signal can provide without significantly changing the signal voltage. We say that
the output ‘follows’ the input. Followers are also often called buffers, though a
buffer amplifier may provide voltage gain along with current amplification.
33
4.3 Emitter Follower
4 TRANSISTORS
+5 V
3.3k
3.3k
Vout
1 Vpp
1 kHz
10k
1 Vpp
1 kHz
10k
RL = 100
(a)
(b)
Figure 4.4: (a) A voltage divider used to attenuate a signal. (b) An emitter follower on the output of the divider, used to increase the current output
capacity.
To see how a follower could be useful, consider the circuit of Fig. 4.4(a),
which shows a voltage divider functioning as a variable attenuator for the input
signal. This might serve, for instance, as a volume knob for an audio source.
Construct this circuit and verify that the potentiometer allows the output signal
amplitude to be controlled.
However, suppose now that the signal is required to drive a low impedance
load (a speaker, for instance). To model this, attach a 100 Ω resistor from the
output to ground, and again observe the output voltage. You will see that the
high impedance divider is unable to supply enough current to drive the load, so
the circuit does not function correctly.
Figure 4.4(b) shows how an emitter follower can solve this problem. To
analyze the circuit, remember that the emitter of the transistor will always be
one diode drop below the base. If the base voltage starts to rise, the base current
will rise, causing the collector current to rise via Ic = βIb . Since β is large, a
substantial collector current can flow, which eventually passes through the load
resistor. This in turn causes the emitter voltage to rise, until it is again about
a diode drop below the base.
In practice, this just means that the emitter follows the base voltage (neglecting the diode drop), but can supply more current by a factor of roughly β.
Equivalently, the output impedance of the attenuator circuit is reduced by β.
Construct the circuit, with the 10 kΩ pot set to provide the maximum output
level. What do you observe at the output? At first, you will likely see only a flat
line at 0 V. This is understandable if you consider what happens when the base
voltage is negative or close to zero. You can compensate for this by adjusting
the dc offset on the function generator to make the input signal more positive.
Try a range of offset values, and describe in your report what the output signal
34
4 TRANSISTORS
4.4 Common-Emitter Amplifier
out
Figure 4.5: Common-emitter amplifier
looks like for offsets of 0 V, 0.5 V, 1 V, and 2 V. Given the attenuation from
the divider and the voltage drop, what offset would you expect to be needed
in order to ensure that the full range of the input oscillation is applied to the
load?
The need to keep the base voltage in a suitable range is a generic and sometimes challenging problem. We say that the transistor must be biased correctly.
There are a variety of solutions, such as adding circuitry to provide a fixed dc
offset, returning the load to a negative power supply, or adding a pnp transistor
to the circuit, which can sink current to a negative supply. Further discussion
can be found in the text.
4.4
Common-Emitter Amplifier
We have considered a transistor as a current amplifier, but the amplifiers we
are most familiar with are voltage amplifiers. The common-emitter amplifier
of Fig. 4.5 shows one way a transistor can be used to provide voltage gain.
To analyze this circuit, take the input voltage to be Vin . The emitter voltage
will then be Vin − VD for diode drop VD . This implies an emitter current Ie =
(Vin − VD )/Re and an approximately equal collector current Ic . If VS is the
collector supply voltage (here 15 V), then the output voltage will be
Rc
Rc
Rc
(Vin − VD ) = Vs −
VD −
Vin .
Vout = VS − Ic Rc ≈ VS −
Re
Re
Re
The dc offset of the signal is changed, but the ac part is multiplied by Rc /Re ,
which can be larger than one.
Construct the circuit as shown, using Re = 1 kΩ and Rc = 10 kΩ. Drive
the input with a 0.1 Vpp sine wave at 1 kHz. It will be necessary to adjust the
input dc offset to properly bias the amplifier, similar to what was required for
the follower circuit. What ac gain amplitude do you observe? Is there a phase
shift between the input and output signals?
35
4.5 Field Effect Transistors
4 TRANSISTORS
Once again, there are a variety of more general solutions to the biasing
problem, as well as several other ways to improve the amplifier performance.
Consult the text for further information.
It is useful to know the output impedance of your amplifier. You can check
this by hooking up an appropriate resistor to ground as a load, and observing
the reduction in the output amplitude. Recall that with a load resistor RL , the
output voltage will be reduced to
Vout (load) =
RL
Vout (open).
Zout + RL
Note that if RL is small compared to Zout , then the large change in Vout may
lead to non-linear behavior. It is best to use a load resistor that produces
a modest, but measureable, change in the output amplitude. You may need
to try a few different loads to achieve this. Note the resistor used and your
calculated impedance in your report. Does your value makes sense given the
circuit design? How might you modify the circuit if a lower impedance were
required?
4.5
Field Effect Transistors
Field effect transistors (FETs) are are another type of transistor. In most
respects, they are typically inferior to the bipolar junction transistors considered
up to now. They offer one key advantage, however: they do not require any
control current to operate. This leads to many useful applications.
There are a several different flavors of FETs, which are discussed in the text.
We will work with the 2N5459, an n-channel JFET. The pin configuration is
shown in Fig. 4.6. The gate, drain, and source terminal correspond to the base,
collector, and emitter terminals of a bipolar transistor.
In a JFET, the gate-source and gate-drain connections form diodes, just like
the base-emitter and base-collector junctions in a bipolar transistor. Check this
with your DMM, just as you did for the 2N3904 of Fig. 4.1. What diode drops
do you measure?
Unlike a bipolar transistor, a JFET is operated with VG < VS < VD , meaning
that the gate diodes are backward-biased and no current flows through the gate
Figure 4.6: Pin identification and circuit diagram for the 2N5459 FET.
36
4 TRANSISTORS
4.6 FET Switch
Figure 4.7: Circuit to measure the IV characteristics of an n-channel JFET.
terminal. It is important not to apply a forward bias to the diodes, because the
FET can be destroyed by a large gate current.
Even though there is no gate current, the gate voltage can still control the
current between the drain and the source. Observe this using the circuit of
Fig. 4.7. Start with the drain voltage (the positive VPS) set at +10 V and
the gate voltage (the negative VPS) set at 0 V. Measure and record the drain
current, which should be on the order of 10 mA. Vary VG down to -5 V in 0.5 V
steps and plot the resulting ID vs VG curve. At what VG does the current go
to zero? In the linear portion of the graph, what is the slope dID /dVG ? This
quantity is known as the transconductance, measured in Ω−1 .
Reduce the VD to 5 V, and remeasure the ID vs VG curve. (You can take
larger steps this time.) Add the new data to your plot. You should see that
the drain current is mostly independent of the drain voltage, so the FET really
does control the current.
To explore the VD dependence further, set VG to zero and plot ID vs VD for
drain voltages between 0 and 10 V. You’ll want more points at lower voltages,
but don’t forget that the supply doesn’t go below 0.3 V or so. You can attach a
wire directly to ground to measure at VD = 0 V. Plotting your data, you should
be able to see a constant-current regime at large VD and a resistive regime at
low VD . In the resistive regime, what is the resistance? Measure this data again
with a gate voltage VG = −1 V and add it to your plot to compare. What is
the resistance now?
4.6
FET Switch
A key application of FETs is as a voltage controlled switch. This works much
the same as the bipolar circuit of Fig. 4.3, with the advantage that no input
current is required. The disadvantage is that the switching current capacity is
much lower: only about 10 mA for the 2N5459 compared to 200 mA for the
37
4.7 FET Follower
4 TRANSISTORS
out
Figure 4.8: Use of a FET as a voltage-controlled switch.
2N3904. Because of this, we will switch an oscillator signal rather than a lamp
current.
Construct the circuit of Fig. 4.8. Use your 6.3 V transformer as a signal
source, with a 10 V dc offset to ensure proper biasing. This produces a 20 Vpp
signal running from 0 V to 20 V. Verify this with your scope before connecting
the FET to the circuit.
The function generator serves as a control signal. The idea is that when the
control signal is low, the FET does not conduct, so Vout will simply follow the
transformer output. When the control signal is high, the FET conducts, effectively shorting Vout to ground through a small effective resistance. To achieve
this, set the amplitude and offset of the function generator such that the the
minimum value of the control signal is −5 V (the FET is ‘off’) and the maximum
value is zero (the FET is ‘on’).
What do you see at the output? You should expect a signal that ‘chops’
alternately between the 60-Hz transformer output and ground. Try varying the
function generator frequency, and try using a sine wave or triangle wave instead
of a square wave. Describe your observations in your report. Does anything
change if you place a 1 MΩ resistor between the function generator and the
gate? If not, what can you conclude about the gate current?
4.7
FET Follower
Another important FET circuit is the follower of Fig. 4.9. Compared to the
emitter follower of Fig. 4.4, the FET version offers again much lower input
current. A variant of this circuit is used in DMMs and oscilloscopes to provide
the high input impedance those devices require.
It is probably not immediately obvious how this circuit works. To analyze
it, assume that some unknown current I is flowing through the lower FET, Q2 .
Then Q2 ’s source will be at voltage VS2 = −15+IR, and the gate-source voltage
38
4 TRANSISTORS
4.7 FET Follower
+15 V
Q1
Vin
R = 1k
Vout
Q2
R = 1k
- 15 V
Figure 4.9: FET follower circuit. Both transistors are 2N5459 JFETs
will be VGS2 = −IR. Since VGS determines I through the FET transconductance, the current I is implicitly determined by the equation VGS (I) = −IR.
This could be solved graphically using the data you took in section 4.5, but
don’t bother for now.
Assuming no load on the output, the same current I flows through both
transistors. If the FETs are identical, Q1 will have the same transconductance
as Q2 , so for the same current, VGS will be the same as well. We must therefore
have VS1 = VG1 +IR. Since Vout = VS1 −IR and VG1 = Vin , we obtain Vout = Vin
as desired for a follower.
In practice, Vin and Vout won’t match exactly because neither the two FETs
nor the two resistors are perfectly identical. Construct the circuit and drive
it with your function generator. How well does the output track the input?
Compare both the dc offsets and the ac amplitudes, over a range of input
voltage levels.
To verify that the circuit works as explained above, set Vin to zero (or some
other dc value). Then determine the FET current IDS by measuring the (dc)
voltage drop across one of the resistors with your DMM and using V = IR.
This same voltage is equal to VGS . Verify that the IDS and VGS values you
measure here are consistent with the IDS vs. VGS data you took in Section 4.5.
Measure the output impedance of the circuit, using the same method as for
the common-emitter amplifier of Section 4.4. Does the value you obtain make
sense, given the circuit design?
39
4.7 FET Follower
4 TRANSISTORS
40
5
Op Amps I
The operational amplifier (op amp) is the single most important active circuit
component for analog electronics work. It can perform a wide variety of useful
functions which we will begin to explore.
This lab will require two days.
Reading: HH Sections 4.01–4.10 (pgs. 175-188)
5.1
Installation
The pin-out designations for a standard 8-pin dual-inline package (DIP) op
amp are shown in Fig. 5.1. When counting pins on a DIP device, always start
by locating the “top” of the package. This can be identified by a semi-circular
indentation, a small circle, or both, as illustrated in Fig. 5.2. The pins are labled
starting in the top left corner and proceeding counter-clockwise, as shown.
Place an LF411 op amp on your breadboard, top up, straddling one of the
central columns. In order to use the op amp, it must be supplied with power.
A good way to set this up is to wire a vertical ‘+’ and ‘-’ column with ±15 V
respectively, and then connnect these power buses to the +VS and −VS pins of
the package. The board power should be off when making this connection. It
is also good practice to filter the power supply connections using a capacitor
to ground, as in Fig. 5.3. This helps maintain a steady voltage if the input
current changes quickly; without it, the inductance of the line from the power
supply can lead to instability. Here, use a 1 µF capacitor, one from the +VS
pin to ground and another from the −VS to ground. These capacitors have a
polarity, with one lead marked by either a + or a − to indicate the appropriate
polarity. Be careful to install the capacitors correctly. Once the chip is installed,
use your DMM to measure the two supply voltages, and record them in your
offset null
inverting
non-inverting
1
8
no connection
2
7
3
6
4
5
out
offset null
Figure 5.1: Pin-out diagram for a
standard 8-pin op-amp package.
Figure 5.2: How to count pins on an
integrated circuit chip.
41
5.2 Open-Loop Test
5 OP AMPS I
1
8
2
7
+
in
3
6
4
out
5
+
Figure 5.3: Connecting power supplies to an op amp.
Figure 5.4: Op amp as an open loop
amplifier.
report. You will need to leave the power connections in place for the remainder
of the exercise.
Note that we will not be using the “offset null” pins today. Leave them
unattached.
5.2
Open-Loop Test
An op-amp is a high gain amplifier with high input impedance. Try to measure
this amplification with the circuit of Fig. 5.4. Note that the input circuit is
a 10 kΩ potentiometer, which allows fine adjustment of the voltage at the op
amp input. Use the pot to set the input voltage close to zero volts value and
measure the resulting output. In principle, this should generate an output
voltage of GVin , with G on the order of 105 . What do you actually observe?
When you change the input voltage, how does the output change? Since there
is no connection from the output back to the input, this is often referred to as
an “open loop” configuration.
To understand these measurements, it is important to distinguish between
the gain and the output range of an amplifier. A functioning amplifier might,
for instance, have a gain of 10, but an output range of only ±1 V. This would
make it a useful amplifier for input signals with amplitudes below 0.1 V, but
a larger input signal would cause the output to saturate, leaving it clamped at
one end of its range. Op amps typically have an output range that is within a
volt or so of the power supply levels. What output range do you measure for
the LF411, and how does it compare to the supply voltages? How small would
the input need to be for the output voltage to fall in the usable range, if the
gain really is 105 ? Does this help explain your circuit’s behavior?
5.3
Inverting Amplifier
Assemble the inverting amplifier circuit of Fig. 5.5. Drive it with a 1 kHz sine
wave. What is the gain (in dB), and how does it compare to the expected value?
Does the gain depend on the signal frequency?
42
5 OP AMPS I
5.4 Non-inverting Amplifier
in
out
in
out
Figure 5.5: Inverting amplifier
Figure 5.6: Non-inverting amplifier
Drive the amplifier with a triangle wave and describe the output. Drive it
with a square wave and note how it responds to a sharp step.
Replace the 10k feedback resistor with a 100k pot, and vary the gain. Can
you take the gain all the way to zero (-∞ dB)? Does the highest gain agree with
what you expect? In order to measure the maximum gain, you will probably
need to turn the input amplitude down to keep the output from saturating. If
you used a bigger pot to keep increasing the feedback resistance even further,
what do you think is the maximum gain you could achieve? Replace the pot
with the 10 kΩ resistor again when you are finished.
You can measure the input impedance of the amplifier circuit by adding
another 1 kΩ resistor in series with the input. The resulting decrease in the
output amplitude can be interpreted as coming from a voltage divider at the
input formed by the new resistor and the original circuit’s input impedance.
What input impedance do you obtain, and does the result make sense?
Verify that the output impedance of the circuit is very low by driving a
10 Ω load resistor. Since the current output of the op-amp is limited, you will
again need to turn the input amplitude down until the output is not clipped. If
the load causes an observable drop in the signal amplitude, you can again use
use voltage divider relation to calculate the output impedance. If there is no
observable drop, all you can say is that the output impedance is small compared
to 10 Ω.
5.4
Non-inverting Amplifier
Assemble the non-inverting amplifier shown in Fig. 5.6. What is the voltage
gain? Replace the 10k resistor with a 10k pot, and observe the range of gains
achievable.
Try to measure the circuit’s input impedance by putting a 1 MΩ resistor
in series with the input and looking for a voltage drop in the output. You
should expect a large value for the impedance. Don’t work too hard at getting
an accurate measurement, because eventually it’s not clear whether the input
impedance will be limited by the op amp or the breadboard.
43
5.5 Follower
5 OP AMPS I
Vin
Vin
10k
10k
Vin
LF411
Vout
10k
1k
10k
LF411
1k
Vout
Vout
1k
1k
(a)
(b)
(c)
Figure 5.7: The follower (a), a pair of voltage dividers (b), and a follower
application (c).
5.5
Follower
One of the most common op-amp circuits is the follower of Fig. 5.7(a). By
applying the op-amp rules, you can readily see that the output of the circuit is
equal to the input: Vout = Vin . It thus functions as a follower, like the transistor
followers you made in the previous lab. Like any follower, the point of this
circuit is to lower the output impedance of a signal, or equivalently to boost the
signal’s current. This is useful if you need to hook a low impedance load up to
a high impedance source.
The op amp follower works better than the transistor followers in most
respects. In contrast to the emitter follower, the input level can be both positive
and negative without encountering problems with biasing, the input impedance
is higher, and there is no base-emitter diode drop between the input and output.
Compared to the FET follower, there is no significant offset due to mismatched
components and the output current capacity is much higher.
For a simple example of using a follower, construct the circuit of Fig. 5.7(b),
where two divide-by-two circuits are naively cascaded, expecting a net output
of Vin /4. Why is the naive calculation incorrect, and what attenuation factor
do you actually measure? In lab 2, you fixed this problem by ensuring that the
second divider used much larger resistors than the first, but a follower can be
used when that solution is impractical. Construct circuit Fig. 5.7(c) and verify
that now the net attenuation is indeed the product of the individual divider
attenuations.
5.6
Summing Amplifier
Another useful trick is shown in Fig. 5.8. This circuit takes two inputs V1 and
V2 and produces the (inverted) sum −(V1 + V2 ). You will analyze this circuit in
44
5 OP AMPS I
5.7 Current Sources
1
out
2
Figure 5.8: Summing amplifier.
your homework. To get some practice with the idea, build a circuit to add the
voltage from your VPS supply to the +5 V fixed supply. How accurately is the
output equal to the negative sum of the inputs? Use a few VPS values of both
signs.
5.7
Current Sources
We usually think of power supplies as voltage sources: a ‘good’ source is one
with a low output impedance, so that it can maintain its voltage regardless
of what load you apply. However, current sources can also be useful. This
describes a supply that produces a constant current, no matter what load you
apply.
The obvious use is in applications that depend specifically on current. For
instance, you might want a good current source to produce a stable magnetic
field from an electromagnet coil. As the coil heats up, its resistance will change,
so a voltage source would not be as desireable. Another common application is
to generate a linear voltage ramp by applying a current source to a capacitor.
Of course, a real current source cannot produce an infinite voltage in response
to an open circuit (= infinite resistance) load. So if you turn on a current source
with no load attached, it will simply ramp up to its maximum possible voltage
and sit there. This is analogous to the fact that a voltage source can’t provide
infinite current to a short circuit (= zero resistance) load; when shorted, a
voltage source ramps up to its maximum current. As a rule, voltage sources
work best with open circuit loads, and current sources work best with short
circuit loads.
An op amp can be used to make a simple current source using the circuit of
Fig. 5.9. Wire this up with R = 1 kΩ, using a 10 kΩ pot as a load and with your
DMM ammeter in series with the pot. You can use the varible power supply to
set Vin ; start at Vin = 1 V. Does the circuit accurately maintain Iload = Vin /R
as you change the pot? What happens if you set Vin = 5 V? Explain what you
observe.
In Fig. 5.9, the load is floating with respect to ground. Unfortunately, loads
45
5.8 Current to Voltage Converter
5 OP AMPS I
in
Figure 5.9: An op-amp current source.
that must be referenced to ground are fairly common. (An oscilloscope is one
example.) You will get to analyze a current source for a load returned to ground
in your homework assignment.
5.8
Current to Voltage Converter
Another function at which op amps excel is converting a current to a voltage.
At first glance, this seems trivial, since that is just the job of a resistor: if you
apply a current I, you get a voltage V = IR. However, if you want a large
‘gain’ (ie, a large voltage for a given current), then you need a large resistor.
This would, of course, have a large input impedance and for a current source,
large load impedances are difficult to handle.
An example where this comes up is the detection of light with a photodiode.
Photodiodes have the property that, under illumination, they produce a current
propotional to the light intensity. The output voltage, however, cannot exceed
more than a few tenths of a volt. So if you try to hook a photodiode up to
a large resistor, the voltage will saturate and the current will be lower than
expected.
Figure 5.10 shows how an op amp can boost the voltage produced without
presenting a large impedance to the photodiode. In fact, since the inverting
input of the op amp is at ground, the photodiode ‘sees’ a short circuit, the
perfect load for a current source. The feedback resistor can be made very large
to produce a large signal. Wire up the circuit using a PNZ335 photodiode,
and use it to observe the room lights. What dc level do you observe? Given
a photocurrent calibration of about 0.5 A/W, how much light power is your
circuit detecting?
It is also intersesting to observe the ac signal structure. Put your scope into
ac coupling mode and zoom in to observe the signal fluctuations. The signal
is complex due to the way fluorescent lights work, but by setting your scope
to line trigger, you should be able to observe a 120 Hz component. What is
the approximate amplitude of this component, and how does that amplitude
compare to the dc level?
Much of the signal variations are at high frequencies and difficult to discern
clearly. You can use the ELVIS Spectrum Analyzer instrument to help. A
46
5 OP AMPS I
5.9 Logarithmic Amplifier
out
in
out
Figure 5.10: Photodiode amplifier.
The photodiode can be oriented either in either direction.
Figure 5.11: Logarithmic amplifier
spectrum analyzer uses Fourier analysis to determine the frequency components
making up a signal. Open it using the ‘DSA’ icon in the ELVIS toolbar. Set the
Frequency Range to 200,000 Hz, and apply your circuit signal to the Scope 0
input of the board. Running the analyzer should show a set of peaks indicating
the components of the light signal. Note the main frequencies in your report.
For reference, the formal name of a current to voltage converter is a transimpedance amplifier. The gain of a transimpedance amplifier is specified in
ohms.
5.9
Logarithmic Amplifier
Recall that the IV curve of a diode has an exponential form. We can use that
to make a logarithmic amplifier, where the output voltage is proportional to
the log of the input voltage. Analyze the circuit of Fig. 5.11 and verify this.
Build the circuit using a 1N914 diode and see how it works, driving it with the
variable dc supply. Note that there are an unknown muliplicative constant and
offset on the output, so you won’t simply observe Vout = log(Vin ). Instead, plot
Vout vs. log(Vin ) and verify that you observe a linear relationship.
In practice, this circuit doesn’t actually perform very well, because the diode
curve becomes non-exponential at large voltages, and also because the output
voltage drifts with temperature. (Try observing this effect by holding your
finger on the diode.) These problems can be fixed using, for example, circuit
4.35 on page 212 of the text. More conveniently, you could simply buy a log
amp integrated circuit, like the LOG104 from Texas Instruments.
How might you make an exponential amplifier, to take the ‘anti-log’ of a
signal? (Again, this is something you’d be better off buying, in practice.)
47
5.9 Logarithmic Amplifier
5 OP AMPS I
48
6
Op Amps II
In the previous lab, you explored several applications of op amps. In this exercise, you will look at some of their limitations. You will also examine the op
amp integrator and differentiator circuits.
This lab will require two days.
Reading: HH Sections 4.11–4.13, 4.19–4.20 (pgs. 189-212, 222–224)
6.1
Output Capacity
The most significant practical limits to what you can do with an op amp derive
from the fact that the output voltage and current are limited. You saw in the
previous exercise that the output voltage is constrained by the supply voltages
driving the op amp, and that the output cannot generally swing all the way
from one supply voltage to the other. In addition, the current that the op amp
can supply is limited. These effects can be observed with the circuit of Fig. 6.1.
For any practical Vin , the output voltage will be clamped at one of its limits.
The voltmeter thus measures how large an output voltage is achievable. As
the potentiometer resistance is lowered, the op amp must supply more current
to maintain its output. Eventually, this causes the output voltage to decline,
necessarily reaching zero when the load resistance is zero.
To test this, construct the circuit using Vin < 0 and measure the output
voltage and output current as the potentiometer is varied across its full range.
Plot the voltage vs. current values in your report. What are the maximum
voltage and current outputs you obtain? Appendix C contains the datasheet
for the LF411 chip. Find the plots it gives for the positive and negative current
limits and compare to your results.
Note that the LF411 is designed to withstand being shorted to ground indefinitely, so you shouldn’t damage anything with this test. Not all amplifiers
in
Figure 6.1: Measuring limits on output voltage and current
49
6.2 Offset Voltage
6 OP AMPS II
in
out
Figure 6.2: 60 dB amplifier.
Figure 6.3: Offset trimming circuit.
have that property, however, so in general you should check before doing an
experiment like this.
Compare the maximum output voltage to the power supply voltage. What is
the difference (in volts) between the two? This range is listed in the data sheet as
the output voltage swing; does your measurement agree with the specification?
Op amps can be designed so that the output swings all the way from one
supply voltage to the other, referred to as ‘rail-to-rail’ design. One important
application is to unipolar operation, where all the signals of interest are positive
and VS- is set to ground. If you tried to do that with an LF411, the op amp
would be unable to produce 0 V out, which would usually be a problem.
If you need more voltage or current than an LF411 can handle, higher power
op amps are available or you can boost the output power using a discrete transistor amplifier.
6.2
Offset Voltage
Ideally, if you present the same voltage to both inputs of an op amp, the output
voltage will be zero. However, a real op amp gives zero output for some small
but nonzero input voltage difference, VOS . To observe this, construct the 1000×
amplifier of Fig. 6.2. If you ground the input, you should observe a non-zero
output, equal to VOS times the amplifier gain. Compare your measured value
to the specification for VOS in the datasheet.
As seen here, the offset voltage is large enough to be significant in a high-gain
circuit. When this is a problem, it can be handled using the offset adjustment
inputs, pins 1 and 5. Fig. 6.3 shows the standard offset trimming network. Wire
this into your circuit and adjust the pot to minimize the output voltage. How
small can you make it?
As handy as this is, VOS unfortunately varies over time and with temperature. You should be able to observe this by warming the chip up with your
finger for a few seconds. Record your observations.
50
6 OP AMPS II
6.3
6.3 Bias Current
Bias Current
An ideal op amp allows no current to enter its inputs. For ac signals, this is
subverted by capacitive coupling between the inputs. However, even at dc, a
small bias current is present. The size of the current depends very much on the
op amp construction. What does the LF411 datasheet specify for its input bias
current? The current can can be observed with the same circuit of Fig. 6.2.
First, convince yourself that with the input grounded, any bias current (on the
V+ input) makes a neglible contribution to the output signal. That’s why we
didn’t need to worry about the bias current while we were measuring VOS .
With the offset voltage nulled as well as possible, attach Vin to ground
through a 1 MΩ resistor. You should be able to see a shift in the output level
when measured with your DMM. You can use the measured shift to determine
the bias current. Is it consistent with the op amp specifications?
6.4
Johnson Noise
If you observe the output voltage from the previous circuit on the oscilloscope,
rather than a DMM, you will notice that it appears quite noisy when the 1 MΩ
resistor is in place. This isn’t a fault of the op amp, but it is a general problem
that arises when you are trying to make a very precise circuit: resistors are
noisy. The effect is known as Johnson noise, and comes from thermal excitation
of the electromagnetic field in the resistor. Consulting a statistical mechanics
text will give you the formula:
p
Vrms = 4kB T R∆f
where kB = 1.38 × 10−23 J/K is Boltzmann’s constant, T is the temperature of
the resistor, R is the resistance, and ∆f is the bandwidth of the noise detector
(in Hz). (If it ever comes up, you should replace R with the real part of the
impedance when you need to find the Johnson noise across a complex network.)
Unfortunately, it is difficult to determine the root-mean square noise amplitude from the signal on your scope, and the bandwidth ∆f is not clear.
However, by replacing the 1 MΩ input resistor
by a 100 kΩ you should see the
√
noise level decrease by about a factor of 10. Include a rough estimate of the
noise level for each resistor in your report.
We can make a better measurement using ELVIS. Open up the spectrum
analyzer instrument, DSA in the toolbar. Make sure the source channel is set
to SCOPE CH 0, and hook your circuit output (with the 1 MΩ resistor on the
input) into the CH 0 input on the side of the ELVIS board. Set the frequency
span to 20 kHz, and the voltage range to ±500 mV. Then run the analyzer. It
will display the noise spectrum, defined as the amount of noise present at each
sampled frequency.
The signal is the rms noise, which is what we need to compare to the Johnson
noise formula. Here the bandwidth ∆f is the frequency range corresponding
to each point displayed. You can determine it by dividing the frequency span
51
6.5 Slew Rate
6 OP AMPS II
Vin
1k
LF411
100
Vout
out
10k
1k
Figure 6.4: Follower for measuring
slew rate
Figure 6.5:
Divider and noninverting amplifier.
by the number of points, here somewhat unfortunately called the “Resolution
(lines).” Use this ∆f to calculate Vrms from the Johnson formula, and compare
to the measured values from the spectrum analyzer observed around the 1 kHz
range. (At lower frequencies, you can be fooled by dc offsets, and at higher
frequencies, the gain of the amplifier is reduced.)
Note that spectrum analyzer gives the noise level in dBVrms , defined as
20 log(Vrms /1 V). Here the 1 V appears as a sort of normalization constant
specifying what 0 dBVrms means. Also, don’t forget that the spectrum analyzer
signal has been amplified by your circuit.
6.5
Slew Rate
Another important limitation of real op amps is that they can only respond at
a finite speed. One reflection of this is the op amp’s slew rate, which measures
the rate dV /dt at which the output voltage can change, typically in V/µs.
Measure the slew rate with a simple follower, Fig. 6.4. For a square wave
input, the output should ideally change abrubtly, but it will in fact exhibit a
finite dV /dt. Measure the slew rate at drive amplitudes of 2 Vpp and 10 Vpp.
Compare your results to the slew rate specification from the datasheet.
6.6
Frequency Response
The slew rate is one limit on an op amp’s frequency response, but it is mostly
important for large-amplitude output signals. Even for small signals, the op
amp can only respond at finite speed, which leads to phase delays and reduced
gain at high frequencies. This behavior can be quantified using the Bode plots
we introduced in Lab 2.
Unfortunately, the ELVIS Bode instrument is too slow for what we want to
see, so you will need to take the data by hand. Set up the non-inverting amplifier
52
6 OP AMPS II
6.7 Integrator
shown in Fig. 6.5. Note the divider on the input, which makes it easier to get a
sufficiently small drive signal. Set the function generator amplitude to 1 Vpp,
and monitor Vin and Vout on your scope. Measure the gain and phase shift
from 50 Hz to 5 MHz. You can take steps of a factor of 10 in regions where
the phase is approximately constant, but use factors of 2-3 where something
interesting is occuring. Note that you can increase the input amplitude at the
higher frequencies, but make sure to keep the output amplitude below 1 V or
so. Also, you will need to be careful to keep the traces centered on the scope;
the dc level may shift at high frequencies due to nonlinear effects. (Using the
scope’s ac coupling feature might be useful here.)
Plot your data (both gain in dB and phase in degrees vs. log f ) in your
report. The unity gain point is defined as the frequency where the op amp
gain drops to 0 dB. Find this point and compare to the op-amp specification,
referred to in the datasheet as the gain-bandwidth product. The bandwidth of
the amplifier circuit can be defined as the frequency where the gain drops by 3
dB below its dc value, G. What bandwidth do you observe here? How does it
compare to the prediction that the bandwidth is equal to the unity gain point
divided by G?
Now replace the 10k feedback resistor by a 33k resistor, making it a nominal
34× amplifier. To compensate, turn the function generator amplitude down so
that the output doesn’t clip. Measure the gain and phase over the same range as
before. Add the data to the same Bode plots as the 11× circuit for comparison.
What is the bandwidth now, and does it agree with what you expect? How do
the two circuits’ gains compare at high frequencies?
6.7
Integrator
Construct the integrator circuit of Fig. 6.6(a), using R = 100 kΩ and C = 10 nF.
Ideally, it produces an output
Z
1
Vout = −
Vin (t)dt.
RC
Test it using a 500 Hz square wave from your function generator, but get everything set up before you turn the circuit power on. Make sure your scope is
set to dc input coupling. Describe what happens when you do apply power.
You should see the output level ramp up or down until it reaches the op amp
output limit. This is expected
R t to occur in response to a dc input: the output
should increases linearly as 0 Vdc dt = Vdc t. In practice, there is always some dc
offset present, due to either the function generator or the op amp’s own offset
value from section 6.2. The integrator is therefore doing what it is supposed to,
but the drift makes it hard to look at the ac waveform that we are interested in.
Try to adjust the dc offset on the function generator to keep the output signal
near zero. Is it possible?
Instead of trying to eliminate the dc input, a better fix is to reduce the
dc gain. This can be achieved by putting a large resistor in parallel with the
53
6.8 Differentiator
6 OP AMPS II
R2
C
R
R1
Vin
C
Vin
Vout
Vout
(a)
(b)
Figure 6.6: (a) Integrator. (b) Practical integrator with ‘rolloff’ resistor R2 .
capacitor, as in Fig 6.6(b). Try R2 = 1 MΩ resistor. What then is the dc gain?
For frequencies ω large compared to 1/R2 C, the impedance of the resistor will
be large compared to that of the capacitor, so the resistor can be neglected and
the behavior of circuit (a) established. What is that frequency here? Observe
the circuit output for a range of square wave frequencies, and describe your
results. Above what frequency do you see proper integrator behavior?
With a sufficiently high frequency, observe the output produced for triangle
wave and sine wave inputs. Do they agree with your qualitative expectations?
To be quantitative, apply a 500 Hz square wave with a 2 Vpp amplitude. Using the integrator formula above, calculate what the amplitude of the output
triangle wave should be. Does it agree with your observation?
To get a complete characterization of the circuit’s transfer function, use the
ELVIS tool to obtain the Bode plot over a frequency range from 1 Hz to 10 kHz.
To make the phase easier to interpret, change the Op Amp Polarity setting to
Inverted (since the circuit produces the negative integral of the input.) Also,
make sure that the input amplitude is set low enough: think about what the
maximum gain of the amplifier will be, and make sure the output won’t exceed
the supply voltages at that point.
Now take three more Bode plots, under the following conditions:
(a) with C decreased to 1 nF
(b) with R1 increased to 1 MΩ
(c) with R2 decreased to 100 kΩ
(Only make the one change each time; for instance, in (b) and (c), use a 10 nF
capacitor.) Overlay all four plots in Excel, plotting the data with lines to make
it legible. Confirm that in each case, the dc gain is given by R2 /R1 and that
the transition to integrator behavior, G ∝ 1/f , occurs at f ≈ 1/2πR2 C.
6.8
Differentiator
An ideal differentiator circuit is shown in Fig. 6.7(a), implementing
Vout = −RC
54
dVin
.
dt
6 OP AMPS II
6.8 Differentiator
100 pF
R
C
Vin
1k
LF411
10 nF
100k
Vin
Vout
LF411
Vout
Figure 6.7: (a) Ideal and (b) practical differentiator circuits.
Unfortunately, the circuit as shown is unstable. Nominally, the gain increases at
high frequencies, but the since the op-amp can only respond at a finite speed, it
will eventually fail. The practical differentiator circuit is shown in Fig. 6.7(b).
Here the extra components serve to roll off the gain at high frequencies. Given
the component values shown, at what frequency should this circuit stop acting
like a differentiator?
Construct the circuit, and drive it with a 500 Hz triangle wave with 2 Vpp
amplitude. Does the amplitude of the square wave output agree with what
you calculate? Do the results for square wave and triangle wave inputs agree
qualitatively with what you expect?
Use ELVIS to measure the Bode plot for the differentiator, from 100 Hz to
100 kHz. Again, set the op amp polarity to be negative, and again think about
what input voltage to use: Determine what frequency will have the largest gain
and make sure that the drive level is low enough that the circuit will not clip at
that frequency. You can check that the amplitude is low enough by decreasing
it further and verifying that the transfer function doesn’t change. Plot the data
in your report. Does the high frequency roll-off appear where you expect? Does
the gain cross zero dB where you expect, based on the differentiator formula?
55
6.8 Differentiator
6 OP AMPS II
56
7
Feedback and Control
An important application of analog electronics, particularly in physics research,
is the servomechanical control system. Here the concept of feedback is generalized and used to control almost any physical variable. We shall spend this and
the next lab constructing and studying a servo for a simple system consisting
of an LED and a photodiode. The concepts, however, are universal and apply
to any servo you may need.
This lab will require two days.
7.1
LED Driver
This exercise will work toward the construction of the circuit in Fig. 7.7. This
is considerably more complex than anything we’ve done up to now, so we will
build it up gradually. However, plan from the start for what you are doing:
think about where you will place the op-amps on your circuit board, and how
you will get power to them all. Use short wires where you can, to reduce circuit
clutter. Lay out each sub-circuit in a clear and logical way. We will be working
with this circuit for the next lab as well, so keep good notes about how the
components are laid out and what each sub-circuit does. The next lab will
require adding two more op amps to the circuit, so leave enough room for them.
The starting point is the sub-circuit of Fig. 7.1, which applies a current to
a light-emitting diode (LED) proportional to an input voltage. An LED is an
ordinary diode that is optimized and packaged to produce light in response to a
forward current, effectively the opposite of a photodiode. By using an op-amp
current source, we ensure a linear response to the control voltage.
Wire up the circuit using a “standard red” LED. Note that one of the leads
is longer than the other: the longer lead is the anode, which requires the more
positive voltage. (You can also check which lead is which using your DMM
in
Figure 7.1: LED driver circuit.
57
7.2 Photodiode
7 FEEDBACK AND CONTROL
cathode
out
anode
anode
Figure 7.2: Photodiode detection
circuit. The heavy lines indicate
where accessible wires should be
used.
cathode
Figure 7.3: Identifying the polarity
of the PNZ335 photodiode.
diode tester.) Drive the circuit with your variable power supply and verify that
you can adjust the brightness of the light by varying Vin .
7.2
Photodiode
Now that we have a light source, we will build a servomechanism to control
it. The first step in that process to measure the light level, which we will do
with the circuit of Fig. 7.2. In real life, we would probably use a lens to collect
light from the LED and focus it onto the photodiode, but for our purposes,
it is sufficient to place the components next to each other and then bend the
leads of the LED so that its top is aimed right into the sensing surface of the
photodiode.
Notice that the 20 pF capacitor on the op-amp feedback forms a low pass
filter with a cutoff frequency of about 8 kHz. This simplifies the high-frequency
response of the system and makes the servo easier to implement.
Also note that the orientation of the photodiode is significant. Only the
side with the darker surface is sensitive to light. The pin layout is described
in Fig. 7.3, along with the direction of the photocurrent. For now, orient the
photodiode so that the circuit output is positive, but you may need to change
the polarity later on. Flipping around the photodiode itself would require you
to move the LED to keep the correct surface illuminated; instead make sure that
the wires connected to the photodiode leads are accessible so you can reverse
them, as illustrated in Fig. 7.2.
Apply the VPS controller to illuminate the LED. Measure the photodiode
output as a function of the input voltage, and plot the relation in your report.
Over what range of inputs is the response linear? The proportionality constant
should be roughly one, within a factor of two or so.
58
7 FEEDBACK AND CONTROL
7.3 Summing Amplifier and Set Point
FGen
10k
10k
1N746A
(3.3 V)
2k
From photodiode
op amp
10k
10k
Verr
VPS
10k
10k
to LED driver
10k
-15 V
(a)
(b)
Figure 7.4: (a) Summing amplifier. (b) Set point subtraction.
7.3
Summing Amplifier and Set Point
We will drive the LED sub-circuit with the summing amplifier of Fig. 7.4(a).
This provides a constant dc bias using the zener diode, to which can be added
the function generator signal and other signals as needed.
Construct the sub-circuit and verify that the output provides an ac signal
added to an approximately 3 V dc level, as desired. Hook the output of the
summer up to the input of the LED driver. Drive the circuit with your function
generator at a frequency of 1 kHz and amplitude of 1 Vpp. The photodiode
output should show a response with comparable amplitude; note the value in
your report. Of course, the summing amplifier inverts the signal; that is why
the zener diode is arranged to give a negative voltage reference. In terms of the
phase response, this introduces a 180◦ shift.
The dc component of the photodiode output indicates the average light
level. The servo system will attempt to regulate this level at a desired set point.
We will use the VPS supply to establish this set point, through the circuit of
Fig. 7.4(b). Construct this circuit, and set the VPS voltage to within 0.5 V of
the the signal produced by the photodiode amplifier, which should be in the 3–
5 V range. The circuit’s ouput is given by VVPS − Vphotodiode , and thus indicates
the deviation of the light level from the set point. We therefore call the output
the error signal Verr . For now, the magnitude of the error signal should be less
than 0.5 V, but it will vary as the light level on the photodiode changes.
Rather than attempting to vary the ambient light level in a controllable
way, we will use the function generator as an effective noise source. Ideally, the
control circuit will counteract the function generator signal, so that the error
signal remains fixed even when the generator is applied.
59
7.4 System Response
7.4
7 FEEDBACK AND CONTROL
System Response
In order to design the servo system, we need to know the frequency response of
the driver-detector combination, defined through
Vout = G0 (ω)Vin
where here Vin is the function generator signal driving the LED, and Vout is the
error signal produced after subtracting the set point. Here G0 is termed the
open-loop transfer function, since we have not yet “closed” the feedback loop.
We can measure G0 using the Bode analyzer tool. Hook the circuit input
up to the ELVIS Scope 0 connector and the error signal up to ELVIS Scope
1, while leaving the function generator also attached to the circuit input. Use
an input amplitude of 1 Vpp, a frequency range from 10 Hz to 200 kHz, and 5
points per division. Choose the polarity setting so that the phase is close to 0◦
at low frequencies. Copy the data (for both phase and gain) into your report
and plot it. Explain the features you observe. (It is possible that the phase
measurement will fall below -180◦ , in which case the analyzer wraps the phase
around to near +180◦ . Your plots will be easier to interpret if you ‘unwrap’ the
phase in Excel by subtracting 360◦ from the appropriate points.)
In fact, the frequency limit on the Bode tool is a little lower than we would
like, and the highest frequency points are sometimes inaccurate. To rectify this,
take a few higher frequency points by hand, using the function generator and
your scope. Obtain the gain and phase at 100 kHz, 200 kHz, 500 kHz and
1 MHz. Add the values to the Bode plot you already have. Note that if you
were using the inverting polarity setting on the Bode tool, you should invert
the signal on the scope to get a consistent phase value.
A sample plot showing the type of data you should expect is provided in
Fig. 7.5. Your data may vary from this in detail, but the general features
should be correct.
7.5
Feedback
If you wave your hand above the photodiode, it should be easy to see how the
error signal is affected by the room lights. Use your oscilliscope to estimate the
signal variation produced by alternately covering and uncovering the photodiode
with your hand, and note the value in your report. We suppose that this is a
problem... perhaps we have an experiment at the location of the photodiode
that requires constant illumination. The idea of the servomechanism is to feed
back the photodiode signal to the LED driver in such a way as to compensate
for the noise. If the room lights get brighter, the LED would get dimmer, and
vice versa. The system for doing so is shown schematically in Fig. 7.6(a). We
have already built and characterized the system function G0 . We shall now set
up the feedback H.
The feedback circuit we shall use is shown in Fig. 7.6(b). Construct this subcircuit, and set the 100 kΩ pot to 0 Ω corresponding to zero feedback amplitude.
60
7 FEEDBACK AND CONTROL
7.5 Feedback
5
Magnitude G (dB)
0
-5
-10
-15
-20
-25
-30
Open loop
-35
Closed Loop
-40
-45
10
100
1000
10000
100000
1000000
Freq (Hz)
60
Phase G (deg)
0
-60
-120
-180
Open loop
-240
Closed loop
-300
-360
10
100
1000
10000
100000
1000000
Freq (Hz)
Figure 7.5: Sample data for open and closed loop transfer functions.
G0
LED
Verr
Photodiode
Vset
H
(a)
100k
1k
Verr
10k
To summing
amplifier
(b)
Figure 7.6: Feedback loop for LED servo. (a) Block diagram. (b) Sub-circuit.
61
7.6 Servo Performance
7 FEEDBACK AND CONTROL
Attach the feedback to the main circuit as in Fig. 7.7. Before turning everything
on, however, consider the polarity of the feedback. We require the feedback to
be negative: if the room light level increases, the circuit should reduce the LED
current to compensate. The actual sign of the feedback depends on whether
it passes through an even or odd number of inverting amplifiers in the loop,
and also on the polarity of the photodiode itself. Examine Fig. 7.7 and try to
determine which photodiode polarity is required. (The polarity shown in the
diagram may or may not be correct.)
Set the photodiode polarity as you think is necessary, and then turn on the
circuit and monitor the error signal on your oscilloscope as you gradually turn
up the feedback resistor. The effect may be clearer if you use the function
generator to drive the circuit with a 1 kHz, 1 Vpp sine wave. (Recall that that
the set point should be adjusted so that the dc level of the error signal is near
zero.) If everything is working correctly, the error signal should move toward
zero and the noise in it should be reduced as the feedback gain is increased. The
noise should continue decreasing to a minimum level, but when you increase the
gain further, the error signal will start to oscillate at a high frequency.
If the error signal grows as soon as the feedback is increased, then you probably have the photodiode polarity wrong, and you should swap the photodiode
wires. Whichever orientation you started with, do reverse the photodiode leads
and observe the other orientation as well. Note that when you reverse the photodiode, you will also need to change the sign of the set-point voltage to re-zero
the uncontrolled error. Record which diode orientation is correct, and describe
what you observe in both cases.
With the function generator turned off, increase the gain resistor until the
circuit just oscillates and measure the resulting oscillation frequency. Then take
out the potentiometer and measure the corresponding resistance value. Replace
the pot and reset the resistance to a point where the stabilization is good, which
should be slightly below the point where oscillation occurs. Again measure and
record the corresponding resistance. Replace the pot at this same setting, and
do not change it again for the remainder of the exercise.
7.6
Servo Performance
Once you get the servo working, you can characterize how well it works. To
start, measure the variation in error signal caused by covering the photodiode
with your hand. How does it compare to what you saw with no feedback?
To be more quantitative, you can measure how well the servo attenuates
noise at a given frequency. Here we will use the simulated noise generated by
the function generator as as shown in Fig. 7.7. You have previously measured
the open-loop system response G0 , with no feedback. Now measure the closedloop response, Gc , with the feedback signal in place. The transfer function is
the ratio of the error signal to the function generator input, just as before. Use
the Bode tool to measure the response from 10 Hz to 200 kHz, and take points
from 100 kHz to 1 MHz by hand. Load the data into Excel and plot it on
62
7 FEEDBACK AND CONTROL
7.7 Servo Analysis
the same graph as G0 . The difference between these curves shows the amount
of noise reduction that the servo provides. Sample curves showing what you
should expect can be seen in Fig. 7.5.
As the figure shows, at some frequencies the noise is actually higher for the
closed-loop curve. This is called noise peaking, and occurs when the servo is
at the edge of its stability. (Or equivalently, when G0 H is close to -1 at some
frequency.) How does the frequency of the noise peak compare to the oscillation
frequency you measured in the previous section when the feedback gain was too
high?
7.7
Servo Analysis
We can compare the servo performance to what we expect. For the openloop transfer function G0 and feedback transfer function H, theory predicts the
closed-loop transfer function to be
Gc =
G0
.
1 + G0 H
You have measured G0 already, so now measure H for the circuit of Fig. 7.6(b):
Without changing the potentiometer setting, replace the input from the error
signal with the signal from the function generator, and monitor the output of
the feedback amplifier with the Bode analyzer. Set the input amplitude in the
analyzer tool to be 0.3 V so the op amp doesn’t saturate. Measure the response
from 10 Hz to 1 MHz as before, and plot the data in your your report. Again,
make sure the polarity setting is such that the phase is zero at low frequencies.
Using this and your earlier data, calculate the theoretical response G0 /(1 +
G0 H). To compare to Gc , you will need to obtain both the magnitude and
phase of this quantity. This involves some complex algebra that you will get
to work through in your next homework assignment. For now, however, you
can simply use these results: If G0 = geiφG and H = heiφH , define z = gh and
φz = φG + φH . We then obtain
G0 g
1 + G0 H = p1 + 2z cos φ + z 2
z
and
arg
G0
1 + G0 H
= φG − tan
−1
z sin φz
1 + z cos φz
.
(Recall that arg(q) is the phase of a complex number q.) Here g and h will need
to be expressed as dimensionless (×) gains, not in dB, and Excel wants φz in
radians. Calculate this magnitude and phase, and add them to your plots of
Gc . You should see that the two curves agree reasonably well, though probably
not perfectly.
Conventionally z = |G0 H| is defined as the loop gain and φz = arg(G0 H)
as the loop phase. From your data, estimate the frequency at which the loop
63
7.7 Servo Analysis
7 FEEDBACK AND CONTROL
phase reaches -180◦ . What is the loop gain at that frequency? The gain should
be a bit below zero dB, and the frequency should be slightly higher than where
you observed noise peaking and oscillation. This is because instability occurs
when the phase is -180◦ at unity gain, and by turning the feedback gain up to
nearly the point of oscillation, you put the circuit near the point of instability.
The phase margin of a servo is defined as the difference between the loop phase
and -180◦ at the frequency where the loop gain reaches 0 dB. What is the
phase margin for your circuit? Does the loop phase come primarily from the
LED/photodiode subcircuit, or from the feedback amplifier?
In the next lab, we will attempt to improve this circuit by using more sophisticated feedback schemes. Hook the feedback amplifier back up and readjust
your circuit to again provide stabilization, leaving the circuit set up.
"Noise" input
10k
10k
1N746A
10k
2k
-15 V
LED controller
10k
Summing
Amplifier
330
20 pF
10k
Set point
subtraction
1M
10k
Verr
VPS
Photodiode
amplifier
10k
10k
100k
1k
Feedback amlifier
Figure 7.7: Complete servo circuit. All op amps are LF411s.
64
8
Feedback and Control II
In the previous lab, you constructed a circuit to stabilize the light level at a
photodiode. We now return to the same circuit and develop more effective ways
to implement the servo control, working up to the full PID control mechanism.
We also explore the transient response of a servo stabilized system.
This lab will require two days.
8.1
Proportional Control
Figure 7.7 shows the circuit you should still have from the previous lab. Here
the control signal is implemented by multiplying the error signal by a constant,
so this type of system is called ‘proportional control’.
For reference, we will repeat a few measurements from the previous lab.
First, unhook the feedback signal from the summing amplifier so that the circuit
is uncontrolled. Use the Bode tool to measure the open-loop transfer function
from the “noise” input to the error signal. Use a frequency range of 100 Hz to
200 kHz. If the response is lower than what you observed in the previous lab,
you may need to adjust the alignment of the LED and photodiode. When you
have a satisfactory curve, save the data in your report. As before, we will refer
to this function as G0 .
Now reattach the control signal and set the proportional gain to just below
the point where the circuit oscillates. Again measure the transfer function
for the error signal and import it to your report. Also record the oscillation
frequency you observe when the gain is too high. Define the period of those
oscillations to be TP , which we will use again later.
After setting the potentiometer to its maximum stable value, take it out and
measure the resistance. Define the corresponding amplifier gain R2 /R1 as HP ,
and note this in your report as well. Then reduce the gain value by a factor of
two and replace the pot in your circuit. Measure the error response again, and
plot both closed-loop curves together in your report. Explain the differences
between the responses with maximum gain and with half-maximum gain.
8.2
Integral Control
Although the proportional gain circuit does reduce the sensitivity of the circuit
to errors, it doesn’t do as good a job as it might. At low frequencies, you should
see about a factor of 10 noise reduction, but it should still be easy to observe,
for instance, the effect of moving your hand around over the photodiode.
The performance can be significantly improved using integral control, where
the control signal consists of the time integral of the error signal, rather than
65
8.3 PI Control
8 FEEDBACK AND CONTROL II
CI
RI
Verr
10k
To V- terminal of
summing amplifier
Figure 8.1: Sub-circuit for implementing integral control. See also Fig. 8.3.
the error signal itself. Add integral control to your system using the circuit of
Fig. 8.1. The output of this circuit is
Z
1
Verr dt,
RI CI
so the choice of τI = RI CI sets the effective gain of the circuit.
An appropriate value for τI can be estimated from the open-loop response
curve G0 that you took in Section 8.1. Use your data to estimate the frequency
f90 at which φG reaches -90◦ and also estimate the magnitude |G0 | at that
frequency. Then choose τI so that |HI (f90 )| = 1/(2πf90 τI ) is about equal to
1/|G0 (f90 )|. Note that you need the numerical gain values, not in dB, here.
You will want to be able to reduce the gain well below this value, so select a
capacitor and a potentiometer combination such that when the potentiometer
is at its maximum value, the time constant is around ten times larger than the
above estimate. Make sure to note the values you choose in your report. Add the
integral stage to your circuit. Start out with the potentiometer at its maximum
value, and thus at the minimum gain. For now, unhook the proportional control
signal from the summing amplifier.
Power up the circuit, and gradually increase the integral gain. As with the
proportional control, you should see the error signal stabilize and then eventually
start to oscillate. Now, however, the stabilization should appear much more
effective in response to, for instance, waving your hand above the photodiode.
With the integral gain set just below the oscillation point, measure the transfer
function and plot it in your report. Measure the potentiometer resistance and
report that as well.
Note that Fig. 8.1 does not include a roll-off resistor to limit the gain at low
frequencies. Why doesn’t the output of the op amp eventually increase until
it rails, as we have seen before? To answer this, think about how your circuit
would respond if the integrator’s output did start to increase.
8.3
PI Control
Often, the control signal consists of a proportional term and an integral term
added together. This is usually referred to as PI control.
Reattach the proportional control signal, with the proportional gain still set
to half its maximum value. (This is usually a reasonable starting point for a PI
66
8 FEEDBACK AND CONTROL II
8.4 PID Control
system.) If the system isn’t stable, turn down the integral gain a bit. Use the
Bode analyzer to measure the combined PI transfer function. How is it improved
compared to integral feedback alone? Try adjusting the two gains together to
achieve the minimum possible noise response: While repeatedly running the
analyzer, adjust the potentiometers to give the lowest possible closed-loop gain
values. What trade-offs do you observe in trying to make this optimization?
When you have settled on your best response, plot it in your report. Measure
both gain resistor values and report them as well.
8.4
PID Control
The noise response can sometimes be improved further yet by adding a third
term to the control signal that is proportional to dVerr /dt. This is achieved with
the circuit of Fig. 8.2, which provides an output of
dVerr
.
dt
The required τD = RD CD time constant can be estimated as HP TP /8, where HP
is the maximum proportional gain value and TP is the oscillation period from
Section 8.1. Use them to select a suitable combination of capacitor and pot, and
note them in your report. Note that the capacitor you choose should not be too
large: to avoid loading the output of the previous op amp, the input impedance
of the derivative amplifier should remain above 100 Ω or so for frequencies up
to 100 kHz.
Construct the derivative circuit, leaving the previous PI components in place.
Again starting out with the RD resistor turned all the way down to provide minimum gain. Power on the circuit and gradually turn up the derivative gain until
the system oscillates. Note in your report the resistor value at which this occurs.
Reduce the gain a bit from there and measure the transfer function. Compare
to what you achieved with PI control. Do you observe any improvement? Often
it is beneficial to decrease the proportional gain when adding derivative control.
Try that, and try adjusting all three gains to optimize the response. Plot your
best response curve in your report, and note all of the resistor values used.
You may or may not get much improvement. In many systems, the benefits
of derivative control are limited by the high frequency characteristics of the
open-loop response, and PI control does as good a job as possible.
RD CD
RD
CD
Verr
10k
To V- terminal of
summing amplifier
Figure 8.2: Sub-circuit for implementing derivative control. See also Fig. 8.3.
67
8.4 PID Control
8 FEEDBACK AND CONTROL II
"Noise" input
10k
10k
1N746A
10k
LED controller
2k
Summing
Amplifier
-15 V
330
20 pF
10k
Set point
subtraction
1M
Control
Signal
10k
Verr
VPS
Photodiode
amplifier
10k
10k
100k
Proportional
1k
10k
CI
RI
Integral
10k
RD
Derivative
CD
10k
Figure 8.3: Complete circuit including PID control.
68
8 FEEDBACK AND CONTROL II
8.5 Transient Response
At this point, your circuit should appear as in Fig. 8.3. Your report should
contain four Bode plots (of gain and phase vs. frequency): (1) the open loop
response from Section 8.1, (2) a plot showing the response with proportional
control at both the maximum and half-maximum levels, (3) a plot showing integral control, PI control with the initial resistor values, and PI control with the
optimum values, and (4) a plot showing PID control with the optimum values.
For each case, you should also have the corresponding gain resistor values. Put
together one final plot for comparison, showing the optimum responses for each
of the P, PI, and PID control mechanisms, along with the open-loop response
for reference.
8.5
Transient Response
Up to now, we have focused primarily on the frequency response of the system.
It can also be useful to observe the transient response to a sudden step. In
practice, this is usually important when the set point of the servo is being
changed rapidly.
To observe the step response, we will modify the circuit to use the function
generator rather than the VPS supply to establish the set point for the servo,
as seen in Fig. 8.4. The function generator should also be removed from the
‘noise’ input of Fig. 8.3. Set the dc offset of the function generator to equal
the previous set point (which should be close to the open-loop voltage produced
by the photodiode amplifier). This makes the upward and downward steps
symmetrical about the previous set point. Set the function generator signal to
a 2 kHz square wave with a 1 Vpp amplitude.
Monitor both the function generator and the output of the photodiode amplifier on your oscilloscope; the photodiode signal shows the transient response
more clearly than the error signal does. You should see that as the set point
changes, the photodiode response follows, perhaps with some delay and/or oscillation. These delays and oscillations are what we will be measuring.
To start, unhook the integral and differential control, and use the propor-
20 pF
10k
1M
10k
Verr
FGEN
Photodiode
amplifier
10k
Scope Ch 1
10k
Scope Ch 2
Figure 8.4: Modifications to circuit for measuring transient response
69
8.5 Transient Response
8 FEEDBACK AND CONTROL II
t settle
105%
95%
90%
t rise
10%
0%
Figure 8.5: Definition of rise time and settling time. The dashed line indicates
the function generator signal
tional control only. Observe the behavior as you vary the gain resistor, and note
in your report what you see for high (but still stable), low, and intermediate
gain values. At high gain values, what oscillation frequency do you observe?
Compare it to the oscillation frequency of Section 8.1.
To be quantitative, we can characterize the response with two parameters,
illustrated in Fig. 8.5. The rise time is the time required for the photodiode
signal to rise from 10% to 90% of its total change. The settling time is the time
required for the signal to settle to within 5% of its final value, measured from
when the function generator changes. For example, if the photodiode signal is
changing from 1 V to 2 V, the rise time would be the time need to rise from
1.1 V to 1.9 V (counting just the first time it reaches 1.9 V, if it is oscillating.)
The settling time would be the delay between when the function generator rises
to the time when the photodiode signal has settled to within a range of 1.95 to
2.05 V.
Accurately measuring the rise time and settling time on the scope can difficult. To help, you can use the Delay feature of the scope to zoom in on the
transition. Start with the scope showing both the function generator and photodiode signals with a reasonable feedback gain value. Switch both channels
to ac coupling, and trigger on the photodiode signal. Now locate the button
labelled ‘B’, just below the Variables knob. Press it, and the scope switches to
a zoomed in section of the trace with a variable delay after the trigger. (The
normal display can be restored by pressing the ‘A’ button.) The values of the
time/division and the delay are displayed on the screen. Adjust the delay value
using the Variables knob until it is about half a period of the square wave. The
scope should then display a transition, specifically the next transition after the
one you are triggering on. This lets you see the transition in both signals clearly.
You can use the cursors to measure the rise time and settling time, but it is
70
8 FEEDBACK AND CONTROL II
8.5 Transient Response
still a little difficult because you can’t see both the horizontal and vertical cursors at once. You can use the fixed division grid on the scope screen to provide
a reference point, or you can obtain an erasable marker from the instructor that
you can use to draw on the screen.
Once you have a measurement technique established, measure the rise time
and settling time for gain resistor values near to Rmax , Rmax /2, and Rmax /4,
where Rmax is the largest value that maintains the circuit’s stability. Ideally,
the upward and downward transitions would be symmetric, but they probably
are not here due to nonlinearities in the LED and photodiode. For simplicity,
only measure the transient response for the upward transitions.
Next, unhook the proportional gain and run the circuit with integral gain
only. Set the gain to a large but stable value. You should find that the settling
time is much longer, so you may need to use a lower drive frequency in order
to observe the complete response. You only need to observe the maximum gain
response here.
Finally, look at the PI and PID control schemes. For each, set the gain
resistors to the optimum values you found with the Bode plots in the previous
sections, and measure the response times at those values. For the PID circuit,
try adjusting the gains to minimize the rise time and settling time. You may
find the derivative control has a little more impact in this type of measurement
than was apparent in the Bode plots. In the PID system, can you qualitatively
describe the effect of each control component?
This completes our study of control systems, so you can disassemble this
circuit when you are done.
71
8.5 Transient Response
8 FEEDBACK AND CONTROL II
72
9
Logic Gates
The next few labs will deal with digital logic, a central topic in modern electronics work. This first lab introduces the basic logic gates and the different
logic families.
This lab will require two days.
Reading: HH sections 8.01–8.12, 8.20–8.22 (pgs. 471–492, 517–521)
9.1
Transistor Gates
Consider the circuit shown in Fig. 9.1(a). Here the transistors are being used
only in their saturated and off states, not in their ‘active’ mode where IC = βIB .
Recall that when the base current IB is zero, the collector current IC is also zero,
while if the base current is large, there is a large IC , limited by the transistor’s
saturation voltage VCES . In reference to the figure, if either signal A or signal
B is low, the series collector current will be zero and the output signal Q will
therefore be high (about Vcc ). If both A and B are high, then a large collector
current will flow and Q will be low. This circuit should therefore implement the
NAND gate: the output is true (= high) if and only if (A AND B) is false. Its
truth table can be written as:
A B Q
H H L
L H H
H L H
L L H
where ‘H’ stands for high and ‘L’ for low.
Construct the circuit on your breadboard, using Vcc = 5 V. Note that most
of the logic functions of the ELVIS board are located on the right-hand side,
including a hookup to the 5 V supply and ground. To start, use either the
supply (H) or ground (L) for the inputs and measure the output voltage with
your DMM. Record the output voltage for each combination of inputs in your
report. Is it consistent with the NAND truth table given above? What output
values does it give for “L” and “H”?
In digital circuits, we don’t normally care about the actual voltage level,
so the DMM provides more information than necessary. ELVIS has a Digital
Reader and a Digital Writer tool that will be more convenient. The pin connections are the DIO pins located on the upper right corner of the board. Change
your circuit to take the A input from the DIO 0 connector and the B input
from DIO 1. Connect the output Q to DIO 8.
73
9.1 Transistor Gates
9 LOGIC GATES
Vcc
Vcc
470
470
Q
470
Q
A
A
470
B
470
B
(a)
470
(b)
Figure 9.1: (a) Transistor implementation of a NAND gate. (b) What gate is
this? All transistors are 2N3904. If you’ve forgotten the pin designations, check
Lab 4 or look them up on line.
Start up the DigIn (Reader) and DigOut (Writer) tools. In the Writer, set
the Lines to Write to 0-7, and in the Reader, set Lines to Read to 8-15 and then
run the tools. The HI/LO buttons in the Writer set the output levels, and the
lights on the Reader indicate the input levels. Check the truth table again and
verify that it agrees with your previous result.
Unhook one of the inputs. Does the ‘floating’ input act like an H signal or
like an L signal?
Rewire your circuit to the configuration of Fig. 9.1(b), again using the DIO
signals for the inputs and outputs. Measure the truth table. Does it agree with
your expectations? What logic function does this circuit implement?
Once you are done with this section, disassemble your circuit and return the
parts to the supply cabinet.
1
14
2
13
3
12
4
7400
1A
1B
1Q
2A
2B
2Q
GND
11
5
10
6
9
7
8
Vcc
4B
4A
4Q
3B
3A
3Q
A
Q
B
Figure 9.2: The 7400 quad NAND gate.
74
9 LOGIC GATES
9.2 Integrated Gates
A
5V
Q
5V
A
A
Q
B
Q
5V
B
NOT
5V
AND
OR
Figure 9.3: Circuits to produce NOT, AND, and OR gates using NAND gates.
9.2
Integrated Gates
You would not normally want to construct a logic gate from transistors, since
integrated circuit chips are available which perform better. Four NAND gates
are available in the 7400 chip, shown in Fig. 9.2. Each set of numbered pins
(1A, 1B, 1Q) refers to an independent gate.
The 7400 series comes in several variants, including the 7400 proper, the
74LS00, the 74HC00, and the 74HCT00. These all have somewhat different
performance characteristics, but the same pin designations. For now, obtain
a 7400 chip from the supply cabinet. Wire up the chip with Vcc = 5 V on
pin 14 and attach pin 7 to ground. Pick one of the gates and wire the inputs
and output to the DIO connectors as before. Measure and record the truth
table, and verify that it is indeed a NAND gate. Unhook one of the inputs and
determine how a floating input is evaluated.
It turns out that the NAND gate is universal, meaning that NAND gates
can be combined to produce any other logic gate. Figure 9.3 shows how to
implement NOT, AND and OR gates. Using the gates on your 7400 chip,
construct each of these gates and check its truth table. List your results in your
report.
9.3
Logic Levels
Ordinarily, you don’t need to worry about what voltages a logic chip uses for
its high and low states. It is nonetheless interesting and occasionally useful to
know. There are two separate issues: (1) what output voltages will the chip
produce in either state? and (2) how will a given input voltage be resolved?
The first question is easily answered with your DMM. Measure the output
voltage from one of your NAND gates, and record the values observed for both
the high and low states.
To address the second question, monitor the output of the gate with a DIO
pin, and drive one input with the positive VPS supply. The other input should
be tied to 5 V, making the chip function as an inverter. Starting with the VPS
voltage at 0 V, gradually increase it until the ouput goes low. At what voltage
75
9.4 Logic Families
9 LOGIC GATES
does this occur? Then starting at a voltage fo 5 V, decrease the VPS value until
the output goes low. Again, note the threshold in your report.
To function well, the output high voltage should be well above the high/low
threshold, and the output low voltage should be well below it. Is this the case
for your chip? If one chip’s output were driving another chip’s input, how much
voltage noise from the first chip would be required to make the second chip
change its output state?
The output levels and input threshold generally vary with the chip design.
The 7400 chip is part of the TTL (transistor-transitor-logic) series, which all
have consistent specifications. High outputs are required to be above 2.4 V,
and low outputs below 0.4 V. An input below 0.8 V must be interpreted as
low, while an input above 2.0 V must be interpreted as high. (Inputs between
0.8 V and 2.0 V are not specified, so any behavior is possible.) Is your 7400
chip consistent with these specifications?
9.4
Logic Families
As mentioned, logic chips come in several varieties, known as families. The
families are distinguished by the middle letters of the chip name, so the 74LS00
is the LS family and the 74HC00 is the HC family. The initial 74 indicates
that these are all logic gate chips, and the final numbers specify which gates are
implemented and define the pin layout. Dozens of families are available, but the
7400, 74LS00, and 74HC00 are among the most common. We shall compare two
of their most important characteristics, switching speed and power consumption.
The switching speed can be measured using the circuit of Fig. 9.4. Here the
A input is taken from the Sync output of the function generator, which provides
a 0 to 5 V square wave. With B tied to 5 V, the circuit acts as an inverter, as in
Fig. 9.3(a). Monitor the Sync signal on your scope along with the output Q. As
the input rises and the output falls, measure the “gate delay” time Tsw between
when the input rises and the output falls. To be precise, you can use the logic
threshold values of 2.0 V for the input and 0.4 V for the output as the start and
stop times for the measurement. The delay is very short, so make sure the BW
limit button on the scope is out and use scope probes on the 10× setting to
minimize the measurement capacitance. You may find the “10× mag” button
useful for increasing the time resolution.
To measure the power consumption of the chip, hook up an ammeter in
series with the Vcc supply voltage. Using dc input voltages, measure the supply
Sync
Scope
1 MHz
5V
Figure 9.4: Circuit for observing the timing characteristics of a gate.
76
9 LOGIC GATES
9.5 CMOS Logic
current drawn when the output is low and when the output is high. Then using
the Sync signal, measure the supply current when the output is switching at
1 MHz. Calculate the power consumed in each case by multiplying the current
times the voltage and report your results in mW.
Perform these measurements for each of the 7400, 74LS00, and 74HC00
chips. What is the main difference between them?
9.5
CMOS Logic
The 7400 and 74LS00 chip both use bipolar transistors to implement the logic
gates, and are referred to as ‘transistor-transistor logic,’ or TTL. The 74HC00
chip is different in that it uses FETs instead. This type of gate is often called
‘CMOS’ because it uses complementary MOSFET transistor pairs. You can
usually identify a CMOS gate because it will have a ‘C’ somewhere in its family
designator.
CMOS chips have some signifcant performance differences from bipolar gates.
You should have found above that the static (not switching) power dissipation
is much lower. This is because FETs don’t draw any gate current. This is
obviously an advantage, but offseting it is the fact that CMOS chips are much
more easily damaged by static discharges and other electrical faults.
An important practical consideration when using CMOS chips is that all
unused inputs must be tied to a definite level. This is recommended for all logic
circuits in any case, but you saw in Section 9.2 that TTL gate inputs generally
float high. To compare, wire up a 74HC00 chip with the A1 and B1 inputs high.
Wire the other six inputs either high or low, as convenient. (Don’t wire any of
the outputs to a fixed value!)
Observe the Q1 output on the scope, verifying that it is low. Now unhook
the corresponding A input. What do you observe? Run a wire to the input and
touch its end with your finger. The output will likely oscillate at 60 Hz due to
your acting as an antenna. What happens if you hold the input wire in one hand
and touch the grounding pad or a 5 V wire with your other hand? Rather than
touching the input wire itself, what if you just hold its plastic insulation in one
hand while touching 0 or 5 V with your other hand? Describe your observations
in your report. Can you see why it is important to tie all inputs to a definite
voltage?
It is worth noting that the 74HC logic series uses slightly different threshold
values than the TTL series discussed earlier. Here a high output must be above
4.7 V and a low output below 0.2 V, while a low input is below 1.3 V and a
high input is above 3.7 V. You don’t need to check these, but if you compare to
the TTL thresholds listed in Section 9.3, you will see that a TTL high outout
might be too low for a CMOS chip to interpret correctly. For this reason, you
should avoid mixing TTL and CMOS chips in the same circuit.
77
9.6 Combinatorial Logic
9 LOGIC GATES
A
B
Q
C
Figure 9.5: Combinatorial logic circuit.
9.6
Combinatorial Logic
By combining various logic gates, you can implement arbitrary logical functions.
Figure 9.5 shows a simple example in which the output Q depends on three
input bits A, B, and C. Analyze this circuit and construct its truth table. In
binary arithmetic, (A, B, C) can be taken as the binary representation of an
integer A × 4 + B × 2 + C × 1, where the L state represents zero and the H
state represents 1. In this interpretation, what mathematical property does the
circuit recognize?
Construct the circuit on your breadboard using TTL gates. The required
chips can be found in the cabinet, and the pin designations can be quickly
determined with an internet search on the part number. Either the LS versions
or the plain 7400 series can be used. Measure the truth table as implemented,
and confirm that it follows your expectations.
9.7
Three-State Logic
Another type of logic gate that is often useful is the “three-state” device. At
first, this might suggest trinary logic, where three output levels represent the
values 0, 1, 2. But in fact, the outputs of a three-state device are 0, 1, and
‘off.’ In the ‘off’ state, the device asserts neither a high nor a low value, but is
instead effectively disconnected from the output pin. This is useful when several
devices are wired together to a common output. A common output is normally
called a ‘bus,’ and is used when multiple devices take turns sending signals to
one receiver.
The 74HCT125 is a three-state buffer, shown in Fig. 9.6. It has the truth
table
OE A Q
L
L L
L H H
H X off
Here ‘X’ stands for any value. The OE input should be read as “output enable”
and the bar indicates that you need to supply the inverse of the enable signal.
In other words, if ‘output enable’ is supposed to be ‘true,’ then you need to
78
9 LOGIC GATES
1
14
2
13
3
4
5
74HCT125
OE1
A1
Q1
OE2
A2
Q2
GND
12
11
10
6
9
7
8
Vcc
OE4
A4
Q4
OE3
A3
Q3
9.8 Multiplexer
DIO 0
A1
OE1
A
Q
DIO 6
DIO 1
DIO 8
A2
OE2
OE
DIO 7
(a)
(b)
(c)
Figure 9.6: The 74HCT125 quad three-state buffer. (a) Pinouts. (b) Circuit
symbol. (c) Testing circuit.
supply a ‘false’ value for OE. As with the NAND gates, there are four separate
buffers on each ’125 chip.
Set up the circuit shown in Fig 9.6(c). Take the inputs A1 and A2 to represent
data signals, while OE 1 and OE 2 control which signal is applied to the output
bus. First set OE 1 = L and OE 2 = H. Then you should see that Q follows A1 ,
while A2 is ignored. Conversely, when OE 1 = H and OE 2 = L, you should see
Q = A2 while A1 is ignored. Describe your observations in your report. What
do you observe for Q when OE 1 = OE 2 = H? Why would it be a bad idea to
set OE 1 = OE 2 = L?
9.8
Multiplexer
To demonstrate the use of three-state logic, we will implement a multiplexer
(or MUX). This device is shown schematically in Fig. 9.7(a). It has a total of
six inputs, four representing data (a, b, c, d) and two representing an “address”
(X, Y ). The single output Q is meant to follow one of the four data inputs,
and the address selects which input it follows. This can be represented by the
truth table:
X Y Q
L L a
L H b
H L c
H H d
where a, b, c, and d stand for the value at the corresponding input. You might
think of the multiplexer like a switch, as in Fig. 9.7(b), with the address bits
setting the switch position. Just like switches, multiplexers are useful in many
situations.
A multiplexer can be constructed using the three-state buffer. Simply hook
each input signal (a, b, c, d) to a corresponding buffer input (A1 , A2 , A3 , A4 ),
hook all four outputs (Q1 , Q2 , Q3 , Q4 ) together, and then use the OE pins to
determine which input is applied to the common output bus. To make this
79
9.9 Monostable Multivibrator
X
a
a
data
9 LOGIC GATES
b
b
Q
c
OE 4
Y
Q
c
X
d
d
Y
(a)
OE 3
X Y
address
(b)
OE 2
(c)
Figure 9.7: (a) Circuit diagram for a 4-input multiplexer. (b) Equivalent switch
circuit. (c) Partial circuit for translating the address (XY ) to the enable signal
(abcd).
work, we need to use logic gates to convert the two address bits (X, Y ) to one
of four enable signals, as follows:
X Y OE 1 OE 2 OE 3 OE 4
L L
L
H
H
H
L H
H
L
H
H
H
H
L
H
H L
H
H
H
L
H H
Figure 9.7(c) shows one way to implement this for channels 2, 3, and 4. Determine for yourself how the enable signal for the OE 1 channel can be derived.
(Feel free to use a different chip besides the NAND gate.)
Once you understand the design, set up the circuit and verify that the multiplexer works as desired. Test it using the Digital Writer and Reader tools,
making sure that for each combination of address bits, the output signal follows
the proper input signal and is unaffected by the other inputs. Describe your
approach and results in your report.
Note that integrated multiplexer circuits are available, such as the 8-input
74151. It would be unusual for you to actually build your own multiplexer in
practice.
9.9
Monostable Multivibrator
The monostable multivibrator is a digital component that finds many applications in circuits that need to generate pulses and delays. When triggered by
a transition on its input, it generates a single output pulse with a duration
determined by an RC network attached to the chip. Because of this behavior,
another common name for the device is a ‘one-shot.’
A common one-shot is the 74122, shown in Fig. 9.8. It has a fairly complicated input logic arrangement in order to provide maximum triggering flexibility. Referencing the circuit diagram, however, an output pulse will be produced
whenever the input to the square block sees a rising edge. If we tie the A2, B1,
80
9 LOGIC GATES
9.10 Logic Races
5V
R
1
14
2
13
3
12
4
7400
A1
A2
B1
B2
CLR
Q
GND
11
5
10
6
9
7
8
Vcc
R/C
NC
C
NC
Rint
Q
C
R/C
A1
C
Q
B1
B2
A2
Q
CLR
Figure 9.8: The 74122 monostable multivibrator. The logic gates at the input
are all internal to the chip.
and B2 inputs high, then what type of transition applied to the A1 terminal
will produce a pulse?
Wire up the circuit that way. You will also need to tie the CLR terminal
high (so that the device is ‘not cleared’). The output pulse duration is given
approximately by
tw = 0.45RC
The resistor R should be in the range of 5 kΩ to 50 kΩ, and the capacitor should
be larger than 1 nF. (More detailed information about the timing elements can
be found on the 74122 data sheet, if needed.) Set up your circuit using a 100k
pot and a 10 nF capacitor, and drive the input A1 at 500 Hz with the Sync
pulse from the function generator. Observe the input and output (Q) signals
on the scope, and verify that the output behaves as claimed when you change
the pot resistance. How accurate is the above formula for tw ?
One-shots end up being so handy that Horowitz and Hill spend some effort
warning against their overuse. The main concern is that the timing they produce
is not very precise, so you shouldn’t use them when precision is important.
Incidentally, the term ‘multivibrator’ refers to a circuit with two possible
states. In a monostable multivibrator, only one of the states is stable: when the
circuit is put in the unstable state, it returns to the stable one after time tw .
A bistable multivibrator remains in whichever state you place it, and is more
commonly called a latch. An astable multivibrator won’t stay put in either
state, and thus forms an oscillator.
9.10
Logic Races
The 74122 chip can be used to illustrate an important condition known as a
logic race. In this condition, the behavior of a circuit depends on the difference
in propagation times between two signals. Unless these propagation times are
deliberately controlled, unpredictable behavior can result.
As an example of a logic race, suppose that you applied the Sync pulse input
to both the A1 and B1 inputs of the 74122, leaving the other inputs all high
81
9.10 Logic Races
9 LOGIC GATES
A1
A1
B1
B1
A1 B1
A1 B1
(a)
(b)
Figure 9.9: Logic race in a 74122 chip, showing how the effective input signal
depends on whether (a) input A1 or (b) input B1 is evaluated first.
as before. The net input signal applied to the trigger of the multivibrator can
then be expressed as A1 · B1, where the bar indicates a NOT operation and
the · indicates AND. Figure 9.9 shows how the form of the net trigger signal
depends on the order in which the A1 and B1 signals are processed by the
circuit. If A1 comes first, an output pulse is triggered on a falling edge of the
input, while if B1 comes first, the pulse is triggered on a rising edge. If both
signals are evaluated at precisely the same time, no output pulse is produced
at all. Without knowing the internal details of the circuit construction, it is
impossible to determine what the behavior will be. To prevent this kind of
uncertainty, logic races should be avoided in circuit design.
To see what actually happens here, modify the circuit as described above.
Describe what you observe at the output when the input state changes.
82
10
Sequential Logic
The output state of a sequential logic circuit depends on both the present input
signals and the circuit’s history. The flip flop is a basic building block for sequential circuits. It is the simplest form of memory, which is a key component
of digital design. Sequential logic is the basis for a state machine, which is the
fundamental archetype of a digital computer.
This lab will require two days.
Reading: HH sections 8.15–8.18, 8.24 (pgs. 500–514, 523–524)
10.1
D-type Flip Flop
There are several varieties of flip-flop, but the simplest and most useful is the
D-type device illustrated in Fig. 10.1. The logic table for the 74LS74 is
S R C D Q Q
L H X X H L
H L X X L H
L L X X H H
H H ↑ L L H
H H ↑ H H L
Here ↑ denotes an L-to-H transition on the C (“clock”) input, which triggers Q
to change to the state on the D (“data”) input. Also, notice the odd behavior
(Q = Q) when S and R are both low.
The 74LS74 chip contains two D-flop circuits. Wire up one of the flops,
S
1
14
2
13
3
4
74LS74
1R
1D
1C
1S
1Q
1Q
GND
12
11
5
10
6
9
7
8
Vcc
2R
2D
2C
2S
2Q
2Q
D
Q
C
Q
R
Figure 10.1: The 74LS74 dual type-D flip flop.
83
10.2 State Machines
10 SEQUENTIAL LOGIC
Combinatorial
Logic
A
Qn
Dn
D
(a)
B
C
C
State Q1
A
0
B
0
C
1
D
1
Q2
0
1
0
1
(b)
Figure 10.2: (a) Schematic of a state machine. Here the slashes on the signal
lines indicate a parallel set of several values. (b) Example of a state diagram,
showing a two-bit counter.
using DIO signals to drive all four inputs. Monitor the outputs using the DIO
Reader. Does the device behave as advertised?
10.2
State Machines
A basic state machine consists of a register (an array of D-flops) whose outputs
are connected back to their inputs via a set of logic gates. With every clock
pulse, the state machine’s output progresses through a fixed series of states.
The states and their order of progression is determined by the logic gates used.
Figure 10.2 illustrates these ideas.
The simplest interesting state machine is the divide-by-two circuit of Fig. 10.3(a).
Construct it and drive the C input with the Sync output of your function generator. Note that all the S̄ and R̄ pins still need to be held high. Observe the
input and output signals on your scope. Is the output frequency half of the
input frequency?
For a more interesting example, suppose we wanted a divide-by-three circuit.
Here we will need to use two D-flops, and we want their output state to cycle
through:
Q1 Q2
L
L
L
H
H L
L
L
L
H
...
This divides the input frequency by three since the output cycle repeats once
for every three input cycles. Either Q1 or Q2 can be taken as the output when a
single signal is required. Note that the output wave form is no longer symmetric,
since the signal is low for two-thirds of the period. Nonetheless, the signal is
84
10 SEQUENTIAL LOGIC
D
10.3 Switch Debouncing
D1
Q
Q1
?
D2
Q2
in
in
Q
out
(a)
(b)
Figure 10.3: (a) Divide-by-two circuit. (b) What type of gate at D2 is required
to make this circuit divide the input frequency by three?
periodic with a period that is three times longer than that of the input.
In this state machine, we don’t really care where the (H, H) state goes, as
long as it is not back to (H, H). What would be the problem with that?
To implement this, we need logic gates to implement the truth table
Q1 Q2 D1 D2
L
L
L
H
L H H
L
L
L
H L
where each state leads to the next on our list. Here we see that we need D1 = Q2 ,
so we can wire Q2 directly to D1 , as in Fig. 10.3(b). What do we need to generate
D2 ? Where does the state (H, H) go in your design?
Using your gate, construct the circuit and drive the clock signals of both
flops with the Sync signal. Observe the outputs on your scope and describe
their behavior in your report. Does everything work as you expected? Is there
a maximum frequency for correct operation, or does it work all the way to
5 MHz (the maximum we can apply)?
10.3
Switch Debouncing
Sometimes it is convenient to set logic levels by hand, using a switch. For
circuits like flip flops that trigger off an edge, this is problematic because manual
switches bounce: rather than giving a clean transition from open to closed, the
transition makes and breaks several times before settling to the desired state.
This can generate spurious triggers.
To see this, get a “mini DIP” switch from the cabinet. This is simply an
array of SPST switches that fits nicely in your circuit board. The wiring shown
in Fig. 10.4(a) configures the switch to provide +5 V when open, or 0 V when
closed. It also powers an LED to indicate the signal state, which is helpful in
complicated circuits. Wire one switch up to the C input of your divide-by-three
85
10.4 RAM
10 SEQUENTIAL LOGIC
5 nF
5V
C
LED
4.7k
(a)
In1
Out2
In3
Out4
In5
Out6
OSCin
GND
1
16
2
15
3
14
4
5
6
MC14490
1k
13
12
11
7
10
8
9
Vcc
Out1
In2
Out3
In4
Out5
In6
OSCout
(b)
5V
5V
OSC
In
From
switch
OSC
Out
In
Out
To
clock
(c)
Figure 10.4: (a) Using a switch to generate logic levels. (b) MC14490 hex
bounce eliminator. (c) Wiring diagram for the MC14490. Use 1N914 diodes on
the oscillator pins.
circuit (replacing the Sync signal). Observe the outputs and record the (Q1 , Q2 )
states after each flip of the switch, for at least 10 transitions. Does the circuit
correctly divide by three?
The easiest fix for the bouncing problem is to use a debouncer chip, like the
MC14490 in Fig. 10.4(b). This chip uses a set of flip-flops and a self-generated
clock signal to detect an input transition, but then ignore any other transitions
for the next few ms while the bouncing settles down. The result is one clean
transition on the output.
Wire up the debouncer as shown in Fig. 10.4(c). The debouncer inputs
include an internal pull-up resistor, so you don’t need the connection to 5 V
on the input, but the chip doesn’t provide enough current to illuminate the
LED. The LED will probably be helpful, so leave it set up as in (a). (The
internal pull-ups also mean that you don’t need to connect the unused inputs
to ground.) Use the debouncer output to clock your divide-by-three circuit. As
before, record the output sequence you obtain. Does it work correctly now?
You can put away your flip-flop circuit now, but keep the switch and debouncer chip set up.
10.4
RAM
A register is a simple form of memory, and is useful when you need to store up
to a few bytes or so. (Recall one byte = eight bits.) When larger amounts of
data storage are required, however, RAM (= random access memory) is more
practical. There are several types of RAM, but the simplest is probably SRAM
(static RAM), which consists essentially of a huge array of D-flops together with
a multiplexer and demultiplexer to allow each flop to be individually accessed.
A schematic is shown in Fig. 10.5.
The idea here is that you present a value on the Data In line (either H or
L), and an address (binary 0 through 7) on the three Address lines. When the
86
10 SEQUENTIAL LOGIC
10.4 RAM
(8 D-flops)
D
Data In
Q
D
Q
8:1 MUX
Write
Enable
1:8 DEMUX
en
en
D
Data
Out
Q
Address
en
Figure 10.5: Schematic of how random access memory works.
Write Enable line is brought high, the demultiplexer passes that signal on to
one of the eight D flops, which then activates and sets its output Q to the Data
In value. That value is now stored at the specified address. Meanwhile, the
Data Out line continually shows the value stored at the D flop identified by the
address lines.
Real memory chips use this basic scheme, but with many more memory
locations. The KM6264AL (Fig. 10.6(a)) is an 8k×8 SRAM chip, meaning
that it can store up to 8192 (= 213 ) ‘words’, where each word consists of 8
bits in parallel. (For comparison, the circuit of Fig. 10.5 shows a 8 × 1 RAM,
with 8 words of 1 bit each.) The pin out diagram is shown in Fig. 10.6(a).
Instead of having separate Data In and Data Out lines, here there are eight data
lines Dn which function as outputs when R/W is high (you are Reading data
from memory), and as inputs when R/W is low (you are Writing to memory).
Thirteen address lines An specify the location in memory to read from or write
to. The OE signal (“not output enable”) must be low to activate the data lines
at all, otherwise they are in the ‘off’ state of three-state logic. The CS1 and
CS2 pins can be used to put the chip in a standby mode where data is retained
but power consumption is minimal. We will not be using any of these features,
so you can directly wire OE = L, CS1 = L, and CS2 = H.
To demonstrate storing and retrieving a signal, wire up the circuit of Fig. 10.7.
A debounced switch from your MC14490 sets R/W ; the oscillator capacitor is
not shown in the diagram but is still required. The switch also controls a
74HCT125 three-state buffer (Fig. 10.6(b)). Recall here that when the OE signals are high, the buffer outputs are in the off state, so that the display lines are
controlled by the 6264 chip in Read mode. When the EN s are low, the buffer
outputs equal the inputs so that data can be input to the chip in Write mode.
87
10 SEQUENTIAL LOGIC
28
2
27
3
26
4
25
5
6
7
8
9
24
23
22
21
20
10
19
11
18
12
17
13
16
14
15
Vcc
R/W
CS2
A8
A9
A11
OE
A10
CS1
D7
D6
D5
D4
D3
OE1
A1
Q1
OE2
A2
Q2
GND
1
14
13
2
3
4
5
74HCT125
1
KM6264AL
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
D0
D1
D2
GND
12
11
10
6
9
7
8
(a)
Vcc
OE4
A4
Q4
OE3
A3
Q3
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
20
2
19
3
18
74HCT574
10.4 RAM
4
5
6
7
17
16
15
14
8
13
9
12
10
11
Vcc
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
C
(c)
(b)
Figure 10.6: (a) Pin outs for the KM6264AL memory chip. (b) Pin outs for the
74HCT125 quad buffer. (c) Pin outs for the 74HCT574 octal D-flop register, to
be used in the next section.
DIO 8-11
(display)
KM6264AL
74HCT125
DIO 0-3
(data)
A1
Q1
D0
A0
A2
Q2
D1
A1
A3
Q3
D2
A2
A4
Q4
D3
A3
DIO 4-7
(address)
MC14490
OE1
OE2
OE3
OE4
R/W
CS2
In1
R/W
Out1
+5 V
CS1
OE
Figure 10.7: Circuit allowing storage and retrieval from random access memory
88
10 SEQUENTIAL LOGIC
10.5 Memory-Based State Machine
For simplicity, we will only use four bits for the data lines and addresses,
even though the chip could accommodate up to eight and thirteen, respectively.
Wire the unused address pins A4 through A12 to ground.
To test the circuit, follow this procedure: First, set R/W low, so that you
can write data to the memory. Set the address bits (DIO 4–7) to 0000, and
vary each of the data bits (DIO 0–3). When you change the state of a data bit,
the corresponding monitor bit (DIO 8–11) should follow it. If it doesn’t, then
recheck your wiring.
Once this works, enter a pattern of your choice in the data bits and make a
note of it. Set the R/W switch high. Now when you change the data bits, the
monitors bits should remain fixed in the pattern you saved.
Finally, change the address bits to 0001, and set R/W low again. Load a
different bit pattern into the data and save it by switching R/W high. Now if
you go back to address 0000, the first bit pattern you saved should be displayed,
while address 0001 displays the second.
After this is working correctly, write several patterns into several different
addresses and verify that you can retrieve them without error. Record your
stored data and addresses in your report. If you do observe any retrieval errors, note them. What data do you observe at addresses where you have not
previously stored anything?
10.5
Memory-Based State Machine
A computer processor is, at its core, what you get when you combine a state
machine with memory. The state machine works as in Fig. 10.2, but instead of
using combinatorial logic to generate the next state from the current one, you
simply look the next state up in memory. Figure 10.8 illustrates the idea.
Suppose you require a state machine that proceeds through states A → B →
C → . . ., where each state represents a specific pattern of N bits. Further,
assume that upon power up, the output of the register in Fig. 10.8 initializes to
state 0. Then program the memory so that bit pattern A is stored at address
0, pattern B is stored at address A, pattern C is stored at address B, and so
n
n
n
n
Figure 10.8: A programmable state machine, comparable to Fig. 10.2(a).
89
10.5 Memory-Based State Machine
10 SEQUENTIAL LOGIC
forth. The data from the memory is fed back to the address through the D-flop
register, which is controlled by a clock.
When the circuit is turned on, the register starts in state 0, which is the
address presented to the memory. The memory data outputs therefore start in
state A, the first state of the desired sequence. When a clock transition arrives,
pattern A is transferred to the address of the memory, so the data output
changes to the pattern stored there, which is B. At the next clock transition,
the address proceeds to B and the data to C. In this way, the entire state
sequence is mapped out.
We shall implement a simple version of this scheme, using the circuit of
Fig. 10.9. To avoid needing too many wires, it uses just two bits for the data
and address. The 74HCT574 chip (Fig. 10.6(c)) serves as the register, and
is clocked by the Sync output of the function generator running at 1 Hz. It
features an enable pin which can be used to turn its outputs off. Note that the
CSS and OE inputs of the 6264 chip must be wired as in Fig. 10.7. The unused
address inputs A2–A12 must all be wired to ground.
The circuit uses two switches to control the operational mode. When the
Program and Run signals are both low, the data and address buffers are enabled,
the register is disabled, and the memory chip is in write mode. This allows the
memory to be programmed, just like you did in the previous section.
When the Program signal is high and Run is low, the data buffer is disabled
and the memory is in read mode, but the address buffer and register still allow
manual control of the address bits. This lets you check the stored data to make
sure it is correct; think of this as “debugging” mode.
Finally, when Program and Run are both high, the register provides the
memory address and the state machine is running. Why do you need to avoid
setting Program low and Run high at the same time?
As shown in the circuit, you don’t need any pull up resistors or LEDs on the
control switches. The LEDs can again be helpful, however, so feel free to wire
them up as in Fig. 10.4 if you find yourself getting confused about what mode
the circuit is in.
To test the circuit, load the following data into the memory:
A1 A0 D1 D0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
To do this, set both switches to the low position, putting the circuit in “program” mode. Set the two address bits to (0,0), and the two data bits to (0,1).
Since the circuit is now continuously writing to memory, the data values are
automatically stored. Then change the address bits to (1,0), and the data bits
to (0,0). Continue in this way through all four states. Note that the order the
states are listed is important. Since the circuit is constantly loading the data
bits to memory, we would have trouble if we tried to change both address bits
90
10 SEQUENTIAL LOGIC
10.5 Memory-Based State Machine
74HCT574
Data Out
(DIO 8,9)
MC14490
Data In
(DIO 0, 1)
Q0
D1
Q1
OE
C
SYNC
KM6264AL
74HCT125
Program
D0
A1
Q1
D0
A0
A2
Q2
D1
A1
OE1
In1
Out1
OE2
R/W
Address In
(DIO 4, 5)
Run
In2
Out2
Address Out
(DIO 12, 13)
A3
A4
OE3
Q3
OE4
Q4
74HC04
Figure 10.9: Circuit for memory-based state machine.
at the same time, by for instance writing data to address (1,1) immediately
after writing to (0,0). The DIO writer only lets us change one value at a time,
so it would be impossible to make this address change without inadvertently
writing to the (0,1) or (1,0) address in between. By entering the data in the
order shown, we avoid this problem because only one address bit is changed in
each step.
Once this is done, put the circuit into debugging mode and check that the
values are correct by observing the data out lines as you step through all four
addresses. If everything look correct, switch to Run mode. The outputs should
then cycle through the same states as the divide-by-three circuit you built earlier. Describe your observations in your report.
Of course, this circuit is much more flexible than the previous one. Devise a
different state sequence of your own and run it. Describe the sequence in your
report, and again note your observations.
When you are finished, disassemble your circuit and clean up your station.
91
10.5 Memory-Based State Machine
10 SEQUENTIAL LOGIC
92
11
Counters and Oscillators
Though specialized, the counter is one of the most likely digital circuits that
you will use. We will see how typical counters work, and also how to interface
data with an LED display. Counters and many other circuits often require a
clock as well, and we will discuss two types of oscillator circuits that can serve
this purpose.
This lab will require one day.
Reading: HH sections 8.03, 8.25, 5.14, 5.19 (pgs. 473–478, 524–525, 286–291,
300-303)
11.1
Binary Counter
The 74193 chip is a typical 4-bit binary counter. It has several useful features:
it can count up or down, it can be initialized to an arbitary value, and it
has outputs to faciliate cascading multiple chips. Figure 11.1 shows the pin
designations, with the following descriptions:
Vcc, Ground: Supply voltages as usual.
Qi : Output bit i. Bit A is the least significant.
Up: Increments counter output by one when a rising edge is received.
Down: Decrements counter output by one when a rising edge is received.
Clear: When high, forces all output low.
Load: When low, each output Qi is set to the value at input Di .
Carry: Gives rising edge when output wraps from 1111 to 0000 while counting up.
Borrow: Gives rising edge when output wraps from 0000 to 1111 while
counting down.
B
1
16
B
2
15
A
3
14
4
13
5
12
C
6
11
D
7
10
C
8
9
D
A
Figure 11.1: Pin designations for 74193 4-bit binary counter.
93
11.2 LED Display
11 COUNTERS AND OSCILLATORS
Note that a trigger input (Up or Down) that is not being used must be held in
the high state. We won’t be using the Di inputs, but they should be tied to
fixed values to to avoid generating errors. The Load input should be tied high.
Wire up the chip with Clear tied to ground and the Down trigger tied to 5
V. Drive the Up trigger with the Sync pulse from your function generator, with
a frequency of 1 Hz. Monitor the outputs Qi with channels 0-3 of the digital
reader, and verify that they count up at the expected rate. Drive the Down
trigger instead and verify that the output counts down.
Note that if you include the trigger signal itself as data, you really have
five bits of counting capacity. If more capacity is needed, it is easy to cascade
multiple chips. Put your counter back into the upward counting mode. Then
get a second 74193 and wire it up like the first, but take the Up trigger from the
Carry output of the first chip. Monitor the four new outputs on channels 4-7 of
the digital reader. Do the eight output bits correctly count from 0 to 255?
11.2
LED Display
Watching the counter output on the Digital Reader is neither satisfying nor
practical. Let us instead display the result on an LED numerical display. The
HP 5082-7340 display is convenient, because it has built in logic and drivers to
convert a binary number to the appropriate combination of illuminated LED
bars. It displays one digit in hexadecimal notation (4 bits), so you will need
two displays.
The pinouts for the 5082 are shown in Fig. 11.2. Here In1 refers to the
ones-place bit, In2 refers to the twos-place bit, etc. The Latch input causes the
display to hold its current value while the input is high. The Blank input causes
the display to go dark while the input is high. For our purpose, they should
both be tied low.
Wire up both displays, using the four bits from the first counter to drive one
and the four bits from the second counter to drive the other. Try to position the
displays so that the most-significant digit is on the left, as in standard notation.
Run the the counters and check that they properly increment from 00 to FF.
Try increasing the frequency of the clock signal. How fast can it go so that you
can still tell that the numbers are counting correctly? (This has more to do
8
7
6
5
1
2
3
4
In2
In4
In8
Blank
Bottom View
1
2
3
4
8
7
6
5
In1
Vcc
GND
Latch
Top View
Figure 11.2: Pin designations for the HP 5082-7340 LED hexadecimal display.
The dot on the bottom of the package shows which pin is pin 1. The numeral
4 on the top view illustration shows how the display value is oriented.
94
11 COUNTERS AND OSCILLATORS
11.3 Binary-Coded Decimal
with your eyes than the circuit, but it is still a useful number to know when
setting up a display.)
11.3
Binary-Coded Decimal
Of course, people don’t usually work in hexadecimal notation. When interfacing
with humans, the normal practice is to use the binary-coded decimal (BCD)
convention. Here counting is done in base ten, but the numbers are stored in
binary representation. A 4-bit BCD counter’s output would thus go:
0000 (0)
0001 (1)
0010 (2)
0011 (3)
0100 (4)
0101 (5)
0110 (6)
0111 (7)
1000 (8)
1001 (9)
0000 (0)
etc
The four bits are not used as efficiently as in a binary counter, but in many
situations bits are cheap. When you need to convert binary data to BCD, you
can use chips like the 74184/74185. (The ’184 converts BCD to binary, and the
’185 converts binary to BCD.) For small circuits, however, it is more likely to
be convenient to simply work in BCD throughout. For instance, the 74192 is a
BCD counter that is pin-compatable with the 74193. Try simply replacing both
’193 chips with ’192s. Does your display now count in decimal? Why you don’t
need to change the display chip too? If you were storing data in a RAM chip,
would you need to know whether it was binary or BCD?
11.4
Timer
So far we have been using the function generator signal for our clock, but if you
were building a real circuit, you would not typically want to rely on an external
signal. There exist a variety of ways to generate an oscillating signal of your
own. One of the most convenient is the 7555 timer chip, shown in Fig. 11.3. The
core logic is shown in part (b). Here the op amps are serving as comparators,
which we will see more of in the next lab. Since there is no negative feedback,
the op amp output simply rails high (5 V) or low (0 V) depending on whether
the positive or negative input signal is higher.
To operate as an oscillator, the 7555 is wired as in part (c). Also, the Reset
signal must be tied high. The connection from the output back to the Trig
and Threshold inputs causes the circuit to oscillate, at a theoretical frequency
95
11.4 Timer
11 COUNTERS AND OSCILLATORS
Vcc
R
Threshold
Gnd
Trig
Out
Reset
1
8
2
7
3
6
4
5
Out
Vcc
Discharge
Threshold
Control
Threshold
Out
Vout
Trig
C
Reset
Gnd
Vcc
5V
Trig
(a)
(b)
(c)
Figure 11.3: (a) Pin designations for 7555 timer. (b) Core logic functionality.
Note that the Reset, Discharge, and Control signals are not shown; consult
the datasheet for more information. (c) External wiring for operation as an
oscillator. The Discharge and Control pins should be left open.
(in Hz) of 0.7/RC. You will get to work through this calculation yourself in a
homework assignment.
Wire up a 7555 chip, using a 200 pF capacitor and a 100 kΩ resistor. Verify
that the output oscillates and compare its frequency to the expected value. You
should measure R and C to make an accurate comparison. Replace the resistor
with a 100k pot. What is the maximum frequency the circuit can produce?
Choose a resistor/capacitor pair to give a signal at approximately 1 Hz, noting
that the device manufacturer recommends using a larger R and a smaller C
to minimize the output current required. Use your timer signal to drive your
counter, so that you have a self-contained circuit. Measure your timer frequency
by counting the number of oscillations in one minute, as determined by a watch
or the wall clock. How accurate is the 0.7/RC formula?
Two notes: First, the 7555 (and a handful of similar chips) are CMOS
versions of the original NE555 TTL chip, which is still available. However,
the 555 chip draws a substantial current spike from the power supply when it
switches, and it can be difficult to prevent that spike from affecting other parts
of your circuit. The 7555 does not have this problem.
Second, the 7555 and its relatives can do considerably more than just oscillate. It can be wired to act as a monostable multivibrator, the oscillation
frequency can be modulated and the pulse width can be varied, among various
other possibilities. If you have an electronics problem involving the generation
of some kind of timed pulses, it would be worth looking through the application
notes for the 555 chip for a solution.
You will be using the counter and timer circuits in the next lab, so you
should leave them set up on your breadboard. You’ll only need one counter
chip and you won’t need the displays, so you can put them away to make room.
96
11 COUNTERS AND OSCILLATORS
11.5 Quartz Crystal Oscillators
74HC04
10M
100k
Crystal
20 pF
20 pF
(a)
(b)
Figure 11.4: (a) Equivalent electronic circuit for a quartz crystal. (b) Oscillator
circuit based on a quartz crystal.
11.5
Quartz Crystal Oscillators
It is difficult to achieve timing precision better than about 0.1% using the 7555
timer, or any other RC-based circuit, due to thermal drifts in the component
values. When greater precision is required, the preferred solution is the quartz
oscillator. This consists of a quartz crystal that is precisely cut so that it vibrates
mechanically at a particular frequency. Quartz is a piezo-electric material, so
when it is subject to strain, it generates an voltage at its surface and vice versa.
It is therefore possible to drive the mechanical vibration with an electronic
signal.
The resulting system is somewhat complicated, but it works out that the
crystal acts electronically as the circuit of Fig. 11.4(a). Such a circuit could of
course be constructed electrically, but the advantage here is that the resonant
frequency is stable to typically a few parts per million. Quartz crystal oscillators
are used, for instance, to generate the timing in standard wristwatches, where
1 ppm corresponds to an error of about 1 second per week.
The easiest way to generate an oscillating signal using a quartz crystal is with
the circuit of Fig. 11.4(b). It is difficult to analyze this circuit quantitatively,
but the basic principle can be understood as follows: the output of the first
NOT gate is fed back to its input, making an unstable circuit that inherently
tends to oscillate. By passing the feedback signal through the crystal, the circuit
oscillation can drive and lock to the oscillation of the crystal. The arrangement
of resistors and capacitors ensures that the instability is large enough to permit
oscillation but small enough for the crystal to be effective. The second NOT
gate serves as a buffer, to ensure that the output signal has standard logic levels
and that loads on the circuit do not affect the oscillation.
Wire up this circuit using a 74HC04 CMOS chip and a 1-MHz crystal. The
97
11.5 Quartz Crystal Oscillators
11 COUNTERS AND OSCILLATORS
circuit tends to work better if the components are placed close together and
the number of wire connections is minimized; at high frequencies like these, the
inductance of a wire can be an appreciable impedance. Similarly, the signal will
be clearer if you use a 10× scope probe. It may also help to filter the chip’s
power supply pin using a 1 µF capacitor to ground. Try to obtain oscillation
by adjusting the potentiometer. You should observe a reasonably clean squarewave signal near 1 MHz frequency.
Once the circuit is working, measure the frequency using your oscilloscope,
and compare to the expected value. (It is likely that any error you see is due to
the scope, rather than the crystal.) When you are finished, clean up the crystal
oscillator circuit, but again, leave a counter and timer out for next time.
98
12 DAC/ADC
12
Converting Between Digital and Analog
For many applications, it is necessary to convert analog signals from a circuit or
sensor to digital signals that can be manipulated by a computer, and vice versa.
The simplest such tasks can be be performed by a comparator, but more generally, an ADC (analog-to-digital converter) or DAC (digital-to-analog converter)
will be required. In this lab, we will explore a few aspects of these processes.
This lab will require two days.
Reading: HH sections 4.23–24, 9.15–16, 9.20–22 (pgs. 229–232, 612–618, 621–
631)
12.1
Comparator
A comparator is a high-gain differential amplifier, much like an op amp. It is not
designed, however, to be operated with negative feedback. Instead, it provides
a binary output, railing high if the input V+ > V− and low if V+ < V− . In this
way, it can serve as a simple interface between analog and digital systems.
The pin designations for the LM311 comparator are shown in Fig. 12.1(a).
The Balance inputs can be used to adjust the offset voltage, just as in an op
amp, while the Strobe input can be used to force the output low, regardless of
the inputs. We will not be using either of these features and you can leave pins
5 and 6 unconnected.
An interesting feature of the LM311, and most comparators, is that it has an
“open-collector” output, represented schematically in 12.1(b). Here an external
pull-up resistor must be used to complete the circuit. Typically, a value of 1 kΩ
is a good compromise between high speed and low power dissipation. Note that
the need for an output resistor is not always made perfectly clear in device
datasheets, but the circuit will not function correctly without one.
5V
0-10 V
10k
V
1k
1
2
3
4
8
LM311
Gnd
V+
VSupply -
7
6
5
Supply +
Out
Balance/Strobe
Balance
Vin
Vout
10k
(a)
(b)
(c)
Figure 12.1: LM311 comparator. (a) Pin designations. (b) Open collector
output configuration. (c) Circuit for lab.
99
12.2 Schmitt Trigger
12 DAC/ADC
An advantage of the open-collector output scheme is seen in Fig. 12.1(c),
where the pull-up voltage can be varied. This lets the comparator serve as a
very simple DAC: it converts an input digital signal at standard logic levels
to an output signal that switches between whatever voltage the analog circuit
requires.
Construct this circuit, taking Vin from a DIO pin, and using the variable
power supply to generate the pull-up voltage. Use 15 V for the positive supply
and ground for the negative supply. Pin 1 must also be connected to ground.
Observe the output on the scope, and note how you get a digitally controlled
version of the VPS voltage. Measure both the high and low output values for
a few different VPS settings. How close to the nominal analog levels (the VPS
voltage and ground) does the output get?
Conversely, if you use 5 V for the pull-up voltage and the variable supply
for the input, the circuit serves as a basic ADC. It provides a single-bit output
that is low when the input is below the threshold and high when it is above the
threshold. Modify the circuit of 12.1(c), accordingly, and observe the output
with the Digital Reader while the input level is varied.
You might notice that if you slowly step the input across the threshold, the
reader display light flickers. When the input is very close to the threshold, even
very small noise signals can cause the comparator state to change. To observe
this effect more clearly, drive the input with a 500 Hz triangle wave from the
function generator, using a 5 Vpp amplitude and a 2.5 V dc offset. Observe both
the input and output with the scope. You should see the output switching as
expected. However, if you trigger on the output signal and zoom in, you should
be able to see multiple back-and-forth transitions between states due to input
noise. You can imagine that using a signal such as this as the trigger for a digital
circuit would be problematic. Fortunately, the problem has a straightforward
fix, the Schmitt trigger.
5V
Vout
R2
1k
R1
Vin
10k
5V
Vout
Vref
5V
hysteresis
LM311
10k
0V
Vref
(a)
(b)
Figure 12.2: (a) Schmitt trigger circuit. (b) Hysteresis curve.
100
Vin
12 DAC/ADC
12.2
12.2 Schmitt Trigger
Schmitt Trigger
A Schmitt trigger consists of a comparator combined with positive feedback, as
seen in Fig. 12.2(a). The effect of the feedback is to create hysteresis in the
switching behavior. If the circuit output is originally low, then the signal at
V+ will be lower than Vin . Therefore, Vin must rise somewhat higher than Vref
before the output will switch. Once the output is high, V+ will be higher than
Vin , so Vin will have to drop somewhat lower than Vref before the output will
switch low again. The difference between the two input thresholds is termed
the hysteresis, as illustrated in Fig. 12.2(b).
This technique reduces the sensitivity to noise, since the input signal would
need to fluctuate by an amount larger than the hysteresis in order to affect the
output. Of course, hysteresis also reduces the accuracy of the comparator, since
the output no longer precisely measures how Vin compares to Vref .
Wire up the circuit using R1 = 10 kΩ and a 100 kΩ potentiometer for
R2 , with the pot resistance initially maximum. Use the scope to observe the
switching behavior with a 500 Hz triangle wave drive, and compare to what you
observed before. Does the output now exhibit a single clean transition?
To analyze the circuit and calculate the hysteresis, note that the R1 and R2
resistors form a voltage divider between the output and the input, so that
V+ =
R2 Vin + R1 Vout
.
R1 + R2
The output will change states when V+ = Vref . Solving for Vin in that condition
gives
R1
R1
Vref −
Vout .
Vin = 1 +
R2
R2
If Vout varies by ∆Vout (here 5 V), the corresponding hysteresis ∆Vin will be
∆Vin =
R1
∆Vout .
R2
Note this analysis assumes that the output pull-up resistor is small compared
to R1 + R2 , so that the voltage drop across it is not significant.
To measure the the hysteresis in your circuit, you can use the oscilloscope’s
XY mode. In this mode, the horizontal sweep is controlled by the Ch 1 signal,
rather than a temporal ramp. This allows the scope to diplay the Ch 2 signal
as a function of the Ch 1 signal instead of as a function of time. Attach your
function generator signal to the scope Ch 1, and the circuit output to Ch 2. Set
the trigger source to Ch 1, but display only Ch 2. Then put the scope in XY
mode by depressing both the “B” and “Alt” buttons near the cursor control
knob. Set the scope to display Ch 2 only.
To see in real time how the signal works, turn the function generator frequency down to 0.5 Hz. You should be able to tell that the output rises at a
lower voltage than where it drops. To measure the difference, turn the input
101
12.3 The AD7569 DAC/ADC
12 DAC/ADC
signal frequency up to 10 kHz so that the entire curve is displayed at once. You
can use the cursors to measure the difference between where the output signal
drops and rises. (Note that you’ll have to display Ch 1 to see what voltage scale
it is set at.) The horizontal separation of these points gives ∆Vin . Compare
your measurement to the above formula for your resistor values. Vary the pot,
and describe how the hysteresis responds.
When designing a Schmitt trigger, you would set the hysteresis based on
the amount of noise in the input signal. Integrated Schmitt triggers circuits are
also available, such as the 7414 hex inverter. The nominal hysteresis level for
the 7414 is 0.8 V.
Once you have completed this section, disassemble the comparator circuit
and put it away.
12.3
The AD7569 DAC/ADC
When more than one bit of A/D conversion is needed, it is normally best to use
an appropriate IC chip. You can choose from a variety of chips using a variety
of methods. To give you a little familiarity with the topic, we will examine one
general purpose chip here, the AD7569 from Analog Devices.
The AD7569 is a complicated device. It contains both a DAC and ADC,
with 8 bits precision each. The ADC uses the successive approximation register
technique. The chip also features a variety of control signals designed to allow
flexible interfacing with different systems. A datasheet for the device is given in
Appendix D, which you should consult for reference. Note that the datasheet
also describes the AD7669, which we are not using. A few things to look at
now:
Page 1: The functional block diagram gives an overview of what the chip
does. Note that the data lines DB0. . . DB7 form a bus that serves as the output
for the ADC and the input for the DAC, depending on the control signals
applied.
Page 6: Pin designations. We have the DIP configuration. Some paper
labels with the pin numbers are available that you can tape to the top of the
chip, to avoid pin counting errors.
Page 7: Pin function descriptions. Note that there are three different
grounds provided. In precise work, it would be desirable to keep the digital
and analog grounds separate, to avoid putting digital noise on your analog signal. We shall not worry about that here, and just tie all the grounds together.
Note also that the CS pin is not described very well. When this pin is high, the
data lines are set to the ‘off’ state of three-state logic. This allows the data bus
to be shared with other devices. Since we have only one device to worry about,
we will keep CS tied low.
Page 10–12: The Digital Interface section explains how the DAC and ADC
are controlled by the digital signals. This is the key information that explains
how to make the chip work. Skim through it now, and refer back to it when
constructing the circuits below.
102
12 DAC/ADC
12.4 Negative Supply
R2
+
+
1 uF
1 uF
R1
Adj
-15 V
Out
Vout
(a)
Out
Adj
In
In
(b)
Figure 12.3: LM337 negative voltage regulator. (a) Pin designations. (b) Wiring
diagram.
Page 15: Unipolar vs Bipolar operation. We will be using bipolar operation,
so make sure you understand Table V. This is called two’s-complement encoding,
and is the standard way to represent negative values in binary.
12.4
Negative Supply
For bipolar operation, the AD7569 requires supply voltages of ±5 V. Our breadboards supply +5 V, but not -5 V. (We could use the variable power supply, but
we will want to use that as a signal source.) We can conveniently derive -5 V
from our -15 V supply using an LM337 negative voltage regulator. This device
and its wiring diagram are shown in Fig. 12.3. It produces an output voltage
R2
Vout = (−1.25 Volts) × 1 +
R1
from an input voltage more negative than this. R1 should be around 100 Ω.
Obtain a chip and wire up the circuit to produce an output voltage close to
-5 V. Record the voltage you obtain.
Note that there is a positive voltage version of this device, the LM317.
Voltage regulators provide a simple and convenient way to generate various
supply voltages from a single source.
12.5
DAC
We shall first use the AD7569 to implement a simple DAC. Obtain a chip and
wire the supply voltages, noting that VDD is positive and VSS is negative. (The
notation refers to the drain and source of a FET.) Wire all three grounds to a
common ground, tie CS low, tie Range high, and tie Reset high. We won’t be
changing any of these settings.
To operate as a DAC, tie Read high, and ST low. Whenever an upward
transition ↑ is applied to the WR input, the chip will read the eight data lines,
convert them to an analog voltage, and output that voltage on the Vout pin. To
start, use a DIP switch to control the WR input. Tie the pin to 5 V through
103
12.6 ADC
12 DAC/ADC
a 1 kΩ resistor, and also to ground through a switch. We don’t need to worry
about debouncing the switch here, because we don’t mind if the chip performs
the DAC conversion several times whenever we flip the switch. Start with the
switch closed (so WR is low).
Take the DB0–7 lines (here acting as inputs) from the DIO pins, which will
be controlled by the Digital Writer tool. Monitor the output Vout with your
scope and a voltmeter.
Power up the circuit, and set the DIO signals to all zeros. Switch WR high
and then low again. Does the output voltage go to zero? Try several different
digital inputs, and verify that that output voltage responds appropriately in
each case. Make a table in your report of the signals you applied and the
resulting outputs. Be sure to include some negative values in your exploration.
What offset do you observe for an input value of zero? What is the minimum
step size for the output voltage? Calculate the output voltages you expect and
compare to your observations.
More often, the inputs for a DAC are generated electronically. As a simple
example, set up a 74193 counter as in Lab 11. Drive its clock with the sync
pulse from the function generator. The same signal can drive the WR pin of the
AD7569. Use the four outputs of the counter to drive pins DB1–4 of the DAC,
while the sync pulse drives DB0. Tie pins DB5–7 low. Observe the output on
the scope. You should see a sawtooth ramp, and at higher speeds, the discrete
output levels should be evident. How many steps do you observe, and why do
you see that many? What do you observe at very high clock speeds, for instance
500 kHz to 5 MHz? The DAC is specified to have a 1 µs settling time. Are your
observations consistent with that?
12.6
ADC
Converting from analog to digital is a little more complicated because there are
two different modes of operation. In Mode 1, the conversion timing is controlled
with the RD and ST pins, while in Mode 2, only the RD signal is used and the
timing is more automatic.
Either mode requires a clock signal to drive the successive approximation
register circuitry. This can be generated internally, by tying a resistor and
capacitor in parallel from the Clk pin to ground. The recommended values (see
Fig. 21 on page 15 of the datasheet) are R = 7.3 kΩ and C = 68 pF. If these
values aren’t available, try to choose a similar pair with about the same RC.
Mode 1 is convenient for manual operation. Connect RD and ST to a pair
of DIO pins that are set low. Tie WR low. Apply a voltage to Vin from the
variable power supply, but do not exceed ±2.5 V. Monitor all eight DB pins on
DIO channels with the Digital Reader. Monitor the input level with a voltmeter.
To make a conversion, first toggle RD high, which temporarily disables the
DB pins. Then apply a rising edge to ST, which initiates the conversion. Set
ST low again, and then set RD low again to display the new data.
104
12 DAC/ADC
12.7 Nyquist Sampling Theorem
Try a handful of input levels, both positive and negative. Again, make a
table of the results in your report, and make sure they are what you expect.
How repeatable are the results, and what does the repeatability indicate about
the noise in the circuit?
To make a more automatic measurement, let us digitize a sine wave. Here
it will be more convenient to use Mode 2 of the ADC. If ST is tied high, then
a conversion will start whenever RD goes low. After the conversion, the new
values will automatically be updated to the outputs. See for instance Figure 12
in the datasheet.
To drive RD, we can use a DIO pin with the digital writer in the “Alternating
1/0’s” configuration, in which the bits automatically toggle at about 7 Hz. Drive
the input with a 0.2 Hz sine wave, with 1 Vpp amplitude and 0.6 V offset.
Observe the digital outputs on the Digital Reader. The output changes too fast
to track directly, but as the input signal oscillates up and down, you should see
the bit pattern shift from the left to the right. If we wanted to take the trouble,
it would be simple to store such data into a RAM chip for later retrieval.
12.7
Nyquist Sampling Theorem
When converting between digital and analog values, the Nyquist Sampling Theorem provides important guidance on the relation between signal bandwidth and
sampling frequency. It states that in order to accurately encode a signal of frequency f , the wave form must be sampled at a frequency of at least 2f . Thus
if your signal contains frequency components up to 10 kHz, your ADC/DAC
system must run at at least 20 kHz. If the sampling rate is slower than this,
the digitized wave form will be inaccurate.
We can use the AD7569 chip to see this effect in action. We will start with an
analog sine wave and digitize it. If the sample rate is too low, Nyquist indicates
that our digitized version will be erroneous. It is hard to tell this by looking at
the digital values, however, so we will instead try to recreate the analog signal
with the ADC. If there are no errors, the initial and final wave forms should be
similar. We shall observe what happens when this is not the case.
The 7 Hz trigger signal from the Digital Writer is to slow to be convenient
here. So first, build a circuit to generate your own trigger using a 7555 timer
chip, as in Lab 11. Pick a resistor/capacitor pair to give a clock frequency
between 50 kHz and 100 kHz. Measure this frequency using your scope.
Using the DAC and ADC together is relatively straightforward. The ADC
puts its results on the data bus shortly after the RD signal drops low, and holds
them there until the signal goes high. The DAC takes it’s values from the bus
when the WR signal goes high. So if we wire RD and WR together, then the
DAC will always have the current value available when needed. The data pins
can be simply left open.
This scheme is not really ideal because it relies on a logic race. In practice,
the DAC needs to have its inputs held on the bus for about 10 ns after the
WR signal rises, because it takes that long to transfer the data into its internal
105
12.7 Nyquist Sampling Theorem
12 DAC/ADC
register. On the other hand, the ADC takes about 10 ns to clear the bus after
the RD signal goes high. So our scheme will only work if the clear time of the
ADC is a little longer than the hold time of the DAC. In fact, it is. A better
design would not leave this to chance, but would instead delay the RD signal
slightly by, for instance, passing it through two inverters before applying it to
the chip. For simplicity we won’t bother with that here.
To implement this, apply the signal from your 7555 timer chip to both the
RD and WR pins. (Make sure the ST pin is still held high.) Drive the ADC
input with a sine wave with 1 Vpp amplitude, and monitor both the input and
the output on the scope. Start with an input frequency of about 1 kHz. You
should see the output follows the input nicely.
To understand the Nyquist phenomenon, start by observing the output wave
only, using it as your trigger source. This is appropriate, because you would not
normally have the input signal available when you are later trying to reconstruct
it from the digitized data. (For instance, if you digitally recorded a music
concert, you would not have the original analog sound signal available when
you later tried to play back your recording.) Observe and describe the signal
as you gradually increase the input wave frequency. The signals will probably
be clearest if you adjust the trigger level to near the top (or bottom) of the
wave form. You can locate these points as the edges of the range over which the
scope triggers. Does the signal still look like a sine wave as you approach and
then exceed half the timer frequency? What happens if the input frequency is
close to the timer frequency?
To help see what is going on, display the input and output signals together
on the scope. Keep using the output signal for the trigger, however. Sweep over
the input frequencies again. It should be clear that near the Nyquist frequency,
the samples occur at basically random times within the wave form, leading to
a jumbled output signal. Can you explain why the output appears as it does
when the input frequency is near the timer frequency?
Finally, change the scope to trigger on the input signal. In this configuration, does anything special seem to happen as you pass through the Nyquist
frequency? By using the input signal as a reference, the scope is able to sort
the jumbled output signal levels appropriately, so that it looks like the output
is more or less correct. What do you observe at the timer frequency now?
The fact that an under-sampled high frequency signal is reconstructed at a
lower frequency is called aliasing. It can be a source of confusion, since it causes
spurious signals to occur at frequencies you don’t expect. The best solution is to
always use a low-pass filter on the input to an ADC so that signal components
above the Nyquist frequency are attenuated away rather than aliased.
Once you have completed the lab, clean up all the components and your
station.
106
13
Microcontrollers
A microcontroller is a tiny computer system, complete with microprocessor,
memory, and a variety of input/output channels including analog converters.
The microcontroller is programmed using a high-level language like C or Basic,
via a connection to a standard desktop or laptop computer. Microcontrollers
are relatively inexpensive and can be a good solution to an electronics problem
that would otherwise involve constructing a complex circuit.
This lab will require two days.
Reading: HH section 10.01 (pgs. 673–678),
mbed “tour” http://mbed.org/handbook/Tour
13.1
The mbed Microcontroller
There are a wide variety of microcontrollers available, with many different programming requirements. The mbed controller we will be exploring is based on
the NXP LPC1768 chip. The emphasis of the mbed system is on ease of use.
The controller attaches to a standard breadboard to provide electronic access,
it receives power and programming via a USB cable to a host computer, and
programs are written and compiled in a simple web-based interface.
To set up the controller, carefully install it into your ELVIS breadboard. It
fits best if you use two adjacent breadboard columns (from socket B to socket
I), rather than straddling a bus column (the +/− connections.) The USB port
should be at the top. The mbed board is large and somewhat delicate, so be
careful to apply gentle and even pressure while inserting it.
Plug the USB cable into the port on the mbed board and one of the ports on
the side of your computer monitor. The Status LED on the mbed board should
illuminate, another LED should blink, and your computer should interpret the
controller as a flash drive (typically E:). To load a program into the controller, it
is simply copied or saved onto the flash drive. When the controller is connected,
or when the Reset button in the center of the board is pushed, the controller
automatically runs the newest program in its memory. The E: drive should
currently contain just one program, “HelloWorld LPC1768”, which is causing
the LED to flash. The other file in the drive, MBED.HTM, can be used to set
up an account for the web-based compiler.
In this case, a generic account for your station has already been set up. To
access it, point your web browser to http://mbed.org/, and go to the Login link
at the top right. If your station number is X, enter the user name UVA3150X
and password physics*X. After logging in, click on the Compiler link, also at
the top right. This takes you to the compiler application. The mbed controller
107
13.2 Digital Inputs and Outputs
13 MICROCONTROLLERS
is programmed in C++, but the programs we will be writing won’t involve any
complicated language elements.
The Program Workspace panel at the left shows the programs you have
written. Right now, there should only be one, HelloWorld. Click on it and go
to the main.cpp file. This shows the program listing, which should be fairly
self-explanatory. Modify the code to use LED2 rather than LED1, and change
the wait times to make the LED blink twice as fast. Compile the new code by
pressing the Compile button in the center of the toolbar, and save the resulting
file to the E: drive with the same name. Once compilation is complete and the
Status light returns to steady illumination, push the Reset button. Describe
the results in your report.
Note that the DigitalOut variable type and the wait command are not
standard C++, but are included as part of the mbed library. The various
special mbed functions are described in the Handbook section of the website.
In a separate browser tab, find the Handbook and look up the wait command.
What are the units of the wait time?
The myled variable is particularly interesting. It acts, in many ways, as
a function itself. When you assign a value to myled, you are really calling a
routine in the mbed library, which directs the hardware on the chip to set the
referenced LED appropriately. If you haven’t seen this kind of thing before, it
is an example of object-oriented programming. Properly, myled is an object
of the class DigitalOut, and consists of a set of functions and variables that
work together to implement the LED control. When done correctly, this type
of programming is transparent and easy to use, as you have hopefully seen here.
13.2
Digital Inputs and Outputs
The HelloWorld program shows one type of digital output, the LED displays.
More generally, most of the controller pins can be used as either digital inputs or
outputs. The possible uses for the various pins are summarized on the small card
included in the controller box, or online under http://mbed.org/handbook/mbedNXP-LPC1768. All of the blue pin numbers can be used as either digital inputs
or outputs. To configure pin 30 as an output, add the line
DigitalOut q(p30);
to the ‘preamble’ section immediately prior to the int main declaration. This
defines a variable q which is bound to the the stated pin. You can read about
the DigitalOut declaration in the Handbook.
In the main function of the program, replace the LED code with a routine
to toggle q:
q = 0;
while(1) {
q = !q;
wait(5e-5);
}
108
13 MICROCONTROLLERS
13.2 Digital Inputs and Outputs
Download and run the code, and observe the output of pin 30 on your scope.
Use pin 1 as ground, and attach it to the ELVIS ground as well. Do you observe
a 10 kHz square wave as expected? What voltage levels are used for logical
high and low? Remove the wait statement so that the signal toggles as fast as
possible, and observe it with a 10× scope probe. What is the resulting output
period? How does it compare to the maximum speed of a typical TTL gate chip
(as you measured in Lab 9)? In general, the main limitation of microcontrollers
compared to conventional circuits is reduced speed.
To configure a pin as a digital input, add the line
DigitalIn fgen(p29);
to your preamble. Implement a NOT gate with the simple code
while(1) {
q = !fgen;
}
Hook pin 29 up to the Sync output of your function generator, and observe both
it and pin 30 on your scope. While you run the program, does pin 30 act as the
inversion of pin 29?
For a more complicated example, use the wait function to implement a
triggered pulse generator. Consider this code, which implements a 100 µs pulse:
q = 0;
while(fgen==1) {};
while(fgen==0) {};
q = 1;
wait(100e-6);
q = 0;
What kind of input signal on fgen will trigger the pulse to occur? Implement
this code inside an infinite loop, and observe the output when applying a 1 kHz
input signal. Suppose instead that when a falling edge is detected, the output
should stay low for 50 µs and then produce a pair of 20 µs pulses separated by
a 10 µs delay. Modify your program to implement this and note your results.
Multiple input and output bits can be controlled together with the BusIn
and BusOut variables, which are again described in the Handbook. Add such a
variable with the declaration
BusIn nibble(p22,p23,p24,p25);
(A ‘nibble’ is conventionally 4 bits, or half a byte.) By using the command
wait(nibble*1e-5);
you can have the duration of the delay following the trigger set to be 10 µs
times the decimal value of nibble. For example, if nibble = 1001bin = 9dec ,
109
13.3 Arbitrary Waveform Generator
13 MICROCONTROLLERS
the output will stay low for 90 µs after an edge is detected, and then produce
the pair of 20 µs pulses. Attach pins 22 through 25 to the ELVIS Digital Writer
outputs, and measure the delay vs. set value for a few cases (including nibble
= 0). Which of the four nibble pins is the most significant bit, and which is the
least significant?
This should give you a taste of the capabilities of the microcontroller for
digital logic. As long as the speed is sufficient, microcontrollers make digital
design fairly trivial. Of course, your ‘HelloWorld’ program no longer has a very
appropriate name. In the Compiler, right click on the program and change its
name to ‘DigitalFun’ instead. Your online programs will be checked along with
your lab report, so make sure to save everything when instructed, and leave your
programs in a working state. Comments in the program files are not required,
but would be useful in places where you did anything interesting or tricky.
13.3
Arbitrary Waveform Generator
The mbed microcontroller is also useful for analog applications. As a first
example, you will implement an arbitrary waveform generator. This is a device
like a function generator, except that the output waveform can be specified as
desired. It can be useful for controlling servomechanisms and other complicated
processes.
Start by creating a new program. Click the New button in the toolbar of the
Compiler. Name the new program ‘Waveform.’ When you go to the main.cpp
listing, you will notice that the HelloWorld program is provided as a default
skeleton to start from.
The first thing we will need for the waveform generator is a DAC. As the
mbed summary card indicates, only one pin can be used for an analog output
signal, pin 18. To configure that pin, add the line
AnalogOut signal(p18);
in the preamble section. This defines a variable signal which is bound to the
DAC function of pin 18. You can read about the AnalogOut declaration in the
Handbook. It works similarly to how the digital variables worked. For example,
replace the contents of the main function with the line
signal = 0.5;
Compile and run your program, and monitor the voltage on pin 18 with your
DMM. Again, use the GND pin as your ground reference. An AnalogOut variable can be assigned any floating-point value between 0 and 1, and produces a
voltage output equal to the variable’s value times a reference voltage of 3.3 V.
Check and record the DAC output for several values of signal. Does it behave
as expected? How accurate is it? Is the smallest voltage increment you can
produce consistent with the specified 10-bit resolution?
For an arbitrary waveform generator, we wish to implement an output voltage V = f (t) for some specified function f of time t. This requires a way to
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13 MICROCONTROLLERS
13.3 Arbitrary Waveform Generator
track and determine the time more accurately that we can do with wait. The
easiest way to achieve this is with the mbed Timer class. Declare a Timer object
t by adding the line
Timer t;
to your progam’s preamble. Look up the Timer functions in the Handbook, and
figure out how to start, reset, and read the timer. Here the output will be a
periodic function, so introduce a floating point period variable that is assigned
a value at the start of the program. To start, use a 1 ms period.
A simple way to control the timing is with a while loop:
t.reset();
while(t.read()<period) {
signal = t.read()/period; /* The function f(t) */
}
where here the signal is a simple sawtooth ramp. This method isn’t perfect since
the actual period can vary by the time required for one output update, but this
is acceptable when the period is long compared to the update time. Implement
this scheme, using an infinite outer loop to repeat each period. For convenience,
also implement a sync-type signal to serve as a scope trigger: Define pin 30 as
a Digital Ouput object sync and toggle its value between high and low at the
start of each period. Use this and monitor the DAC output on your scope.
Once you have a working program, observe its performance for a range of
periods. Does a period of 100 s seem to function correctly? (How can you
measure this?) When you make the period short, on the order of 100 µs, you
should be able to see discrete steps in the output on your scope corresponding
to the finite DAC update time. How long is the update time? What is the
discrepancy between the specified and actual waveform periods?
Try some more complicated mathematical functions, bearing in mind that
the signal value must be between zero and one. A list of functions available in the
C math library can be found at http://en.wikipedia.org/wiki/Math.h. Both the
‘Pre-C99’ and ‘C99’ functions are available. Craft a few interesting waveforms
and note them in your report. For each waveform, find the output update
time and deduce the amount of time required to perform the mathematical
calculation. You should see that for complicated functions, the calculation time
becomes a significant burden.
Another interesting function is the random number generator rand(). Implement it using the code
signal = rand()/(1.0*RAND_MAX);
which produces a random value between zero and one. Run this code and note
your observations. A device that produces a random signal like this is called a
noise generator, and finds a variety of applications.
111
13.4 LCD Display
13 MICROCONTROLLERS
Note that the calculation-time limit to the update speed can be remedied by
precalculating the required values and storing them in an array. While running,
the waveform generator can simply read the values from the array and thus run
at its maximum rate. This technique can also be used to make the waveform
period more precise.
13.4
LCD Display
The AnalogOut and DigitalOut objects are two ways for the microcontroller
to generate output, but text output is also often convenient. Such output can
either be displayed on an electronic display module or transmitted to the host
computer. We shall investigate the display module first. A typical LCD module
is included in the mbed controller box. It is manufactured by Lumex, part
number S01602DTR. It can display 2 lines of text with 16 characters per line,
and is therefore commonly referred to as a 16 × 2 display.
Functions for handling the display interferace are not built into the mbed
compiler. However, a great variety of special-purpose libraries are available
through the compiler website. We will use the Text LCD project by Simon
Ford.
Start by creating a new program on the compiler page, and call it ‘MyLCD.’
Then click the Import button in the toolbar. Once the import screen loads,
click on the Libraries tab. In the search box at the bottom of the screen, enter
“TextLCD Ford.” The desired library should appear. Select it and click the
Import button at the top right. This imports the TextLCD library into your
program. To use it with your code, add the line
#include "TextLCD.h"
at the top of your program.
We will modify the wiring setup slightly from that described on the web
page. First, identify the pin numbers on the LCD module; they are labeled
on the back of the card. Numbers 1 and 14 indicate the corresponding pins.
Insert the module into your breadboard and hook it up to the mbed controller
as shown in Table 1. Given these pin connections, an LCD object must be
declared with the parameters
TextLCD lcd(p10, p12, p14, p15, p16, p17);
Once this is complete, use the cookbook example to display a message on
your LCD module. Note that you can use the newline character \n to extend
your message across both lines. Convince yourself that the display works as
claimed, and describe your observations in your report.
13.5
Voltmeter
You can use the LCD display along with the microcontroller’s analog input
capability to construct a simple digital voltmeter. Create a new program ‘Volt112
13 MICROCONTROLLERS
LCD pin
1
2
3
4
5
6
7–10
11
12
13
14
mbed pin
GND
Vu
1k resistor to GND
p10
GND
p12
no connection
p14
p15
p16
p17
13.5 Voltmeter
Function
Ground
5 V supply
Contrast control
Register Select
R/W
Enable
Data
Data
Data
Data
Table 1: Pin connections for LCD module. The first column gives the LCD pin
number, the second column gives the mbed pin, and the third column describes
the function.
meter’ and import the TextLCD code just as you did above. In the preamble
to your program, declare an analog input channel using
AnalogIn vin(p19);
You can read about AnalogIn in the Handbook. It works much like the AnalogOut class you encountered above. In the main routine, set up an infinite
loop:
while(1) {
lcd.printf("V = %f\n\n",3.3*vin);
wait(0.5);
}
(If you are unfamiliar with the printf command, you can find a description on
Wikipedia.)
This will continually display the measured voltage on the LCD. To test it,
hook pin 19 input up to the ELVIS VPS positive supply through a 1 kΩ resistor,
as shown in Fig. 13.1. Bear in mind that maximum readable voltage is 3.3 V,
and to avoid damage don’t let the input exceed 5 V. How well does the reading
on the LCD disply agree with the VPS setting? If the ADC does not seem to
be working, you can try using pins 18 or 20 instead.
The LCD reading probably fluctutates due to circuit noise. This can be
clarified by observing the underlying digital signal. The mbed uses a 12 bit
Figure 13.1: Attaching an input to the mbed ADC.
113
13.6 Communication with PC
13 MICROCONTROLLERS
ADC, so the floating point value of vin should really be considered as a scaled
integer. The range from 0 to 1 corresponds to 212 = 4096 different digital values.
To display them directly, modify your code to
lcd.printf("V = %f\n\n",4095*vin);
(Why do you multiply by 4095 rather than 4096?) What do you observe when
you run the program? Try to characterize the fluctuations you observe.
It is useful to know how long it takes to acquire an ADC sample. Modify your
program to determine this by looping over 10,000 samples and measuring the
elapsed time with a timer. Don’t update the LCD during this loop, since that
would add to the time required. Instead, define a new floating point variable,
x, and force an ADC conversion using x = vin. At the end, display the elapsed
time on the LCD module and calculate the time per measurement.
If you now modify your program to calculate the average all 10,000 samples
and display the mean value, are the fluctuations reduced?
Leave the LCD display set up, you will use it again below.
13.6
Communication with PC
If you want to acquire a stream of data and save it on a computer, the LCD
display is not adequate. Instead, the microcontroller can communicate with
a computer through a RS-232 connection. Here ‘RS-232’ is a simple serial
communications protocol that most computers support. In the mbed system,
it has been conveniently implemented through the USB cable, but in general it
would require a separate cable hooked up to the computer’s serial port.
To test the communication routines, create a new program called ‘Communicate.’ In the preamble, insert a declaration
Serial pc(USBTX, USBRX);
This establishes serial communication channel pc implemented through the USB
connection. Writing to the channel is accomplished with the pc.printf() command and reading from it with pc.scanf(), which behave like the ordinary C
functions. Once again, you can find more details in the Handbook. For now,
simply add a line
pc.printf("Hello World\n");
to your program.
You also need to set up your computer to listen to the serial channel. This
can be done with a variety of terminal programs. Here we will use PuTTY. Note
that version 0.6 or higher is required; if this is not available, TeraTerm can be
used as well. Instruction for this, and for setting up a new mbed controller, can
be found in Appendix B.
You should, however, be able to simply locate PuTTY on your pc and run it.
In the Session screen, select a Serial connection and enter COM3 for the serial
114
13 MICROCONTROLLERS
13.7 Multi-Channel Analyzer
line. Leave the connection speed at 9600 baud. Then go to the Terminal screen
and select “Implicit CR in every LF,” “Implicit LF in every CR,” and “Local
echo: Force on.” Press Open and a terminal screen should appear. When you
run your program on the controller, does the message display on the PuTTY
terminal?
To demonstrate communication from the pc to the controller, write a program that echos a line typed on the computer to the LCD display, using
char text[16];
while(1) {
pc.scanf("%s",text);
lcd.printf("%s\n\n",text);
}
(You will of course need to set up a TextLCD object first.) Note that the LCD
display does not automatically clear displayed characters, so if you write a long
word followed by a short one, the end of the long word will still be present.
This can be fixed by calling the lcd.cls() command prior to lcd.printf. Try
writing a few messages, exploring the behavior produced by long words, spaces,
back spaces, and other atypical characters. Describe your observations in your
report.
13.7
Multi-Channel Analyzer
The final microcontroller project that we will implement is a multi-channel
analyzer. This is a type of sampling voltmeter, which obtains many values and
produces a histogram of their distribution. For instance, the data in Fig. 13.2
shows the result of 10,000 measurements sorted into 100 bins. Each bin’s value
shows the number of times that a measurement was within the corresponding
voltage range. Multi-channel analyzers are most often useful for characterizing
time-varying but non-periodic signals. Here, however, we will simply use our
function generator as a signal source.
You have seen already most the tools needed to write an MCA program on
the microcontroller. Store the bin values in an array int counts[100]; which
will need to be initialized to zeros using, for example
for(n=0;n<100;++n) counts[n]=0;
For the input, set up an AnalogIn object on pin 19. The main part of the
program should be a loop over S samples, with a delay time T between each
sample. To sort each sample into the correct bin, use
d = floor(vin*100);
++counts[d];
Once all the samples are accumulated, print out all 100 bin values to the serial
channel. It is helpful to precede the output by a header line so that you can find
115
13.8 Wrap Up
13 MICROCONTROLLERS
600
Number of Occurences
500
400
300
200
100
0
0
0.33
0.66
0.99
1.32
1.65
1.98
2.31
2.64
2.97
3.3
Signal level (V)
Figure 13.2: Data produced by a multichannel analyzer.
the begining of the data stream on the terminal. For futher convenience, turn
on an LED while the program is acquiring data and turn it off when acquistion
is done.
To test your program, set the number of samples to 100 and the sample
time to 0.7 ms. If you run it with no input connected, you should find most
of the counts in the lowest few bins. Then take the input from your function
generator, running a 1 Vpp sine wave at 100 Hz with a 1 V offset. Now the
counts should be spread over the mid-range bins.
When everything seems to be working, increase the number of samples to
10000. On your computer, copy and paste the output values into your report
and make a column graph as in Fig. 13.2. Compare the amplitude distributions
you observe for the function generator set to give a constant value, a sine wave,
a triangle wave, and a square wave. Do the distibutions appear as you expect?
How easy is it to distinguish the different wave forms? Does anything change
if the input period is made to be a multiple of the sampling time? Would you
expect anything to change?
13.8
Wrap Up
Before finishing, make sure that all six of your programs are present in the online
compiler directory: DigitalFun, Waveform, MyLCD, Voltmeter, Communicate,
and MCA.
To turn the mbed module off, just unplug the USB cable. Remove the LCD
module, USB cable, and mbed card and put them back in the controller box.
Be particularly careful when removing the mbed card to avoid stressing it. If
116
13 MICROCONTROLLERS
13.8 Wrap Up
necessary, ask the instructor for help.
Since this is the final lab of the semester, make sure to clean up your station
and put all electrical components away.
117
13.8 Wrap Up
13 MICROCONTROLLERS
118
A EXCEL PLOTS
A
Excel Plots
For your lab reports, you will need to prepare data plots using Excel. Here are
the instructions for doing so:
A.1
Creating a Chart
1. Use the mouse to select the data you want to plot. The data should be in
columns, and the leftmost column will be taken as the x-axis. If the the data
are not in adjacent columns, select one set of values at at time while holding
down the Ctrl key.
2. Under the Insert menu, select Chart. For the chart type, normally select
XY (Scatter) and then chose a subtybe depending on whether you want the
plot to use lines, curves, or points.
3. Click Next, and under the Series tab, give your dataset a name.
4. Click Next, and give your chart a title and axis labels.
5. Click Finish, and your chart will appear.
A.2
Modifying a Chart
To add another dataset to a chart, right click on the chart area and select Source
Data. Under the Series tab, click Add. Give the new dataset a name. Click in
the X Values box and then select the x data on the worksheet using the mouse.
Click in the Y Values box, delete the default “={1}” entry, and then select the
y data on the worksheet. Click OK and the new data will be added.
All graphs should have titles and appropriately labeled axes. To set these,
right click on the chart and select Chart Options.
To modify the axis scales, double click on the axis you want to change.
Under the Scale tab, you can change the axis range and switch between linear
and log scales. Sometimes the data will lie on top of an axis, making it hard
to click. You can also modify the axis using the Chart toolbar, which appears
somewhere on the screen when a chart is selected. In the toolbar, select the
axis you want to change and click the Format Axis button, which looks like a
hand pointing at a piece of paper.
It is important to choose a line type or marker style that makes the information in your plot clear. In general, use marker points when you have a small
number of values or when they have obvious measurement noise. Use straight
lines between points when you have many points and they are not very noisy.
Avoid using curves between points, as they can be misleading.
To change the data marker style, double click on a data point. You can
change the color or style, add error bars, and choose which dataset is plotted on
top. Sometimes two data sets are on top of each other, and it is hard to select
the one you want. You can also use the Chart toolbar: select the data series
you want and click the Format Data Series icon.
119
A.3 Fitting Data
A.3
A EXCEL PLOTS
Fitting Data
Excel provides some support for fitting data, which will occasionally be useful.
With an existing chart selected, go to the Chart menu and select Add Trendline.
A box comes up allowing you to select the type of fit. On the Options tab, you
should normally select the “Display Equation on Chart” box. Click OK to close
the box and add the fit.
A.4
Excel 2007
The lab computers use the 2003 version of Excel. If you are using a newer
version on your own computer, the process is a little different. To create a
chart, click on the Insert tab of the ribbon. The different chart types are listed
in the Charts toolbar, and the subtypes form a drop down menu. When you
select a chart, the Chart Tools tab appears in the ribbon, and displays the
various things you can change. Adding a new dataset is done using the Select
Data tool under the Design tab. Trendlines can be added via the Layout tab.
120
B SETUP SERIAL COMMUNICATIONS FOR MBED
B
Setup Serial Communications for mbed
To set up the serial communication channel for a new mbed controller (Section
13.6), follow these instructions:
1. Plug in the mbed controller
2. Download the driver installer from
http://mbed.org/media/downloads/drivers/mbedWinSerial_16466.exe
3. Run the installer. To do this, you must be logged on with Administrator
privileges.
4. Go to the Device Manager, and check which COM channel was created.
Normally this is COM3, but sometimes it is a higher number.
5. Either PuTTY or TeraTerm can be used for communication.
PuTTY Settings (version 0.61):
Session:
Connection type: Serial
Connection: COM3
Speed: 9600
Terminal: Implicit CR in every LF? Yes
Implicit LF in every CR? Yes
Local echo: Force On
TeraTerm (version 4.71):
Connection: Serial
COM3
Terminal:
Receive: LF
Transmit: CR+LF
Local Echo: On
(The above settings assume the mbed is using the COM3 port.)
121
B SETUP SERIAL COMMUNICATIONS FOR MBED
122
C LF411 DATASHEET
C
LF411 datasheet
LF411
Low Offset, Low Drift JFET Input Operational Amplifier
General Description
Features
These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply
current yet maintain a large gain bandwidth product and fast
slew rate. In addition, well matched high voltage JFET input
devices provide very low input bias and offset currents. The
LF411 is pin compatible with the standard LM741 allowing
designers to immediately upgrade the overall performance of
existing designs.
These amplifiers may be used in applications such as high
speed integrators, fast D/A converters, sample and hold
circuits and many other circuits requiring low input offset
voltage and drift, low input bias current, high input impedance, high slew rate and wide bandwidth.
n
n
n
n
n
n
n
n
n
n
n
Typical Connection
Connection Diagrams
Internally trimmed offset voltage:
Input offset voltage drift:
Low input bias current:
Low input noise current:
Wide gain bandwidth:
High slew rate:
Low supply current:
High input impedance:
Low total harmonic distortion:
Low 1/f noise corner:
Fast settling time to 0.01%:
0.5 mV(max)
10 µV/˚C(max)
50 pA
0.01 pA/√Hz
3 MHz(min)
10V/µs(min)
1.8 mA
1012Ω
≤0.02%
50 Hz
2 µs
Metal Can Package
00565505
Note: Pin 4 connected to case.
Top View
Order Number LF411ACH
or LF411MH/883 (Note 11)
See NS Package Number H08A
00565501
Dual-In-Line Package
Ordering Information
LF411XYZ
X indicates electrical grade
Y indicates temperature range
“M” for military
“C” for commercial
Z indicates package type
“H” or “N”
00565507
Top View
Order Number LF411ACN, LF411CN
See NS Package Number N08E
BI-FET II™ is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS005655
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123
LF411 Low Offset, Low Drift JFET Input Operational Amplifier
August 2000
LF411
C LF411 DATASHEET
Absolute Maximum Ratings (Note 1)
H Package
Tjmax
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
LF411A
LF411
± 22V
± 38V
± 18V
± 30V
Supply Voltage
Differential Input Voltage
θjA
N Package
150˚C
115˚C
162˚C/W (Still Air)
120˚C/W
65˚C/W (400
LF/min
Air Flow)
θ jC
Input Voltage Range
20˚C/W
Operating Temp.
± 19V
(Note 2)
± 15V
Range
Output Short Circuit
(Note 4)
(Note 4)
Storage Temp.
Duration
Continuous Continuous
−65˚C≤TA≤150˚C −65˚C≤TA≤150˚C
Range
Lead Temp.
H Package
N Package
(Soldering,
10 sec.)
670 mW
670 mW
ESD Tolerance
Power Dissipation
(Notes 3, 10)
DC Electrical Characteristics
Symbol
Parameter
260˚C
260˚C
Rating to be determined.
(Note 5)
Conditions
LF411A
Min
LF411
Typ
Max
Min
Units
Typ
Max
VOS
Input Offset Voltage
RS=10 kΩ, TA=25˚C
0.3
0.5
0.8
2.0
mV
∆VOS/∆T
Average TC of Input
RS=10 kΩ (Note 6)
7
10
7
20
µV/˚C
25
100
25
Offset Voltage
IOS
Input Offset Current
(Note 6)
VS= ± 15V
Tj=25˚C
(Notes 5, 7)
Tj=70˚C
VS= ± 15V
Tj=25˚C
(Notes 5, 7)
Tj=70˚C
2
Tj=125˚C
IB
Input Bias Current
25
50
Tj=125˚C
50
Tj=25˚C
AVOL
Large Signal Voltage
VS= ± 15V, VO= ± 10V,
Gain
RL=2k, TA=25˚C
Over Temperature
25
200
VO
Output Voltage Swing
VS= ± 15V, RL=10k
± 13.5
VCM
Input Common-Mode
± 12
± 16
50
Voltage Range
200
nA
25
nA
200
pA
4
nA
50
nA
Ω
200
V/mV
15
200
V/mV
± 12
± 11
± 13.5
V
25
+19.5
pA
2
1012
1012
Input Resistance
Common-Mode
50
4
RIN
CMRR
200
100
−16.5
+14.5
V
−11.5
V
RS≤10k
80
100
70
100
dB
(Note 8)
80
100
70
100
dB
Rejection Ratio
PSRR
Supply Voltage
Rejection Ratio
IS
Supply Current
1.8
AC Electrical Characteristic
Symbol
Parameter
2.8
1.8
3.4
mA
(Note 5)
Conditions
LF411A
Min
Typ
LF411
Max
Min
Typ
Units
Max
SR
Slew Rate
VS= ± 15V, TA=25˚C
10
15
8
15
V/µs
GBW
Gain-Bandwidth Product
VS= ± 15V, TA=25˚C
3
4
2.7
4
MHz
en
Equivalent Input Noise Voltage
TA=25˚C, RS=100Ω,
f=1 kHz
in
Equivalent Input Noise Current
TA=25˚C, f=1 kHz
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124
25
25
0.01
0.01
C LF411 DATASHEET
Parameter
LF411
AC Electrical Characteristic
Symbol
(Note 5) (Continued)
Conditions
LF411A
Min
THD
Total Harmonic Distortion
AV=+10, RL=10k,
VO=20 Vp-p,
BW=20 Hz−20 kHz
Typ
LF411
Max
Min
< 0.02
Typ
Units
Max
< 0.02
%
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits.
Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage.
Note 3: For operating at elevated temperature, these devices must be derated based on a thermal resistance of θjA.
Note 4: These devices are available in both the commercial temperature range 0˚C≤TA≤70˚C and the military temperature range −55˚C≤TA≤125˚C. The
temperature range is designated by the position just before the package type in the device number. A “C” indicates the commercial temperature range and an “M”
indicates the military temperature range. The military temperature range is available in “H” package only.
Note 5: Unless otherwise specified, the specifications apply over the full temperature range and for VS= ± 20V for the LF411A and for VS= ± 15V for the LF411. VOS,
IB, and IOS are measured at VCM=0.
Note 6: The LF411A is 100% tested to this specification. The LF411 is sample tested to insure at least 90% of the units meet this specification.
Note 7: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj. Due to limited
production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient
temperature as a result of internal power dissipation, PD. Tj=TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is
recommended if input bias current is to be kept to a minimum.
Note 8: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice, from
± 15V to ± 5V for the LF411 and from ± 20V to ± 5V for the LF411A.
Note 9: RETS 411X for LF411MH and LF411MJ military specifications.
Note 10: Max. Power Dissipation is defined by the package characteristics. Operating the part near the Max. Power Dissipation may cause the part to operate
outside guaranteed limits.
Typical Performance Characteristics
Input Bias Current
Input Bias Current
00565511
00565512
3
125
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LF411
C LF411 DATASHEET
Typical Performance Characteristics
(Continued)
Positive Common-Mode
Input Voltage Limit
Supply Current
00565513
00565514
Negative Common-Mode
Input Voltage Limit
Positive Current Limit
00565515
00565516
Negative Current Limit
Output Voltage Swing
00565517
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00565518
4
126
C LF411 DATASHEET
LF411
Typical Performance Characteristics
(Continued)
Output Voltage Swing
Gain Bandwidth
00565519
00565520
Bode Plot
Slew Rate
00565522
00565521
Undistorted Output
Voltage Swing
Distortion vs Frequency
00565523
00565524
5
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LF411
C LF411 DATASHEET
Typical Performance Characteristics
(Continued)
Open Loop Frequency
Response
Common-Mode Rejection
Ratio
00565525
00565526
Power Supply
Rejection Ratio
Equivalent Input Noise
Voltage
00565527
00565528
Open Loop Voltage Gain
Output Impedance
00565529
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00565530
6
128
C LF411 DATASHEET
LF411
Typical Performance Characteristics
(Continued)
Inverter Settling Time
00565531
Pulse Response
RL=2 kΩ, CL10 pF
Large Signal Inverting
Small Signal Inverting
00565541
00565539
Large Signal Non-Inverting
Small Signal Non-Inverting
00565542
00565540
7
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LF411
C LF411 DATASHEET
Pulse Response RL=2 kΩ, CL10 pF
(Continued)
Current Limit (RL=100Ω)
00565543
The LF411 will drive a 2 kΩ load resistance to ± 10V over the
full temperature range. If the amplifier is forced to drive
heavier load currents, however, an increase in input offset
voltage may occur on the negative voltage swing and finally
reach an active current limit on both positive and negative
swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to
ground.
Application Hints
The LF411 series of internally trimmed JFET input op amps
( BI-FET II™ ) provide very low input offset voltage and
guaranteed input offset voltage drift. These JFETs have
large reverse breakdown voltages from gate to source and
drain eliminating the need for clamps across the inputs.
Therefore, large differential input voltages can easily be
accommodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will force the output to a high state, potentially causing a
reversal of phase to the output. Exceeding the negative
common-mode limit on both inputs will force the amplifier
output to a high state. In neither case does a latch occur
since raising the input back within the common-mode range
again puts the input stage and thus the amplifier in a normal
operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output; however, if both
inputs exceed the limit, the output of the amplifier may be
forced to a high state.
The amplifier will operate with a common-mode input voltage
equal to the positive supply; however, the gain bandwidth
and slew rate may be decreased in this condition. When the
negative common-mode voltage swings to within 3V of the
negative supply, an increase in input offset voltage may
occur.
The LF411 is biased by a zener reference which allows
normal circuit operation on ± 4.5V power supplies. Supply
voltages less than these may result in lower gain bandwidth
and slew rate.
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A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) to AC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected
3 dB frequency of the closed loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately 6 times the expected 3 dB frequency, a lead capacitor should be placed
from the output to the input of the op amp. The value of the
added capacitor should be such that the RC time constant of
this capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
8
130
C LF411 DATASHEET
LF411
Typical Applications
High Speed Current Booster
00565509
PNP=2N2905
NPN=2N2219 unless noted
TO-5 heat sinks for Q6-Q7
9
131
www.national.com
LF411
C LF411 DATASHEET
Typical Applications
(Continued)
10-Bit Linear DAC with No VOS Adjust
00565532
where AN=1 if the AN digital input is high
AN=0 if the AN digital input is low
Single Supply Analog Switch with Buffered Output
00565533
www.national.com
10
132
C LF411 DATASHEET
LF411
Simplified Schematic
00565506
Note 11: Available per JM38510/11904
Detailed Schematic
00565534
11
133
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LF411
C LF411 DATASHEET
Physical Dimensions
inches (millimeters) unless otherwise noted
Metal Can Package (H)
Order Number LF411MH/883 or LF411ACH
NS Package Number H08A
Molded Dual-In-Line Package (N)
Order Number LF411ACN or LF411CN
NS Package Number N08E
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12
134
C LF411 DATASHEET
LF411 Low Offset, Low Drift JFET Input Operational Amplifier
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component is any component of a life
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can be reasonably expected to cause the failure of
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safety or effectiveness.
1. Life support devices or systems are devices or
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into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
135
C LF411 DATASHEET
136
D AD7569 DATASHEET
D
AD7569 datasheet
a
LC2MOS
Complete, 8-Bit Analog I/0 Systems
AD7569/AD7669
AD7569 FUNCTIONAL BLOCK DIAGRAM
FEATURES
2 ms ADC with Track/Hold
1 ms DAC with Output Amplifier
AD7569, Single DAC Output
AD7669, Dual DAC Output
On-Chip Bandgap Reference
Fast Bus Interface
Single or Dual 5 V Supplies
GENERAL DESCRIPTION
The AD7569/AD7669 is a complete, 8-bit, analog I/O system
on a single monolithic chip. The AD7569 contains a high speed
successive approximation ADC with 2 µs conversion time, a track/
hold with 200 kHz bandwidth, a DAC and an output buffer amplifier with 1 µs settling time. A temperature-compensated 1.25 V
bandgap reference provides a precision reference voltage for the
ADC and the DAC. The AD7669 is similar, but contains two
DACs with output buffer amplifiers.
AD7669 FUNCTIONAL BLOCK DIAGRAM
A choice of analog input/output ranges is available. Using a supply voltage of +5 V, input and output ranges of zero to 1.25 V
and zero to 2.5 volts may be programmed using the RANGE input pin. Using a ± 5 V supply, bipolar ranges of ± 1.25 V or
± 2.5 V may be programmed.
Digital interfacing is via an 8-bit I/O port and standard microprocessor control lines. Bus interface timing is extremely fast, allowing easy connection to all popular 8-bit microprocessors. A
separate start convert line controls the track/hold and ADC to
give precise control of the sampling period.
PRODUCT HIGHLIGHTS
The AD7569/AD7669 is fabricated in Linear-Compatible
CMOS (LC2MOS), an advanced, mixed technology process
combining precision bipolar circuits with low power CMOS
logic. The AD7569 is packaged in a 24-pin, 0.3" wide “skinny”
DIP, a 24-terminal SOIC and 28-terminal PLCC and LCCC
packages. The AD7669 is available in a 28-pin, 0.6" plastic
DIP, 28-terminal SOIC and 28-terminal PLCC package.
1. Complete Analog I/O on a Single Chip.
The AD7569/AD7669 provides everything necessary to
interface a microprocessor to the analog world. No external
components or user trims are required and the overall accuracy of the system is tightly specified, eliminating the need
to calculate error budgets from individual component
specifications.
2. Dynamic Specifications for DSP Users.
In addition to the traditional ADC and DAC specifications,
the AD7569/AD7669 is specified for ac parameters, including signal-to-noise ratio, distortion and input bandwidth.
3. Fast Microprocessor Interface.
The AD7569/AD7669 has bus interface timing compatible
with all modern microprocessors, with bus access and relinquish times less than 75 ns and write pulse width less than
80 ns.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
137
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
D AD7569 DATASHEET
AD7569/AD7669–SPECIFICATIONS
(V = +5 V 6 5%; V = RANGE = AGND
2
DAC SPECIFICATIONS1
DAC = AGNDADC = DGND = 0 V; RL = 2 kV, CL = 100 pF to AGNDDAC
unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
AD7569
J, A Versions3 AD7569
AD7669
K, B
J Version
Versions
AD7569
S Version
AD7569
T Version
Units
8
±2
±1
±1
8
±2
± 1/2
± 3/4
8
±3
±1
±1
8
±3
± 1/2
± 3/4
Bits
LSB typ
LSB max
LSB max
±2
± 2.5
± 1.5
±2
±2
± 2.5
± 1.5
±2
LSB max
LSB max
±2
± 2.5
±1 5
±2
±2
± 2.5
± 1.5
±2
LSB max
LSB max
±2
±3
±1
±2
±2
±4
±1
±3
LSB max
LSB max
STATIC PERFORMANCE
Resolution 4
Total Unadjusted Error 5
Relative Accuracy 5
Differential Nonlinearity 5
Unipolar Offset Error
@ +25°C
TMIN to TMAX
Bipolar Zero Offset Error
@ +25°C
TMIN to TMAX
Full-Scale Error 6 (AD7569 Only)
@ +25°C
TMIN to TMAX
Full-Scale Error 6 (AD7669 Only)
@ +25°C
TMIN to TMAX
DACA/DACB Full-Scale Error Match 6
(AD7669 Only)
∆Full Scale/∆VDD, TA = +25°C
∆Full Scale/∆VSS, TA = +25°C
Load Regulation at Full Scale
DD
SS
Conditions/Comments
Guaranteed Monotonic
DAC data is all 0s; VSS = 0 V
Typical tempco is 10 µV/°C for +1.25 V range
DAC data is all 0s; V SS = –5 V
Typical tempco is 20 µV/°C for ± 1.25 V range
VDD = 5 V
VDD = 5 V
±3
± 4.5
LSB max
LSB max
± 2.5
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
0.2
0.5
0.5
0.2
LSB max
LSB max
LSB max
LSB max
VDD = 5 V
VOUT = 2.5 V; ∆VDD = ± 5%
VOUT = –2.5 V; ∆V SS = ± 5%
RL = 2 kΩ to °/C
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio 5 (SNR)
Total Harmonic Distortion 5 (THD)
Intermodulation Distortion 5 (IMD)
44
48
55
46
48
55
44
48
55
46
48
55
dB min
dB max
dB typ
VOUT = 20 kHz full-scale sine wave with f SAMPLING = 400 kHz
VOUT = 20 kHz full-scale sine wave with f SAMPLING = 400 kHz
fa = 18.4 kHz, fb = 14.5 kHz with f SAMPLING = 400 kHz
ANALOG OUTPUT
Output Voltage Ranges
Unipolar
Bipolar
0 to +1.25/2.5
± 1.25/± 2.5
Volts
Volts
VDD = +5 V, VSS = 0 V
VDD = +5 V, VSS = –5 V
LOGIC INPUTS
CS, X/B,WR, RANGE, RESET, DB0–DB7
Input Low Voltage, V INL
Input High Voltage, V INH
Input Leakage Current
Input Capacitance 7
DB0–DB7
Input Coding (Single Supply)
Input Coding (Dual Supply)
0.8
2.4
10
10
0.8
2.4
10
10
0.8
2.4
10
10
0.8
2.4
10
10
V max
V min
µA max
pF max
VIN = 0 to VDD
Binary
2s Complement
7
AC CHARACTERlSTICS
Voltage Output Settling Time
Positive Full-Scale Change
Negative Full-Scale Change (Single Supply)
Negative Full-Scale Change (Dual Supply)
Digital-to-Analog Glitch Impulse 5
Digital Feedthrough 5
VIN to VOUT Isolation
DAC to DAC Crosstalk 5 (AD7669 Only)
DACA to DACB Isolation 5 (AD7669 Only)
2
4
2
15
1
60
1
–70
2
4
2
15
1
60
POWER REQUIREMENTS
VDD Range
VSS Range (Dual Supplies)
4.75/5.25
–4.75/–5.25
4
6
4.75/5.25
4.75/5.25
4.75/5.25
V min/V max For Specified Performance
–4.75/–5.25 –4.75/–5.25 –4.75/–5.25 V min/V max Specified Performance also applies to V SS = 0 V
for unipolar ranges.
VOUT = VIN = 2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V
13
13
13
mA max
Output unloaded
mA max
Outputs unloaded
VOUT = VIN = –2.5 V; Logic Inputs = 2.4 V; CLK = 0.8 V
4
4
4
mA max
Output unloaded
mA max
Outputs unloaded
1
1
1
1
IDD
(AD7569)
(AD7669)
ISS (Dual Supplies)
(AD7569)
(AD7669)
DAC/ADC MATCHING
Gain Matching 6
@ +25°C
TMIN to TMAX
13
18
2
4
2
15
1
60
1
1
2
4
2
15
1
60
1
1
µs max
µs max
µs max
nV secs typ
nV secs typ
dB typ
nV secs typ
dB max
% typ
% typ
Settling time to within ± 1/2 LSB of final value
Typically 1 µs
Typically 2 µs
Typically 1 µs
VIN = ± 2.5 V, 50 kHz Sine Wave
VIN to VOUT match with VIN = ± 2.5 V,
20 kHz sine wave
NOTES
1
Specifications apply to both DACs in the AD7669. VOUT applies to both VOUTA and VOUTB of the AD7669.
2
Except where noted, specifications apply for all output ranges including bipolar ranges with dual supply operation.
3
Temperature ranges as follows:
J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
4
1 LSB = 4.88 mV for 0 V to +1.25 V output range, 9.76 mV for 0 V to +2.5 V and ± 1.25 V ranges and 19.5 mV for ± 2.5 V range.
5
See Terminology.
6
Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar full-scale voltage is (FS – 1 LSB); ideal bipolar positive full-scale voltage is (FS/2 – 1 LSB)
and ideal bipolar negative full-scale voltage is –FS/2.
7
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
–2–
REV. B
138
D AD7569 DATASHEET
AD7569/AD7669
ADC SPECIFICATIONS
(VDD = +5 V 6 5%; VSS1 = RANGE = AGNDDAC = AGNDDAC = DGND = 0 V; fCLK = 5 MHz external unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.) Specifications apply to Mode 1 interface.
Parameter
AD7569
J, A Versions3
AD7669
J Version
AD7569
K, B
Versions
AD7569
S Version
AD7569
T Version
Units
8
±3
±1
±1
8
±3
± 1/2
± 3/4
8
±4
±1
±1
8
±4
± 1/2
± 3/4
Bits
LSB typ
LSB max
LSB max
±2
±3
± 1.5
± 2.5
±2
±3
± 1.5
± 2.5
LSB max
LSB max
Conditions/Comments
DC ACCURACY
Resolution3
Total Unadjusted Error4
Relative Accuracy4
Differential Nonlinearity4
Unipolar Offset Error
@ +25°C
TMIN to TMAX
Bipolar Zero Offset Error
@ +25°C
TMIN to TMAX
Full-Scale Error5
@ +25°C
TMIN to TMAX
∆Full Scale/∆VDD, TA = +25°C
∆Full Scale/∆VSS, TA = +25°C
±3
± 3.5
± 2.5
±3
±3
±4
± 2.5
± 3.5
LSB max
LSB max
–4, +0
–5.5, +1.5
0.5
0.5
–4, +0
–5.5, +1.5
0.5
0.5
–4, +0
–7.5, +2
0.5
0.5
–4, +0
–7.5, +2
0.5
0.5
LSB max
LSB max
LSB max
LSB max
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio4 (SNR)
Total Harmonic Distortion4 (THD)
Intermodulation Distortion4 (IMD)
Frequency Response
Track/Hold Acquisition Time7
44
48
60
0.1
200
46
48
60
0.1
200
44
48
60
0.1
300
45
48
60
0.1
300
dB min
dB max
dB typ
dB typ
ns typ
VIN = 100 kHz full-scale sine wave with fSAMPLING = 400 kHz6
VIN = 100 kHz full-scale sine wave with fSAMPLING = 400 kHz6
fa = 99 kHz, fb = 96.7 kHz with fSAMPLING = 400 kHz
VIN = ± 2.5 V, dc to 200 kHz sine wave
± 300
10
± 300
10
Volts
Volts
µA max
pF typ
VDD = +5 V; VSS = 0 V
VDD = +5 V; VSS = –5 V
See equivalent circuit Figure 5
ANALOG INPUT
Input Voltage Ranges
Unipolar
Bipolar
Input Current
Input Capacitance
LOGIC INPUTS
CS, RD, ST, CLK, RESET, RANGE
Input Low Voltage, VINL
Input High Voltage, VINH
Input Capacitance8
CS, RD, ST, RANGE, RESET
Input Leakage Current
CLK
Input Current
IINL
IINH
LOGIC OUTPUTS
DB0–DB7, INT, BUSY
VOL, Output Low Voltage
VOH, Output High Voltage
DB0–DB7
Floating State Leakage Current
Floating State Output Capacitance8
Output Coding (Single Supply)
Output Coding (Dual Supply)
CONVERSION TIME
With External Clock
With Internal Clock, TA = +25°C
POWER REQUIREMENTS
No Missing Codes
Typical tempco is 10 µV/°C for +1.25 V range; VSS = 0 V
Typical tempco is 20 µV/°C for + 1.25 V range; VSS = –5 V
VDD = 5 V
± 300
10
0 to +1.25/ +2.5
± 1.25/± 2.5
± 300
10
VIN = +2.5 V; ∆VDD = ± 5%
VIN = –2.5 V; ∆VSS = ± 5%
0.8
2.4
10
0.8
2.4
10
0.8
2.4
10
0.8
2.4
10
V max
V min
pF max
10
10
10
10
µA max
V IN = 0 to VDD
–1.6
40
–1.6
40
–1.6
40
–1.6
40
mA max
µA max
VIN = 0 V
VIN = VDD
0.4
4.0
0.4
4.0
0.4
4.0
0.4
4.0
V max
V min
ISINK = 1.6 mA
ISOURCE = 200 µA
10
10
10
10
10
10
Binary
2s Complement
10
10
µA max
pF max
2
1.6
2.6
2
1.6
2.6
2
1.6
2.6
µs max
µs min
µs max
2
1.6
2.6
fCLK = 5 MHz
Using recommended clock components shown in Figure 21.
Clock frequency can be adjusted by varying RCLK.
As per DAC Specifications
NOTES
1
Except where noted, specifications apply for all ranges including bipolar ranges with dual supply operation.
2
Temperature ranges are as follows: J, K versions; 0°C to +70°C
A, B versions; –40°C to +85°C
S, T versions; –55°C to +125°C
3
1 LSB = 4.88 mV for 0 V to +1.25 V range, 9.76 mV for 0 V to +2.5 V and ± 1.25 V ranges and 19.5 mV for +2.5 V range.
4
See Terminology.
5
Includes internal voltage reference error and is calculated after offset error has been adjusted out. Ideal unipolar last code transition occurs at (FS – 3/2 LSB). Ideal bipolar last code transition occurs at
(FS/2 – 3/2 LSB).
6
Exact frequencies are 101 kHz and 384 kHz to avoid harmonics coinciding with sampling frequency.
7
Rising edge of BUSY to falling edge of ST. The time given refers to the acquisition time, which gives a 3 dB degradation in SNR from the tested figure.
8
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
REV. B
–3–
139
D AD7569 DATASHEET
AD7569/AD7669–TIMING CHARACTERISTICS1 (See Figures 8, 10, 12; V
Parameter
DAC Timing
t1
t2
t3
t4
t5
ADC Timing
t6
t7
t8
t9
t10
t11
t12
t132
t143
t15
t16
t172
DD
= 5 V 6 5%; VSS = 0 V or –5 V 6 5%)
Limit at
258C (All Grades)
Limit at
TMIN, TMAX
(J, K, A, B Grades)
Limit at
TMIN, TMAX
(S, T Grades)
Units
Test Conditions/Comments
80
0
0
60
10
80
0
0
70
10
90
0
0
80
10
ns min
ns min
ns min
ns min
ns min
WR Pulse Width
CS, A/B to WR Setup Time
CS, A/B to WR Hold Time
Data Valid to WR Setup Time
Data Valid to WR Hold Time
50
110
20
0
0
60
0
60
95
10
60
65
120
60
90
50
130
30
0
0
75
0
75
120
10
75
75
140
75
115
50
150
30
0
0
90
0
90
135
10
85
85
160
90
135
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns max
ns max
ns max
ns max
ns max
ST Pulse Width
ST to BUSY Delay
BUSY to INT Delay
BUSY to CS Delay
CS to RD Setup Time
RD Pulse Width Determined by t 13.
CS to RD Hold Time
Data Access Time after RD; CL = 20 pF
Data Access Time after RD; CL = 100 pF
Bus Relinquish Time after RD
RD to INT Delay
RD to BUSY Delay
Data Valid Time after BUSY; CL = 20 pF
Data Valid Time after BUSY; CL = 100 pF
NOTES
1
Sample tested at +25°C to ensure compliance. All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
2
t13 and t17 are measured with the load circuits of Figure 1 and defined as the time required for an output to cross either 0.8 V or 2.4 V.
3
tl4 is defined as the time required for the data line to change 0.5 V when loaded with the circuit of Figure 2.
Specifications subject to change without notice.
a. High-Z to VOH
b. High-Z to VOL
a. VOH to High-Z
Figure 1. Load Circuits for Data Access Time Test
b. VOL to High-Z
Figure 2. Load Circuits for Bus Relinquish Time Test
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating Temperature Range
Commercial (J, K) . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Industrial (A, B) . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (S, T) . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
VDD to AGNDDAC or AGNDADC . . . . . . . . . . . . . –0.3 V, +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +14 V
AGNDDAC or AGNDADC to DGND . . . . –0.3 V, VDD + 0.3 V
AGNDDAC to AGNDADC . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 V
Logic Voltage to DGND . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
CLK Input Voltage to DGND . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT (VOUTA, VOUTB) to
AGND1DAC . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
VIN to AGNDADC . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V
NOTE
1
Output may be shorted to any voltage in the range V SS to VDD provided that the
power dissipation of the package is not exceeded. Typical short circuit current for
a short to AGND or V SS is 50 mA.
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other condition above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7569/AD7669 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. B
140
D AD7569 DATASHEET
AD7569/AD7669
NOTE:
The term DAC (Digital-to-Analog Converter) throughout the
data sheet applies equally to the dual DACs in the AD7669 as
well as to the single DAC of the AD7569 unless otherwise
stated. It follows that the term VOUT applies to both VOUTA and
VOUTB of the AD7669 also.
TERMINOLOGY
Total Unadjusted Error
Total unadjusted error is a comprehensive specification that includes internal voltage reference error, relative accuracy, gain
and offset errors.
Relative Accuracy (DAC)
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after allowing for offset and gain errors. For the bipolar output ranges,
the endpoints of the DAC transfer function are defined as those
voltages that correspond to negative full-scale and positive fullscale codes. For the unipolar output ranges, the endpoints are
code 1 and code 255. Code 1 is chosen because the amplifier is
now working in single supply and, in cases where the true offset
of the amplifier is negative, it cannot be seen at code 0. If the
relative accuracy were calculated between code 0 and code 255,
the “negative offset” would appear as a linearity error. If the offset is negative and less than 1 LSB, it will appear at code 1, and
hence the true linearity of the converter is seen between code 1
and code 255.
Relative Accuracy (ADC)
Relative Accuracy is the deviation of the ADC’s actual code
transition points from a straight line drawn between the endpoints of the ADC transfer function. For the bipolar input
ranges, these points are the measured, negative, full-scale transition point and the measured, positive, full-scale transition point.
For the unipolar ranges, the straight line is drawn between the
measured first LSB transition point and the measured full-scale
transition point.
Digital Feedthrough
Digital Feedthrough is also a measure of the impulse injected to
the analog output from the digital inputs, but is measured when
the DAC is not selected. It is essentially feedthrough across the
die and package. It is also a measure of the glitch impulse transferred to the analog output when data is read from the internal
ADC. It is specified in nV secs and is measured with WR high
and a digital code change from all 0s to all 1s.
DAC-to-DAC Crosstalk (AD7669 Only)
The glitch energy transferred to the output of one DAC due to
an update at the output of the second DAC. The figure given is
the worst case and is expressed in nV secs. It is measured with
an update voltage of full scale.
DAC-to-DAC Isolation (AD7669 Only)
DAC-to-DAC Isolation is the proportion of a digitized sine
wave from the output of one DAC, which appears at the output
of the second DAC (loaded with all 1s). The figure given is the
worst case for the second DAC output and is expressed as a ratio in dBs. It is measured with a digitized sine wave (fSAMPLING =
100 kHz) of 20 kHz at 2.5 V pk-pk.
Signal-to-Noise Ratio
Signal-to-Noise Ratio (SNR) is the measured signal to noise at
the output of the converter. The signal is the rms magnitude of
the fundamental. Noise is the rms sum of all the nonfundamental signals (excluding dc) up to half the sampling frequency.
SNR is dependent on the number of quantization levels used in
the digitization process; the more levels, the smaller the quantization noise. The theoretical SNR for a sine wave is given by
SNR = (6.02N + 1.76) dB
where N is the number of bits. Thus for an ideal 8-bit converter,
SNR = 50 dB.
Harmonic Distortion
Harmonic Distortion is the ratio of the rms sum of harmonics to
the fundamental. For the AD7569/AD7669, Total Harmonic
Distortion (THD) is defined as
2
Differential Nonlinearity
Differential Nonlinearity is the difference between the measured
change and an ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ± 1 LSB max ensures monotonicity (DAC) or no missed codes (ADC). A differential nonlinearity of ± 3/4 LSB max ensures that the minimum
step size (DAC) or code width (ADC) is 1/4 LSB, and the maximum step size or code width is 3/4 LSB.
Digital-to-Analog Glitch Impulse
Digital-to-Analog Glitch Impulse is the impulse injected into the
analog output when the digital inputs change state with the
DAC selected. It is normally specified as the area of the glitch in
nV secs and is measured when the digital input code is changed
by 1 LSB at the major carry transition.
REV. B
20 log
2
2
2
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the individual
harmonics.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products, of order (m + n), at sum and difference frequencies of
mfa ± nfb where m, n = 0, l, 2, 3,… . Intermodulation terms
are those for which m or n is not equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb) and the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
–5–
141
2
V 2 +V 3 +V 4 +V 5 +V 6
V1
D AD7569 DATASHEET
AD7569/AD7669
AD7569 PIN CONFIGURATIONS
PLCC
DIP, SOIC
LCCC
AD7669 PIN CONFIGURATIONS
DIP, SOIC
PLCC
ORDERING GUIDE
Model
Temperature
Range
Relative
Accuracy
TMIN –TMAX
Package
Option1
AD7569JN
AD7569JR
AD7569AQ
AD7569SQ2
AD7569BN
AD7569KN
AD7569BR
AD7569BQ
AD7569TQ2
AD7569JP
AD7569SE2
AD7569KP
AD7569TE2
AD7669AN
AD7669JN
AD7669JP
AD7669AR
AD7669JR
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
0°C to +70°C
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
0°C to +70°C
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 0.5 LSB
± 0.5 LSB
± 0.5 LSB
± 0.5 LSB
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1/2 LSB
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
N-24
R-24
Q-24
Q-24
N-24
N-24
R-24
Q-24
Q-24
P-28A
E-28A
P-28A
E-28A
N-28
N-28
P-28A
R-28
R-28
NOTES
1
E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = Small Outline SOIC.
2
To order MIL-STD-883, Class B processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
REV. B
–6–
142
D AD7569 DATASHEET
AD7569/AD7669
PIN FUNCTION DESCRIPTION
(Applies to the AD7569 and AD7669 unless otherwise stated.)
Pin
Mnemonic
AGNDDAC
Pin
Mnemonic
Description
Analog Ground for the DAC(s). Separate
ground return paths are provided for the
DAC(s) and ADC to minimize crosstalk.
VOUT
Output Voltage. VOUT is the buffered output
(VOUTA, VOUTB) voltage from the AD7569 DAC. VOUTA and
VOUTB are the buffered DAC output voltages
from the AD7669. Four different output voltage ranges can be achieved (see Table I).
VSS
RANGE
RESET
Negative Supply Voltage (–5 V for dual supply or 0 V for single supply). This pin is also
used with the RANGE pin to select the different input/output ranges and changes the data
format from binary (VSS = 0 V) to 2s complement (VSS = –5 V) (see Table I).
Range Selection Input. This is used with the
VSS input to select the different ranges as per
Table I. The range selected applies to both
the analog input voltage of the ADC and the
output voltage from the DAC(s).
Reset Input (Active Low). This is an asynchronous system reset that clears the DAC
register(s) to all 0s and clears the INT line of
the ADC (i.e., makes the ADC ready for new
conversion). In unipolar operation, this input
sets the output voltage to 0 V; in bipolar
operation, it sets the output to negative full
scale.
DB7
Data Bit 7. Most Significant Bit (MSB).
DB6–DB2
Data Bit 6 to Data Bit 2.
DGND
Digital Ground.
DB1
Data Bit 1.
DB0
Data Bit 0. Least Significant Bit (LSB).
WR
Write Input (Edge triggered). This is used in
conjunction with CS to write data into the
AD7569 DAC register. It is used in conjunction with CS and A/B to write data into the
selected DAC register of the AD7669. Data is
transferred on the rising edge of WR.
Description
CS
Chip Select Input (Active Low). The device is
selected when this input is active.
RD
READ Input (Active Low). This input must
be active to access data from the part. In the
Mode 2 interface, RD going low starts conversion. It is used in conjunction with the CS
input (see Digital Interface Section).
ST
Start Conversion (Edge triggered). This is
used when precise sampling is required. The
falling edge of ST starts conversion and drives
BUSY low. The ST signal is not gated with
CS.
BUSY
BUSY Status Output (Active Low). When
this pin is active, the ADC is performing a
conversion. The input signal is held prior to
the falling edge of BUSY (see Digital Interface Section).
INT
INTERRUPT Output (Active Low). INT going low indicates that the conversion is complete. INT goes high on the rising edge of CS
or RD and is also set high by a low pulse on
RESET (see Digital Interface Section).
A/B (AD7669
Only)
DAC Select Input. This input selects which
DAC register data is written to under control
of CS and WR. With this input low, data is
written to the DACA register; with this input
high, data is written to the DACB register.
CLK
A TTL compatible clock signal may be used
to determine the ADC conversion time. Internal clock operation is achieved by connecting
a resistor and capacitor to ground.
AGNDADC
Analog Ground for the ADC.
VIN
Analog Input. Various input ranges can be selected (see Table I).
VDD
Positive Supply Voltage (+5 V).
Table I. Input/Output Ranges
Range
VSS
Input/Output
Voltage Range
DB0–DB7
Data Format
0
1
0
1
0V
0V
–5 V
–5 V
0 V to +1.25 V
0 V to +2.5 V
± 1.25 V
± 2.5 V
Binary
Binary
2s Complement
2s Complement
REV. B
–7–
143
D AD7569 DATASHEET
AD7569/AD7669—Typical Performance Graphs
Noise Spectral Density vs. Frequency
Power Supply Rejection Ratio vs. Frequency
Positive-Going Settling Time (± 2.5 V Range)
Negative-Going Settling Time (± 2.5 V Range)
DAC/ADC Full-Scale Temperature Coefficient
IMD Plot for ADC
REV. B
–8–
144
D AD7569 DATASHEET
AD7569/AD7669
CIRCUIT DESCRIPTION
D/A SECTION
The AD7569 contains an 8-bit, voltage-mode, D/A converter
that uses eight equally weighted current sources switched into
an R-2R ladder network to give a direct but unbuffered 0 V to
+1.25 V output range. The AD7669 is similar, but contains two
D/A converters. The current sources are fabricated using PNP
transistors. These transistors allow current sources that are
driven from positive voltage logic and give a zero-based output
range. The output voltage from the voltage switching R-2R ladder network has the same positive polarity as the reference;
therefore, the D/A converter can be operated from a single
power supply rail.
The PNP current sources are generated using the on-chip
bandgap reference and a control amplifier. The current sources
are switched to either the ladder or AGNDDAC by high speed
p-channel switches. These high-speed switches ensure a fast settling time for the output voltage of the DAC. The R-2R ladder
network of the DAC consists of highly stable, thin-film resistors.
A simplified circuit diagram for the D/A converter section is
shown in Figure 3. An identical D/A converter is used as part of
the A/D converter, which is discussed later.
supply, a transistor on the output acts as a passive pull-down
with output voltages near 0 V with VSS = 0 V. This means that
the sink capability of the amplifier is reduced as the output voltage nears 0 V in single supply. In dual supply operation the full
sink capability of 1.25 mA is maintained over the entire output
voltage range.
For all other parameters, the single and dual supply performances of the amplifier are essentially identical. The output
noise from the amplifier, with full scale on the DAC, is 200 µV
peak-to-peak. The spot noise at 1 kHz is 35 nV/√Hz with all 0s
on the DAC. A noise spectral density versus frequency plot for
the amplifier is shown in the typical performance graphs.
VOLTAGE REFERENCE
The AD7569/AD7669 contains an on-chip bandgap reference
that provides a low noise, temperature compensated reference
voltage for both the DAC and the ADC. The reference is
trimmed for absolute accuracy and temperature coefficient. The
bandgap reference is generated with respect to VDD. It is buffered by a separate control amplifier for both the DAC and the
ADC reference. This can be seen in the DAC ladder network
configuration in Figure 3.
DIGITAL SECTION
The data pins on the AD7569/AD7669 provide a connection
between the external bus and DAC data inputs and ADC data
outputs. The threshold levels of all digital inputs and outputs
are compatible with either TTL or 5 V CMOS levels. Internal
input protection of all digital pins is achieved by on-chip distributed diodes.
The data format is straight binary when the part is used in single
supply (VSS = 0 V). However, when a VSS of –5 V is applied, the
data format becomes twos complement. This data format applies to the digital inputs of the DAC and the digital outputs of
the ADC.
ADC SECTION
Figure 3. DAC Simplified Circuit Diagram
OP AMP SECTION
The output from the D/A converter is buffered by a high speed,
noninverting op amp. This op amp is capable of developing
± 2.5 V across a 2 kΩ and 100 pF load to AGNDDAC. The amplifier can be operated from a single +5 V supply to give two
unipolar output ranges, or from dual supplies (± 5 V) to allow
two bipolar output ranges.
The feedback path of the amplifier contains a gain/offset network that provides four voltage ranges at the output of the op
amp. The output voltage range is determined by the RANGE
and VSS inputs. (See Table I in the Pin Function Description
section.) The four possible output ranges are: 0 V to +1.25 V,
0 V to +2.5 V, ± 1.25 V and ± 2.5 V. It should be noted that
whichever range is selected for the output amplifier also applies
to the input voltage range of the A/D converter.
The output amplifier settles to within 1/2 LSB of its final value
in typically less than 500 ns. Operating the part from single or
dual supplies has no effect on the positive-going settling time.
However, the negative-going output settling time to voltages
near 0 V in single supply will be slightly longer than the settling
time to negative full scale for dual supply operation. Additionally, to ensure that the output voltage can go to 0 V in single
REV. B
The analog-to-digital converter on the AD7569/AD7669 uses
the successive approximation technique to achieve a fast conversion time of 2 µs and provides an 8-bit parallel digital output.
The reference for the ADC is provided by the on-chip bandgap
reference.
Conversion start is controlled by ST or by CS and RD. Once a
conversion has been started, another conversion start should not
be attempted until the conversion in progress is completed.
Exercising the RESET input does not affect conversion; the
RESET input resets the INT line high, which is useful in interrupt driven systems where a READ has not been performed at
the end of the previous conversion. The INT line does not have
to be cleared at the end of conversion. The ADC will continue
to convert correctly, but the function of the INT line will be
affected.
Figure 4 shows the operating waveforms for a conversion cycle.
The analog input voltage, VIN, is held 50 ns typical after the falling edge of ST or (CS & RD). The MSB decision is made approximately 50 ns after the second falling edge of the input
CLK following a conversion start. If t1 in Figure 4 is greater
than 50 ns, then the falling edge of the input CLK will be seen
as the first falling clock edge. If t1 is less than 50 ns, the first falling clock edge of the conversion will not occur until one clock
cycle later. The succeeding bit decisions are made approximately 50 ns after a CLK edge until conversion is complete.
–9–
145
D AD7569 DATASHEET
AD7569/AD7669
At the end of conversion, the SAR contents are transferred to
the output latch, and the SAR is reset in readiness for a new
conversion. A single conversion lasts for 8 input clock cycles.
INTERNAL CLOCK
Clock pulses are generated by the action of an internal current
source charging the external capacitor (CCLK) and this external
capacitor discharging through the external resistor (RCLK).
When a conversion is complete, this internal clock stops operating and the CLK pin goes to the DGND potential. Connections
for RCLK and CCLK are shown in the operating diagram of Figure 21. The nominal conversion time versus temperature for the
recommended RCLK and CCLK combination is shown in Figure
6. The internal clock provides a convenient clock source for the
AD7569/AD7669. Due to process variations, the actual operating frequency for this RCLK/CCLK combination can vary from
device to device by up to ± 25%.
Figure 4. Operating Waveforms Using External Clock
ANALOG INPUT
The analog input of the AD7569/AD7669 feeds into an on-chip
track-and-hold amplifier. To accommodate different full-scale
ranges, the analog input signal is conditioned by a gain/offset
network that conditions all input ranges so the internal ADC always works with a 0 V to +1.25 V signal. As a result, the input
current on the VIN input varies with the input range selected as
shown in Figure 5.
Figure 6. Conversion Time vs. Temperature for Internal
Clock Operation
DIGITAL INTERFACE
DAC Timing and Control—AD7569
Figure 5. Equivalent VIN Circuit
TRACK-AND-HOLD
Table II shows the truth table for DAC operation for the
AD7569. The part contains an 8-bit DAC register, which is
loaded from the data bus under control of CS and WR. The
data contained in the DAC register determines the analog output from the DAC. The WR input is an edge-triggered input,
and data is transferred into the DAC register on the rising edge
of WR. Holding CS and WR low does not make the DAC register transparent.
The track-and-hold (T/H) amplifier on the analog input of the
AD7569/AD7669 allows the ADC to accurately convert an input sine wave of 2.5 V peak-to-peak amplitude up to a frequency of 200 kHz, the Nyquist frequency of the ADC when
operated at its maximum throughput rate of 400 kHz. This
maximum rate of conversion includes conversion time and time
between conversions. Because the input bandwidth of the T/H
amplifier is much larger than 200 kHz, the input signal should
be band-limited to avoid converting high-frequency noise
components.
Table II. AD7569 DAC Truth Table
The operation of this T/H amplifier is essentially transparent to
the user. The T/H amplifier goes from its tracking mode to its
hold mode at the start of conversion. This occurs when the
ADC receives a conversion start command from either ST or
CS & RD. At the end of conversion (BUSY going high), the
T/H reverts back to tracking the input signal.
EXTERNAL CLOCK
CS
WR
RESET
DAC Function
H
L
L
g
X
H
L
g
L
X
H
H
H
H
L
DAC Register Unaffected
DAC Register Unaffected
DAC Register Updated
DAC Register Updated
DAC Register Loaded with All Zeros
L = Low State, H = High State, X = Don’t Care
The AD7569/AD7669 ADC can be used with its on-chip clock
or with an externally applied clock. When using an external
clock, the CLK input of the AD7569/AD7669 may be driven
directly from 74HC, 4000B series buffers (such as 4049) or
from TTL buffers. When conversion is complete, the internal
clock is disabled. The external clock can continue to run between conversions without being disabled. The mark/space ratio
of the external clock can vary from 70/30 to 30/70.
The contents of the DAC register are reset to all 0s by an active
low pulse on the RESET line, and for the unipolar output ranges,
the output remains at 0 V after RESET returns high. For the bipolar output ranges, a low pulse on RESET causes the output to
go to negative full scale. In unipolar applications, the RESET line
can be used to ensure power-up to 0 V on the AD7569 DAC output and is also useful when used as a zero override in system calibration cycles. If the RESET input is connected to the system
REV. B
–10–
146
D AD7569 DATASHEET
AD7569/AD7669
RESET line, the DAC output resets to 0 V when the entire
system is reset. Figure 7 shows the input control logic for the
AD7569 DAC; the write cycle timing diagram is shown in
Figure 8.
The contents of the DAC registers are reset to all 0s by an active
low pulse on the RESET line, and for the unipolar output
ranges, the outputs remain at 0 V after RESET returns high.
For the bipolar output ranges, a low pulse on RESET causes the
outputs to go to negative full scale. In unipolar applications, the
RESET line can be used to ensure power-up to 0 V on the
AD7669 DAC outputs and is also useful when used as a zero
override in system calibration cycles. If the RESET input is connected to the system RESET line, then the DAC outputs reset
to 0 V when the entire system is reset. Figure 9 shows the DAC
input control logic for the AD7669, and the write cycle timing
diagram is shown in Figure 8.
Figure 7. AD7569 DAC Input Control Logic
Figure 9. AD7669 DAC Control Logic
ADC Timing and Control
Figure 8. AD7569/AD7669 Write Cycle Timing Diagram
DAC Timing and Control—AD7669
The ADC on the AD7569/AD7669 is capable of two basic operating modes. In the first mode, the ST line is used to start conversion and drive the track-and-hold into hold mode. At the end
of conversion, the track-and-hold returns to its tracking mode.
The second mode is achieved by hard-wiring the ST line high.
In this case, CS and RD start conversion, and the microprocessor is driven into a WAIT state for the duration of conversion by
BUSY.
Table III shows the truth table for the dual DAC operation of
the AD7669. The part contains two 8-bit DAC registers that are
loaded from the data bus under the control of CS, A/B and WR.
Address line A/B selects which DAC register the data is
loaded to. The data contained in the DAC registers determines
the analog output from the respective DACs. The WR input is
an edge-triggered input, and data is transferred into the selected
DAC register on the rising edge of WR. Holding CS and WR
low does not make the selected DAC register transparent. The
A/B input should not be changed while CS and WR are low.
Table III. AD7669 DAC Truth Table
CS
WR
A/B
RESET
DAC Function
H
L
g
L
g
X
H
g
L
g
L
X
X
L
L
H
H
X
H
H
H
H
H
L
DAC Registers Unaffected
DACA Register Updated
DACA Register Updated
DACB Register Updated
DACB Register Updated
DAC Registers Loaded with
All Zeros
Figure 10. ADC Mode 1 Interface Timing
L = Low State, H = High State, X = Don’t Care
REV. B
–11–
147
D AD7569 DATASHEET
AD7569/AD7669
MODE 1 INTERFACE
The timing diagram for the first mode is shown in Figure 10. It
can be used in digital signal processing and other applications
where precise sampling in time is required. In these applications, it is important that the signal sampling occurs at exactly
equal intervals to minimize errors due to sampling uncertainty
or jitter. In these cases, the ST line is driven by a timer or some
precise clock source.
MODE 2 INTERFACE
The falling edge of the ST pulse starts conversion and drives the
AD7569/AD7669 track-and-hold amplifier into its hold mode.
BUSY stays low for the duration of conversion and returns high
at the end of conversion and the track-and hold amplifier reverts
to its tracking mode on this rising edge of BUSY. The INT line
can be used to interrupt the microprocessor. A READ to the
AD7569/AD7669 address accesses the data, and the INT line is
reset on the rising edge of CS or RD. Alternatively, the INT can
be used to trigger a pulse that drives the CS and RD and places
the data into a FIFO or buffer memory. The microprocessor can
then read a batch of data from the FIFO or buffer memory at
some convenient time. The ST input should not be high when
RD is brought low; otherwise, the part will not operate correctly
in this mode.
The second interface mode is intended for use with microprocessors, which can be forced into a WAIT state for at least 2 µs.
The ST line of the AD7569/AD7669 must be hardwired high to
achieve this mode. The microprocessor starts a conversion and
is halted until the result of the conversion is read from the converter. Conversion is initiated by executing a memory READ to
the AD7569/AD7669 address, bringing CS and RD low. BUSY
subsequently goes low (forcing the microprocessor READY or
WAIT input low), placing the microprocessor into a WAIT
state. The input signal is held on the falling edge of RD (assuming CS is already low or is coincident with RD). When the conversion is complete (BUSY goes high), the processor completes
the memory READ and acquires the newly converted data.
While conversion is in progress, the ADC places old data (from
the previous conversion) on the data bus. The timing diagram
for this interface is shown in Figure 12.
It is important, especially in systems where the conversion start
(ST pulse) is asynchronous to the microprocessor, that a READ
does not occur during a conversion. Trying to read data from
the device during a conversion can cause errors to the conversion in progress. Also, pulsing the ST line a second time before
conversion ends should be avoided since it too can cause errors
in the conversion result. In applications where precise sampling
is not critical, the ST pulse can be generated from a microprocessor WR or RD line gated with a decoded address (different
from AD7569/AD7669 CS address).
Figure 12. ADC Mode 2 Interface Timing
The major advantage of this interface is that it allows the microprocessor to start conversion, WAIT, and then READ data with
a single READ instruction. The user does not have to worry
about servicing interrupts or ensuring that software delays are
long enough to avoid reading during conversion. The fast conversion time of the ADC ensures that for many microprocessors,
the processor is not placed in a WAIT state for an excessive
amount of time.
DIGITAL SIGNAL PROCESSING APPLICATIONS
Figure 11. Multichannel Inputs
This interface mode is also useful in applications where a number of input channels are required to be converted by the ADC.
Figure 11 shows the circuit configuration for such an application. The signal that drives the ST input of the AD7569/
AD7669 is also used to drive the ENABLE input of the multiplexer. The multiplexer is enabled on the rising edge of the ST
pulse while the input signal is held on the falling edge; therefore,
the signal must have settled to within 8 bits over the duration of
this ST pulse. The settling time, including tON (ENABLE) of
the multiplexer plus the T/H acquisition time (typically 200 ns),
thus determines the width of the ST pulse. This is suited to applications where a number of input channels needs to be successively sampled or scanned.
In Digital Signal Processing (DSP) application areas such as
voice recognition, echo cancellation and adaptive filtering, the
dynamic characteristics (SNR, Harmonic Distortion, Intermodulation Distortion) of both the ADC and DAC are critical. The
AD7569/AD7669 is specified dynamically as well as with standard dc specifications. Because the track/hold amplifier has a
wide bandwidth, an antialiasing filter should be placed on the
VIN input to avoid aliasing of high-frequency noise back into the
band of interest.
The dynamic performance of the ADC is evaluated by applying a
sine-wave signal of very low distortion to the VIN input, which is
sampled at a 409.6 kHz sampling rate. A Fast Fourier Transform
(FFT) plot or Histogram plot is then generated from which SNR,
harmonic distortion and dynamic differential nonlinearity data
can be obtained. For the DAC, the codes for an ideal sine wave
are stored in PROM and loaded down to the DAC. The output
spectrum is analyzed, using a spectrum analyzer to evaluate SNR
REV. B
–12–
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D AD7569 DATASHEET
AD7569/AD7669
and harmonic distortion performance. Similarly, for intermodulation distortion, an input (either to VIN or DAC code)
consisting of pure sine waves at two frequencies is applied to the
AD7569/AD7669.
Figure 15. DAC Output Spectrum
HISTOGRAM PLOT
Figure 13. ADC FFT Plot
Figure 13 shows a 2048 point FFT plot of the ADC with an input signal of 130 kHz. The SNR is 48.4 dB. It can be seen that
most of the harmonics are buried in the noise floor. It should be
noted that the harmonics are taken into account when calculating the SNR. The relationship between SNR and resolution (N)
is expressed by the following equation:
SNR = (6.02N + 1.76) dB
This is for an ideal part with no differential or integral linearity
errors. These errors will cause a degradation in SNR. By working backward from the above equation, it is possible to get a
measure of ADC performance expressed in effective number of
bits (N). This effective number of bits is plotted versus frequency in Figure 14. The effective number of bits typically falls
between 7.7 and 7.8, corresponding to SNR figures of 48.1 dB
and 48.7 dB.
Figure 15 shows a spectrum analyzer plot of the output spectrum from the DAC with an ideal sine-wave table loaded to the
data inputs of the DAC. In this case, the SNR is 46 dB.
When a sine wave of specified frequency is applied to the VIN input of the AD7569/AD7669 and several thousand samples are
taken, it is possible to plot a histogram showing the frequency of
occurrence of each of the 256 ADC codes. If a particular step is
wider than the ideal 1 LSB width, the code associated with that
step will accumulate more counts than for the code for an ideal
step. Likewise, a step narrower than ideal width will have fewer
counts. Missing codes are easily seen because a missing code
means zero counts for a particular code. The absence of large
spikes in the plot indicates small differential nonlinearity.
Figure 16 shows a histogram plot for the ADC indicating very
small differential nonlinearity and no missing codes for an input
frequency of 204 kHz. For a sine-wave input, a perfect ADC
would produce a cusp probability density function described by
the equation
p(V ) =
1
π( A2 − V 2 )1/2
where A is the peak amplitude of the sine wave and p(V) the
probability of occurrence at a voltage V.
The histogram plot of Figure 16 corresponds very well with this
cusp shape.
Further typical plots of the performance of the AD7569/AD7669
are shown in the Typical Performance Graphs section of the data
sheet.
Figure 14. Effective Number of Bits vs. Frequency
Figure 16. ADC Histogram Plot
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INTERFACING THE AD7569/AD7669
AD7569/AD7669—Z80 INTERFACE
AD7569/AD7669—ADSP-2100 INTERFACE
Figure 17 shows a typical interface to the Z80 microprocessor.
The ADC is configured for operation in the Mode 1 interface
mode. A precise timer or clock source starts conversion in applications requiring equidistant sampling intervals. The scheme
used, whereby INT of the AD7569/AD7669 generates an interrupt on the Z80, is limited in that it does not allow the ADC to
be sampled at the maximum rate. This is because the time between samples has to be long enough to allow the Z80 to service
its interrupt and read data from the ADC. To overcome this,
some buffer memory or FIFO could be placed between the
AD7569/AD7669 and the Z80. Writing data to the relevant
AD7569/AD7669 DAC simply consists of a <LD (nn), A> instruction where nn is the decoded address for that DAC. Reading data from the ADC, after an INT has been received,
consists of a < LDA, (nn)> instruction.
Figure 19 shows a typical interface to the DSP processor, the
ADSP-2100. The ADC is in the Mode 2 interface mode, which
means that the ADSP-2100 is halted during conversion. This is
achieved using the decoded address output. This is gated with
DMWR to ensure that it halts the processor for READ instructions only. INT going low at the end of conversion releases the
processor and allows it to finish off the READ instruction.
Figure 19. AD7569/AD7669 to ADSP-2100 Interface
Figure 17. AD7569/AD7669 to Z80 Interface
AD7569/AD7669—68008 INTERFACE
A typical interface to the 68008 is shown in Figure 18. In this
case, the ADC is configured in the Mode 2 interface mode. This
means that the one read instruction starts conversion and reads
the data. The read cycle is stretched out over the entire conversion period by taking the INT line back into the DTACK input
of the 68008. The additional gates are required so the 68008
receives a DTACK when the processor is writing data to the
AD7569/AD7669. In this case, there are no wait states introduced into the write cycle. Writing data to the relevant AD7569/
AD7669 DAC consists of a <MOVE.B Dn, addr> where Dn is
the data register, which contains the data to be loaded to that
DAC, and addr is the decoded address for the DAC. Data is
read from the ADC using a <MOVE.B addr,Dn> with the conversion result placed in register Dn.
Because the instruction cycle of the ADSP-2100 is so fast
(125 ns cycle), the DMWR pulse also has to be stretched also
for write cycles. This is achieved using the 74121, which generates a pulse that is fed back to DMACK. The duration of this
pulse determines how long the ADSP-2100 write cycle is
stretched. The buffers driving the DMACK line must have
open-collector outputs. Writing data to the relevant AD7569/
AD7669 DAC is achieved using a single instruction, <DM
(addr) = MRO>, where addr is the decoded address of that
DAC, and MRO contains the data to be loaded to the DAC register. Data is read from the ADC also, using a single instruction
<MRO = DM (addr)>, where the conversion result is placed in
the MRO data register.
AD7569/AD7669—IBM PC* INTERFACE
The AD7569/AD7669 is ideal for implementing an analog input/output port for the IBM PC. Figure 20 shows an interface
that realizes this function. The ADC is configured in the Mode
1 interface mode, and conversions are initiated using a precise
clock source for equidistant sampling intervals. At the end of
conversion, the INT line goes low, and the 74121 generates
Figure 20. AD7569/AD7669 to IBM PC Interface
Figure 18. AD7569/AD7669 to 68008 Interface
*IBM PC is a trademark of International Business Machines Corp.
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an RD pulse for the AD7569/AD7669. This RD pulse accesses
data from the ADC and places the conversion result into a register on the 74646. The rising edge of this pulse generates an interrupt request to the processor. The conversion result is read
from the 74646 register by performing an I/O read to the
decoded address of the 74646. Writing data to the relevant
AD7569/AD7669 DAC involves an I/O write to the 74646,
which transfers the data to the data inputs of the AD7569/
AD7669. Data is latched into the selected DAC register on the
rising edge of IOW.
UNIPOLAR (0 V to +2.5 V) CONFIGURATION
The 0 V to +2.5 V output voltage range is achieved by tying VSS
to AGNDDAC(= 0 V) and the RANGE input to VDD. The table
for output voltage versus digital code is as in Table IV with
2.VREF replacing VREF. Note that for this range
1 LSB = 2.V REF (2−8 ) = V REF
BIPOLAR (–1.25 V to +1.25 V) CONFIGURATION
APPLYING THE AD7569/AD7669 DAC
An internal gain/offset network on the AD7569/AD7669 allows
several output voltage ranges. The part can produce unipolar
output ranges of 0 V to +1.25 V or 0 V to +2.5 V and bipolar
output ranges of –1.25 V to +1.25 V or –2.5 V to +2.5 V. Connections for these various output ranges are outlined below.
UNIPOLAR (0 V to +1.25 V) CONFIGURATION
The first of the configurations provides an output voltage range
of 0 V to +1.25 V. This is achieved by tying the VSS and
RANGE inputs to AGNDDAC(= 0 V). Figure 21 shows the configuration of the AD7569 to achieve this output range. A similar
configuration of the AD7669 gives the same output range. The
table for output voltage versus the digital code in the DAC register is shown in Table IV.
The first of the bipolar configurations is achieved by tying the
RANGE input to AGNDDAC(= 0 V) and VSS to –5 V. The VSS
voltage level at which the AD7569/AD7669 changes to bipolar
operation is approximately –1 V. When the part is configured
for bipolar outputs, the input coding becomes twos complement. The table for output voltage versus the digital code in the
DAC register is shown in Table V. Note as with the unipolar
configuration, a digital input code of all 0s produces an output
of 0 V. It should be noted, however, that a low pulse on the
RESET line for the bipolar ranges sets the output voltage to
negative full scale.
Table V. Bipolar (–1.25 V to +1.25 V) Code Table
DAC Register Contents
MSB LSB
DAC Register Contents
MSB LSB
Analog Output, VOUT
 127 
0111
1111
+VREF 

 128 
0000
0001
+VREF 

 128 
0000
0000
0V
1111
1111
–VREF 

 128 
1000
0001
–VREF 

 128 
1000
0000
–VREF 
 = –VREF
 128 
Figure 21. AD7569 Unipolar (0 V to +1.25 V) Operation
Table IV. Unipolar (0 V to +1.25 V) Code Table
1
128
 1 
 1 
 127 
 128 
NOTE: 1 LSB = (V REF)(2–7) = VREF (1/128)
Analog Output, VOUT
BIPOLAR (–2.5 V to +2.5 V) CONFIGURATION
The –2.5 V to +2.5 V bipolar output range is achieved by tying
the RANGE input to VDD and the VSS input to –5 V. Once
again, the input coding is 2s complement. The table for output
voltage versus digital code is as in Table V with 2.VREF replacing
VREF. Note that for this range
 255 
 256 


1111
1111
+VREF
1000
0001
 129 
+VREF 

 256 
1000
0000
 128 
+VREF 
 = +VREF/2
 256 
0111
1111
 127 
+VREF 

 256 
0000
0001
 1 
+VREF 

 256 
0000
0000
0V
1 LSB = 4.V REF (2−8 ) = V REF
NOTE: 1 LSB = (V REF) (2–8) = VREF (1/256); V REF = +1.25 V Nominal
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APPLYING THE AD7569/AD7669 ADC
The analog input on the AD7569/AD7669 accepts the same
four input ranges as the output ranges on the DAC. Whatever
output range is selected for the DAC also applies to the input
range of the ADC.
Although separate AGNDs exist for both the DAC and ADC to
minimize crosstalk, writing data to the DAC while the ADC is
performing a conversion may result in an incorrect conversion
from the ADC due to an interaction of currents between the
DAC and ADC. Therefore, to ensure correct operation of the
ADC, the DAC register should not be updated while the ADC
is converting.
UNIPOLAR OPERATION
The circuit of Figure 21 shows the AD7569 configured for both
an input and output range of 0 V to +1.25 V (the AD7669 configuration is similar). The nominal transfer characteristic for this
range is shown in Figure 22. The output code is Natural Binary
with 1 LSB = (1.25/256)V = 4.88 mV.
As before, to achieve the unipolar 0 V to +2.5 V input range,
VSS is connected to 0 V, and the RANGE input is tied to a logic
high. The nominal transfer characteristic is as in Figure 22 but,
in this case, 1 LSB = (2.5/256)V = 9.76 mV.
Figure 23. Nominal Transfer Characteristic for Bipolar
(–1.25 V to +1.25 V) Operation
typical example is a digital filter where an ac analog signal is
quantized by the ADC, digitally processed and recreated using
the DAC. In these types of applications, the offset error can be
eliminated by ac coupling the recreated signal. Full-scale error
effect is linear and does not cause problems as long as the input
signal is within the full dynamic range of the ADC. An important parameter in DSP applications is Differential Nonlinearity,
and this is not affected by either offset or full-scale error.
In applications where absolute accuracy is important ADC offset and full-scale error can be adjusted to zero. Figure 24 shows
the additional components required for offset and full-scale error adjustment. Offset error must be adjusted before full-scale
error. Zero offset is achieved by adjusting the offset of the op
amp driving VIN (i.e., A1 in Figure 23). In unipolar applications, for zero offset error, apply 1/2 LSB at the analog input
and adjust the op amp offset voltage until the ADC output code
flickers between 0000 0000 and 0000 0001. For zero full-scale
error, apply an analog input of FS – 3/2 LSBs and adjust R1 until the ADC output code flickers between 1111 1110 and 1111
1111.
In bipolar applications, to adjust for bipolar zero offset, apply
–1/2 LSB at the analog input and adjust the op amp offset voltage until the output code flickers between 1111 1111 and 0000
0000. For zero full-scale error, apply +FS/2 – 3/2 LSB at the
analog input and adjust R1 until the ADC output code flickers
between 0111 1110 and 0111 1111.
Figure 22. Nominal Transfer Characteristic for Unipolar
(0 V to +1.25 V) Operation
BIPOLAR OPERATION
The analog input of the AD7569/AD7669 ADC is configured
for bipolar inputs when VSS = –5 V. The output code provided
by the part is twos complement. Figure 23 shows the transfer
function for bipolar (–1.25 V to +1.25 V) operation. The LSB
size for this range is (2.5/256)V = 9.76 mV.
The transfer function for the –2.5 V to +2.5 V range is identical
to that of Figure 23, but now FS = 5 V and the LSB size is
(5/256)V = 19.5 mV.
ADC OFFSET AND FULL-SCALE ERROR ADJUSTMENT
In most Digital Signal Processing (DSP) applications, offset and
full-scale error have little or no effect on system performance. A
Figure 24. ADC Error Adjust Circuit
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Figure 25. Peak-Reading A/D Converter
PEAK DETECTION—AD7569
The circuit of Figure 25 shows a peak-reading A/D converter,
which is useful in such applications as monitoring flow rates,
temperature, pressure, etc. The circuit ensures that a peak will
not be missed while at the same time does not require the microprocessor to frequently monitor the data. The peak value is
stored in the A/D converter and can be read at any time.
The gain on the AD524 is adjusted to yield a 0 V to +2.5 V output. When the input signal exceeds the current stored value, the
output of the TL311 goes low, triggering the Q output of the
74121. This low-going pulse starts a conversion on the AD7569
ADC, and at the end of conversion latches the result into the
DAC. This pulse must be at least 120 ns greater than the conversion time of the ADC. The Q output is used to drive the
strobe input of the TL311, resetting the TL311 output high in
readiness for another conversion.
head (or motor) is monitored. The closed-loop system allows an
error between the desired position and the actual position to be
monitored and corrected. The correction is achieved by adjusting the ratio of the phase currents in the motor windings until
the required head position is reached.
The AD7669 is ideally suited for the closed-loop microstepping
technique with its on-chip dual DACs for positioning the disk
drive head, and onboard ADC for monitoring the position of the
head. A generalized circuit for a closed-loop microstepping system is shown in Figure 26. The DAC waveforms are shown in
Figure 27, along with the direction information for clockwise rotation supplied by the controller.
The additional gates on the RD and WR inputs are to allow the
data to be read by the microprocessor while at the same time
ensuring that the DAC is not updated when the microprocessor
reads the data. It may be necessary to monitor the AD7569
BUSY line to ensure that a processor READ is not attempted
while the AD7569 is in the middle of a conversion. The READ
pulse width from the processor must be less than 1 µs to ensure
correct data is read from the ADC. A low-going pulse on the
RESET line resets the DAC output to 0 V and starts a new “peakdetection” period. This RESET pulse must also be less than 1 µs.
DISK DRIVE APPLICATION—AD7669
Closed-Loop Microstepping
Microstepping is a popular technique in low density disk drives
(both floppy and hard disk) that allows higher positional resolution of the disk drive head over that obtainable from a full- step
driven stepper motor. Typically, a two-phase stepper motor has
its phase currents driven with a sine-cosine relationship. These
cosinusoidal signals are generated by two DACs driven with the
appropriate data. The resolution of the DACs determines the
number of microsteps into which each full step can be divided.
For example, with a 1.8° full-step motor and a 4-bit DAC, a
microstep size of 0.11° (1.8°/(2n)) is obtainable.
The microstepping technique improves the positioning resolution possible in any control application; however, the positional
accuracy can be significantly worse than that offered by the
original full-step accuracy specification due to load torque effects.
Figure 26. Typical Closed-Loop Microstepping Circuit with
the AD7669
The AD7669 is used in the unipolar 0 V to +2.5 V configuration. This allows the circuit of Figure 26 to be completely unipolar (+5 V, +12 V supplies); no negative power supplies are
required. The power output stage is a dual H-Bridge device
such as the UDN-2998W from Sprague Electric. The phase
currents in both windings are detected by means of the small
value sense resistors, RSA and RSB, in series with the windings.
The voltage developed across these resistors is amplified and
compared with the respective DAC output voltage. The comparators in turn chop the phase winding current. The ADC
completes the feedback path by converting information from a
suitable transducer for analysis by the controller.
To ensure that the increased resolution is usable, it is necessary
to use a closed-loop system where the position of the disk drive
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On initial start-up, the output voltage, VO, will be invalid until
the length of the delay is reached (i.e., until the counter is reset). From this point forward, the delayed data is read from the
6116 and loaded to the DAC before the newly converted data is
written into the same memory location. The input clock to the
system can be a square wave of maximum input frequency 200
kHz
(assuming 2 µs conversion time for the ADC). The mark/space
ratio of the input clock can be varied to maximize the sampling
frequency if required. The clock low time has to be equal to the
conversion time and access time of the ADC plus the setup time
required for the 6116. The clock high time has only to be equal
to the setup time for the DAC plus the delay time through the
counter and the access time of the 6116.
Figure 27. Typical DAC Output Voltages for Microstepping
and Direction Signals for Clockwise Rotation with the
UDN-2998W
ANALOG DELAY LINE—AD7569
In many applications, especially in audio systems, it is necessary
to provide a delay on the input signal. The circuit of Figure 28
shows how a simple analog delay line can be implemented,
based on the AD7569. The input signal is sampled using the
AD7569 ADC, and converted data is loaded into the 6116 (2K
3 8 static ram). The inverted input clock drives a counter that
selects the address for the 6116. The delay is selected by choosing one of the output lines of the HCT4040 counter to reset the
coun-ter. This can be done using a simple switch in a manual
system or by a multiplexer in a programmable delay application.
Data is written to the DAC using the inverted input clock signal.
The amount of memory used, as well as the sampling frequency,
determines the maximum possible delay. Using the HCT4040,
and the 6116 with an input clock frequency of 200 kHz, the
maximum delay is 5 ms on a maximum input frequency of
100 kHz. Using 64K memory, with an 8 kHz input clock frequency, the maximum delay is 8 seconds on a maximum input
frequency of 4 kHz.
TRANSIENT RECORDER—AD7569
The scheme just outlined can also form the basis for a transient
recorder. In this case, transients on the input signal are converted and stored in memory. The transient can then be recalled
from memory at a later time, and the transient waveform can be
recreated using the AD7569 DAC.
INFINITE SAMPLE-AND-HOLD—AD7569
The AD7569 is ideal for implementing a single-chip infinite
sample-and-hold function. Basically, the ADC samples and converts the input signal into an 8-bit digital word. The 8 bits of
data are then loaded to the DAC and the sampled value is restored to analog form. The sampled value is held until the DAC
register is updated. The full-scale matching between the ADC
and the DAC on the AD7569 ensures a typical error of less than
1% between the analog input voltage and the “held” output
voltage. Figure 29 shows the connections required on the
AD7569 to achieve this infinite sample-and-hold function.
Figure 29. Infinite Sample-and-Hold
Figure 28. Analog Delay Line
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TARE FUNCTION FOR WEIGH SCALE—AD7569
The infinite sample-and-hold just outlined can also form the basis of a circuit to provide a tare function for a weigh scale system. Figure 30 shows a circuit for a weigh scale system. It
incorporates a tare function using a simple circuit based on the
AD7569.
The AD587, along with the 2N6285, provides a buffered +10 V
reference to supply the low impedance load cell transducer. The
load cell output is amplified by the AD624 precision instrumentation amplifier with gain adjustment provided by R1. The output of the AD624 is applied to the noninverting input of a unity
gain differential summing amplifier that uses the AD707, a high
precision op amp with low drift. The AD707 feeds a 3 1/2 digit
panel meter module that converts the signal for digital readout.
The input signal to the panel meter is also applied to the analog
input of the AD7569 for the tare function. When the tare switch
(S1) is closed, a tare cycle commences and VIN is sampled and
held infinitely at VOUT until the next tare cycle. VOUT drives the
inverting input of the differential amplifier and forces its output
to zero. Thus, the tare function is used to give a readout of zero
for any undesired weight, such as a box, when only the item
placed in it is to be weighed. The tare function can also be used
in calibrating the system, to cancel out offset errors due to the
load cell, AD624 and differential amplifier.
The AD7569 offers many advantages in the system outlined,
such as: simple, low cost circuit—no need for microprocessor,
software, etc.—and low power consumption.
Figure 30. Weigh Scale System with Tare Function
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OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Pin Cerdip (Q-24)
28-Terminal Leadless Ceramic Chip Carrier
(E-28A)
28-Terminal Plastic Leaded Chip Carrier
(P-28A)
28-Pin Plastic DIP (N-28)
28-Lead Small Outline (SO)
(R-28)
PRINTED IN U.S.A.
C1214–10–8/88
24-Pin Plastic (N-24)
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