AN IMPROVED DC-DC CONVERTER FOR PHOTOVOLTAIC POWER SYSTEM APPLICATIONS
by
Christopher D. Lute
A thesis submitted to the Faculty and the Board of Trustees of the Colorado School of Mines in
partial fulfillment of the requirements for the degree of Master of Science (Electrical Engineering).
Golden, Colorado
Date _______________
Signed: _________________________
Christopher Lute
Signed: _________________________
Dr. Marcelo G. Simões
Thesis Advisor
Golden, Colorado
Date _______________
Signed: _________________________
Dr. R. Haupt
Professor and Head
Department of Electrical Engineering
and Computer Science
ii
ABSTRACT
The Floating Interleaved Boost Converter (FIBC) is a novel DC-DC converter topology that can
provide high voltage gain with improved efficiency and decreased input ripple when compared to
conventional converters. These advantages make the FIBC a promising candidate for solar photovoltaic
(PV) power system applications. PV modules produce low voltage Direct Current (DC) electricity; this
must first be converted to a high voltage DC before being converted to Alternating Current (AC). The
FIBC has been demonstrated as a DC-DC converter solution for fuel cells and electric vehicle
applications in laboratory settings. In this thesis, the FIBC will be investigated for PV applications,
focusing particularly on challenges and solutions for commercialization.
This thesis will present a four phase FIBC for PV power system applications. The circuit
topology will be analyzed mathematically, and its characteristic advantages will be highlighted. A dual
loop, digital linear feedback controller will be developed that is capable of regulating both current and
voltage in the device. Additionally, Maximum Power Point Tracking (MPPT), a requisite for PV power
converters, will be included and demonstrated. Simulation results from PSIM will be provided to
illustrate key findings and control development. The development of a hardware prototype using an
embedded microcontroller will be detailed. Finally, the experimental testing and results will be discussed.
iii
TABLE OF CONTENTS
ABSTRACT
.............................................................................................................................. iv
LIST OF FIGURES ....................................................................................................................... vii
LIST OF TABLES .......................................................................................................................... ix
LIST OF ABBREVIATIONS .......................................................................................................... x
ACKNOWLEDGEMENTS .......................................................................................................... xiii
CHAPTER 1
INTRODUCTION ................................................................................................. 1
1.1
Objective ................................................................................................................ 1
1.2
Motivation.............................................................................................................. 2
1.3
Background ............................................................................................................ 2
1.3.1
DC-DC Converter Design Criteria and Characteristics ......................................... 2
1.3.2
DC-DC Boost Converter Topologies ..................................................................... 3
1.3.3
PV Characteristics.................................................................................................. 5
1.3.4
Maximum Power Point Tracking ........................................................................... 7
1.4
PV Power System .................................................................................................. 8
1.5
Scope and Contributions ...................................................................................... 10
1.6
Organization......................................................................................................... 11
CHAPTER 2
CONVERTER ANALYSIS ................................................................................. 13
2.1
Converter Simulation Study................................................................................. 13
2.2
Mathematical Analysis ........................................................................................ 17
2.3
Bidirectional Converter........................................................................................ 28
iv
2.4
Conclusion ........................................................................................................... 29
CHAPTER 3
MAXIMUM POWER POINT TRACKING ....................................................... 31
3.1
MPPT Algorithms ................................................................................................ 31
3.2
Conclusion ........................................................................................................... 35
CHAPTER 4
CONTROL DESIGN ........................................................................................... 36
4.1
Analog Control Design ........................................................................................ 36
4.2
Current Control Loop........................................................................................... 39
4.3
Voltage Control Loop .......................................................................................... 40
4.4
Discrete Controller ............................................................................................... 41
4.5
Conclusion ........................................................................................................... 42
CHAPTER 5
MODELING AND SIMULATION ..................................................................... 44
5.1
Simulation Description ........................................................................................ 44
5.2
Simulation Results ............................................................................................... 45
5.3
Conclusion ........................................................................................................... 48
CHAPTER 6
EXPERIMENTAL PROTOTYPE DEVELOPMENT ........................................ 50
6.1
Inductor ................................................................................................................ 51
6.2
Thermal Management .......................................................................................... 53
6.3
Proof-of-Concept Development ........................................................................... 56
6.4
Snubber Development.......................................................................................... 59
6.5
Gate Driver .......................................................................................................... 62
6.6
Analog Signal Conditioning ................................................................................ 63
6.7
Overcurrent Protection ......................................................................................... 64
v
6.8
Overvoltage Protection ........................................................................................ 66
6.9
Complete Circuit .................................................................................................. 67
6.10
Hardware Design ................................................................................................. 70
6.11
Isolation and Electromagnetic Interference ......................................................... 72
6.12
Microcontroller Code ........................................................................................... 75
6.13
Cost ...................................................................................................................... 77
6.14
Conclusion ........................................................................................................... 77
CHAPTER 7
EXPERIMENTAL TESTING AND RESULTS ................................................. 79
7.1
Current Controller ................................................................................................ 79
7.2
Voltage Controller ............................................................................................... 85
7.3
Maximum Power Point Tracking ......................................................................... 87
7.4
Conclusion ........................................................................................................... 93
CHAPTER 8
CONCLUSION AND FUTURE WORK ............................................................ 94
REFERENCES ............................................................................................................................. 98
APPENDIX A INDUCTOR TEST REPORT ............................................................................ 100
APPENDIX B COMPONENT LIST ......................................................................................... 102
APPENDIX C BILL OF MATERIALS LIST ........................................................................... 113
vi
LIST OF FIGURES
Figure 1.1 Example of PV pn junction. ........................................................................................................ 5
Figure 1.2 Typical I/V and P characteristics for a PV module under various irradiance values. ................. 7
Figure 1.3 Typical PV power system block diagram. ................................................................................... 9
Figure 1.4 Power outputs for full system simulation. ................................................................................... 9
Figure 1.5 Battery SOC for full system simulation. ................................................................................... 10
Figure 1.6 DC link voltage, inverter voltage and current. .......................................................................... 10
Figure 2.1 Circuit for 4P FIBC. .................................................................................................................. 17
Figure 2.2 4P FIBC with ideal switch representation. ................................................................................ 18
Figure 2.3 4P FIBC, switching state one. ................................................................................................... 18
Figure 2.4 4P FIBC, switching state two. ................................................................................................... 20
Figure 2.5 4P FIBC, switching state three. ................................................................................................. 21
Figure 2.6 4P FIBC, switching state four.................................................................................................... 22
Figure 2.7 4P FIBC, switching state five. ................................................................................................... 23
Figure 2.8 Bidirectional 4P FIBC. .............................................................................................................. 29
Figure 2.9 Power results for bidirectional 4P FIBC. ................................................................................... 29
Figure 3.1 P&O MPPT algorithm. .............................................................................................................. 32
Figure 3.2 IC algorithm flow diagram. ....................................................................................................... 34
Figure 4.1 Open loop input and output voltage response............................................................................ 37
Figure 4.2 Power response for VC and VDC voltage control strategies for a step change in irradiance. .. 37
Figure 4.3 Control block diagram for 4P FIBC. ......................................................................................... 38
Figure 4.4 4P FIBC control loops. .............................................................................................................. 39
Figure 4.5 Bode diagram of the open loop uncompensated and compensated current control loop........... 40
Figure 4.6 Bode diagram of the open loop uncompensated and compensated voltage control loop .......... 41
Figure 5.1 Step response for analog P&O................................................................................................... 45
Figure 5.2 Fixed versus variable delta for IC MPPT, with step change in irradiance ................................ 46
Figure 5.3 Step response for discrete P&O. ................................................................................................ 47
Figure 5.4 Step response for discrete IC. .................................................................................................... 47
Figure 6.1 Completed inductors attached to chassis ................................................................................... 53
Figure 6.2 POC 1. ....................................................................................................................................... 57
Figure 6.3 POC 1 annotated breadboard. .................................................................................................... 57
Figure 6.4 POC 2. ....................................................................................................................................... 58
Figure 6.5 POC 2 annotated breadboard. .................................................................................................... 58
Figure 6.6 VCE (yellow) and IL (blue) waveforms for POC 1, duty cycle = 0.75. .................................... 59
vii
Figure 6.7 VDS (yellow) and IL (blue) waveforms for POC 2, duty cycle = 0.75. .................................... 60
Figure 6.8 VDS (yellow) and IL (blue) waveforms for POC 2, duty cycle = 0.75. .................................... 62
Figure 6.9 Gate driver circuit schematic. .................................................................................................... 63
Figure 6.10 CT signal conditioning circuit schematic. ............................................................................... 63
Figure 6.11 Voltage sensor signal conditioning circuit schematic. ............................................................ 64
Figure 6.12 Overcurrent protection circuit schematic................................................................................. 65
Figure 6.13 Overvoltage protection circuit schematic. ............................................................................... 66
Figure 6.14 Complete circuit schematic diagram. ...................................................................................... 68
Figure 6.15 PCB for 4P FIBC. .................................................................................................................... 71
Figure 6.16. Hardware prototype. ............................................................................................................... 72
Figure 6.17 PCB with switching DC-DC converters. ................................................................................. 73
Figure 6.18 Hardware prototype with external linear power supplies. ....................................................... 74
Figure 6.19 Fixed-Point Integer Control Block Diagram ........................................................................... 77
Figure 7.1 Staggered PWM pulses.............................................................................................................. 79
Figure 7.2 Experimental test setup for current control testing. ................................................................... 80
Figure 7.3 Four inductor currents, steady state, 3 A reference. .................................................................. 80
Figure 7.4 Inductor currents IL1 and IL3 and input current IIN, steady state, 3 A reference. ........................ 81
Figure 7.5 Step response for inductor current IL2 for a reference from 4 to 8 A at time t = 2 ms. .............. 82
Figure 7.6 Step response for inductor current IL2 for a reference from 8 to 4 A at time t = 2 ms ............... 82
Figure 7.7 Step response for inductor current IL2 for a reference from 4 to 8 A, multiple cycles. ............. 83
Figure 7.8 Step response for four inductor currents for a reference from 2.5 to 4 A at time t = 1 ms ........ 83
Figure 7.9 Step response for four inductor currents (IL3 not shown) for a reference from 2.5 to 4 A ........ 84
Figure 7.10 Step response for four inductor currents for a reference from 2.5 to 4 A, multiple cycles ..... 84
Figure 7.11 Experimental test setup for voltage control testing. ................................................................ 85
Figure 7.12 Output voltage response to step change in load from 157 Ω to 103 Ω and back .................... 86
Figure 7.13 Input and inductor current response for a step change in load from 157 Ω to 103 Ω ............. 86
Figure 7.14 Four inductor current response for a step change in load from 157 Ω to 103 Ω and back ...... 87
Figure 7.15. MPPT testing setup................................................................................................................. 88
Figure 7.16 Simulation result for IC MPPT method with duty cycle sweep using PV model input. ......... 89
Figure 7.17 Simulation result for IC MPPT method with duty cycle sweep using DC input source ......... 90
Figure 7.18 Input voltage and current response for CV and IC MPPT algorithms in response to ............. 91
Figure 7.19 Power response for CV and IC MPPT algorithms in response to a change ............................ 91
Figure 7.20 Input voltage and current response for CV and IC MPPT algorithms in response to ............. 92
Figure 7.21 Power response for CV and IC MPPT algorithms in response to a change ............................ 92
viii
LIST OF TABLES
Table 2.1 Device parameters for simulation study...................................................................................... 15
Table 2.2 Device parameters for simulation study...................................................................................... 16
Table 5.1 MPPT Simulation Energy Results Comparison .......................................................................... 48
Table 6.1 Selected Component Ratings and Part Numbers. ....................................................................... 50
Table 7.1 MPPT power comparison. .......................................................................................................... 89
Table B-1 Component List........................................................................................................................ 103
Table C-1 Bill of Materials. ...................................................................................................................... 114
ix
LIST OF ABBREVIATIONS
4P
A
AC
ADC
AL
AT/cm
CCM
CdTe
CIGS
Cin
cm
COSS
Cout
CS
CT
CV
DC
DCR
EMI
EOFF
EON
ESR
fc
FIBC
fsw
GW
hr
I
IC
ID
IGBT
IIN
ISC
ISR
It,rms
J
kHz
Four phase
Amperes
Alternating Current
Analog to Digital Converter
Nominal inductance factor
Ampere-turns per centimeter
Continuous Conduction Mode
Cadmium Telluride
Copper Indium Gallium Selenide
Input Capacitor
centimeter
Output capacitance of the MOSFET
Output capacitor
snubber capacitor
Current Transducer
Constant Voltage
Direct Current
DC resistance
Electromagnetic Interference
turn-off energy
turn-on energy
Equivalent Series Resistance
crossover frequency
Floating, Interleaved Boost Converter
Switching frequency
Gigawatts
hour
Current
Incremental Conductance
drain current
Integrated Gate Bipolar Transistor
Input current
Short circuit current
Interrupt Service Routine
RMS Transistor current
Joules
kilohertz
x
Ki
KI
KP
Kv
kW
L
mA
MC
MHz
MIPS
MOSFET
MPP
MPPT
ms
mV
N
nH
nH/T2
o
C/W
OCV
oz/ft2
P
P&O
PCB
PI
PLL
PM
POC
PPE
PV
PWM
rCin
rCout
rD
rDT
rL
RL
RMS
RS
rT
RθCS
current sensor gain
Integral gain
Proportional gain
voltage sensor gain
Kilowatts
Inductor
milli-Amperes
Motor Control
Megahertz
Mega-Instructions Per Second
Metal Oxide Semiconductor Field Effect Transistor
Maximum Power Point
Maximum Power Point Tracking
millisecond
millivolts
Initial number of turns
nano-Henrys
nano-Henrys per Tesla squared
degrees Celsius per Watt
Open Circuit Voltage
ounce per square foot
Power
Perturb and Observe
Printed Circuit Board
Proportional-integral
Phase Locked-Loop
Phase Margin
Proof Of Concept
Polypropylene
Photovoltaic
Pulse Width Modulation
Input capacitor ESR
Output capacitor ESR
Diode resistance
Switch reverse recovery diode resistance
Inductor DC resistance
Load resistance
Root Mean Square
snubber resistor
Switch on resistance
thermal resistance from case to mounting surface
xi
RθJC
RθSA
S
SCP
SEPIC
SOC
STC
T
TA
tf
THD
TJ
tr
tS
tsw
TVS
ux,avg
V
VC
VCE(on)
VDC
VDC
VDS
VDT
Vf
VGS
VOC
VOUT
Vref
Vt,peak
W
W/m2
Δ
η
λ
µF
µH
µm
µs
Ω
thermal resistance from junction to case
thermal resistance of the heat sink
Switching stress
Short Current Pulse
Single-Ended Primary Inductor Converter
State Of Charge
Standard Test Conditions
Temperature
ambient air temperature
fall time
Total Harmonic Distortion
junction temperature
rise time
Simulation time
switching period
Transient Voltage Suppression
Switch input average value
Voltage
Capacitor voltage
Collector-emitter on voltage
Volts Direct Current
DC link voltage
Drain to source voltage
Switch reverse recovery diode threshold voltage
Diode forward voltage drop
Gate to source voltage
Open circuit voltage
Output voltage
Reference voltage
Peak transistor voltage
Watts
Watts per meter squared
MPPT increment/decrement interval
efficiency
Irradiance
micro-Farads
micro-Henreys
micrometers
microseconds
Ohms
xii
ACKNOWLEDGEMENTS
I would like to take this time to express my most sincere gratitude for several people whose
support, guidance, and insight were indispensable in completing this thesis. First, I must express my
appreciation for my advisor, Dr. Marcelo Simões, who offered me the chance to work on this exciting and
challenging research project, and who has been helpful and supportive through every step of the process.
Working on this has provided a wealth of knowledge that I never would have received in a classroom, and
for that I am extremely grateful. I would also like to extend my thanks to the committee, Dr. Ravel
Ammerman and Dr. Salman Mohagheghi, for their interest in and support of this research.
I gratefully acknowledge The National Science Foundation and The Petroleum Institute, Abu
Dhabi, UAE, for their financial support during my study and research.
I would also like to thank Robert V. White of Embedded Power Labs for providing insightful
design review and suggestions that proved essential to the development of a working prototype.
Additionally, Danilo Brandão provided helpful review and guidance on several aspects, and gave me a
trove of good Brazilian music to listen to.
Magnetics, Inc. of Pittsburgh, PA, generously donated the cores and bobbins for the custom
inductors, which is greatly appreciated. Also appreciated is the fine work done by Badger Magnetics of
Colorado Springs, CO, who assembled the final inductors. Advanced Circuits in Aurora, CO, did
excellent and prompt work on the printed circuit board at a generous discount.
Finally, I must thank my wife, Claire, and two children, Matthew and Josephine. They have been an
invaluable source of strength and support.
xiii
CHAPTER 1
INTRODUCTION
Renewable energy conversion technologies based on solar and wind sources are very interesting
for electricity production because they are non-polluting and do not deplete finite fossil fuel resources.
Solar photovoltaic (PV) power systems have found numerous applications, ranging from small, standalone systems to utility-scale, grid-connected power plants [1]. At the end of 2012, the cumulative
installed, grid-connected PV capacity in the United States reached approximately 7.4 Gigawatts (GW). Of
the nearly 316,000 PV installations which were connected to the grid in 2012, approximately 283,000
(nearly 90%) were residential systems [2]. Solar PV installations tend to be expensive when compared
with conventional fossil fuel power generation, but benefit from having no associated fuel cost [3].
However, in order to maximize the return on investment, it is important to maximize the amount of
electricity generated by the PV system. This thesis focuses on the development of a novel, effective
power converter which will extract the maximum power from a PV array using a Maximum Power Point
Tracking (MPPT) control algorithm with a very efficient circuit topology.
1.1
Objective
The goal of this thesis is to design, build, demonstrate, and evaluate a novel, direct-current (DC)
converter for use in for PV power system applications, with several advantages when compared to the
current state-of-art. The system designed in this thesis will serve as part of a residential-scale, or small
commercial, PV power system. The interface for the PV modules and inverter will be addressed as part of
the design process. A provision for including optional energy storage will be considered as well, although
the actual incorporation of energy storage is outside of the scope of this thesis. MPPT capability will be
implemented as part of the converter design, in order to maximize energy capture. The design process will
include performing mathematical modeling and simulation, with analysis made with simulation software
such as PSIM and Matlab-Simulink. After completing the modeling and simulation study, the converter
will be implemented in hardware and evaluated.
The Floating, Interleaved Boost Converter (FIBC) is a novel topology which has been initially
proposed for fuel cell and hybrid electric vehicle applications, where high voltage gain and high
efficiency are of great concern [4]. The FIBC has been demonstrated to offer improved voltage boost ratio
and efficiency when compared to conventional boost converters [5], [6]. One contribution of this thesis is
to adapt this converter for PV applications, and make it suitable for further energy storage integration. An
improved, discrete dual-loop linear feedback controller will be developed and implemented. Different
1
MPPT techniques will be evaluated and demonstrated. A hardware prototype will be developed and
experimental results presented. This prototype will exhibit a significantly higher fidelity than previous
laboratory prototypes of this converter topology by more closely representing commercially produced
hardware. It will use an embedded microcontroller to execute all control functions using fixed-point
arithmetic. The prototype will also incorporate several ancillary circuit features and functions, including:
analog signal measurement and conditioning, gate drivers, and overcurrent and overvoltage protection.
The final prototype will be much closer to a commercial product, or an industrial retrofit, than the
prototypes already developed by Kabalo, et al in [5] or Choi, et al in [7]. Specific challenges and unique
characteristics will be identified as they relate to commercialization. A bidirectional version of the
converter for battery charging applications will be presented and demonstrated in simulation. However,
the hardware implemented in this thesis is unidirectional; a bidirectional prototype for battery storage is
suggested as a future effort.
1.2
Motivation
Recent decreases in the cost of solar technologies have spurred wider deployment of PV
electricity generation systems. Two studies produced by the US Department of Energy, the SunShot
Vision [8], and the Renewable Energy Futures study [9], both anticipate continued, significant growth in
PV between now and the coming
decades. These two studies estimated growth in solar capacity
(including both PV and concentrated solar power), and the proportion of energy generated by solar
technologies up to the year 2050. There was a wide range in results, depending primarily on cost
trajectories, but also influenced by grid flexibility and transmission constraints. The study results estimate
the installed PV capacity in 2050 to range anywhere from 100 GW to > 600 GW, with decreasing
installed cost being the primary driver [10]. Meeting these goals of increased installation at reduced cost
will require advanced, high performance power converters capable of maximizing energy conversion.
1.3
Background
This section provides background information and literature review on: DC-DC converter design
criteria and characteristics, DC-DC boost converter topologies, PV characteristics, and MPPT.
1.3.1
DC-DC Converter Design Criteria and Characteristics
An important design criterion for DC-DC converters for PV applications is the ability to produce
a high voltage output from a low voltage input. The operating voltage for commercially available PV
modules is low voltage dc, typically around 20 volts direct current (VDC) [11]. However, a high input
voltage is necessary for efficient conversion to alternating current (AC) when using a DC-AC inverter.
2
One option is to increase this voltage through series combination of multiple PV modules. However, this
approach suffers from several disadvantages. First, series combinations reduce reliability; a failure of any
one module in a series string will result in the entire string being unavailable. As the current through
series-connected components must always be equal, the total string current will be dictated by the lowest
performing module in the string. This is especially problematic in partial-shading situations, where
shading of a single module will diminish the power output of the entire string. Therefore, it is
advantageous to combine modules in parallel and use a DC-DC converter to increase the output voltage to
the required input of the DC-AC inverter. The output voltage of this DC-DC converter must be in the
range of 400 VDC for a typical DC link input voltage for a three-phase 208/120 V or single-phase 220 V
or 240 V inverter.
Other important criteria for the design include efficiency and cost. As with any renewable energy
application, efficiency is of paramount importance. Cost is another important factor in converter design.
Therefore, the converter should employ the least complex topology necessary to achieve the stated goals,
and should employ methods to use less expensive components when possible.
In addition, the converter may need to address criteria related to ripple and isolation. Ripple refers
to the deviation of the input and output voltage and current from a pure DC. Ripple occurs in DC-DC
converters due to the switching transients. High input current and voltage ripple can negatively impact the
amount of power produced by the PV array, and may interfere with the proper operation of MPPT
algorithms. The other factor to consider is isolation; DC-DC converters may be non-isolated or isolated.
Galvanic isolation is accomplished through the use of a high frequency transformer in the DC-DC
converter, or by a low frequency output transformer. However, these transformers add to the size, weight,
and cost of converters, and have associated losses. Therefore, galvanic isolation is typically neglected for
PV power converters systems [12].
1.3.2
DC-DC Boost Converter Topologies
Many different DC-DC converters exist that can produce an output voltage that is greater than the
input voltage. Conventional boost converter topologies include: boost, buck-boost, Cúk, Single Ended
Primary Inductor Converter (SEPIC), and Zeta converters. A DC-DC boost converter produces an output
voltage which is always greater in magnitude than the input voltage [13]. The practically realizable
voltage gain of this converter in most cases is not greater than 4, particularly when high output voltage
and power are required, making this impractical for this application [7]. The boost converter works by
closing a switch which isolates the output stage while charging an inductor. When the switch is open,
energy from both the input and inductor flow to charge an output capacitor [14]. For buck-boost
3
converters, the magnitude of the output voltage can be greater or less than the input voltage, and has
opposite polarity. Notable disadvantages of this circuit include: high input-voltage ripple and high
switching stress [13]. Like the buck-boost converter, the Cúk produces an inverter output which can be
greater or less than the input voltage in magnitude. This converter has lower input and output current
ripple than other converter topologies [14], and has been used for many PV power system applications
[13]. The SEPIC can, like the buck-boost and Cúk converters, produce an output voltage which can be
either greater or less than the input, but without inverting. Finally, the Zeta converter can also provide a
non-inverter output which can be greater or less than the input in magnitude.
The voltage gain which can be achieved using any DC-DC converter topology is limited by the
parasitics of the components [7]. As power, and current, through a device increases, the conduction (I2R)
losses will have greater impacts. Therefore, new high-gain converter topologies are required to provide
the necessary voltage gain at high power.
The FIBC consists of two conventional boost converters, a floating version on the positive rail
and a non-floating version on the negative rail. These are connected in series at the output with the input
source. This series connection increases the obtainable voltage gain while reducing the output voltage
ripple [7]. The inductor branch can then be split into multiple parallel phases, which reduces the amount
of current through each branch, thus reducing the loss. Interleaving converters have reduced current
ripple, but the classical interleaved converter does not provide improved voltage gain over conventional
boost converters [7]. By combining two boost converters together, and including interleaving, the FIBC
can produce high voltage gain with lower current ripple.
Although the FIBC requires a greater number of components than conventional converters, it
benefits from:

Increased efficiency and voltage gain [5]

Decreased input ripple [5]

Lower voltage and current ratings for semiconductor devices (e.g., switches, diodes) [5]

Higher switch utilization factors and lower switching stress [5]

Smaller inductor volumes due to lower current flow through each inductor [7]

Lower capacitor voltage ratings, as each capacitor carries only about 60% of the output
voltage [7]

Lower I2R losses and voltage drop through inductive components [7]
4
These advantages have led the FIBC topology to be proposed as a suitable solution for fuel cell
and hybrid electric vehicle applications [4]. It has also been proposed as a promising candidate for PV
power systems, but has not yet been demonstrated for this particular application [7]. Open loop hardware
demonstrations of the FIBC have been conducted in [6] and [7]. A laboratory prototype was demonstrated
for fuel cell applications by Kabalo, et al., in [5] and [15]. This prototype made use of a dual-loop, sliding
mode controller to regulate inductor current and output voltage [16]. This prototype used a dSPACE DS
1104 real time board for control implementation. The FIBC has also been demonstrated for electric
vehicle applications using a linear feedback control algorithm implemented by a digital signal controller
[17].
1.3.3
PV Characteristics
PV technology is capable of converting sunlight directly into electricity. The building block of
PV technology is the PV cell, which is a specially designed pn junction (or multiple junctions for multilayer PV cells) using a semiconductor material. An example of a pn junction is provided in Figure 1.1.
Single crystal (mono-crystalline) silicon tends to be the most robust, efficient semiconductor material for
producing PV cells. Unfortunately, producing mono-crystalline silicon tends to be relatively energy
intensive, making them more expensive. Multi-crystalline (poly-crystalline) silicon PV cells are more
economical, but are typically less efficient. Newer, thin-film semiconductor technologies have been
introduced. These materials, which include amorphous silicon, Copper Indium Gallium Selenide (CIGS),
and Cadmium Telluride (CdTe) are unique in that only a very thin layer, 1-2 micrometers (µm) is
required, which reduces material costs [11].
Figure 1.1 Example of PV pn junction.
A typical PV cell will yield < 3 Watts (W) at around 0.5 VDC. In order to produce more useful
power and voltage, multiple cells are combined into modules. Each module consists of around 36 cells,
5
combined in series/parallel combinations to obtain the desired voltage and power rating. Module power
output ranges from a few watts to > 300 W. Open circuit voltage ratings of around 20-30 VDC are
common. Cells are mounted and interconnected with wires or metal foil strips, then encapsulated with a
protective glass or composite. Anticipated module lifetime is normally over 20 years [11].
Most applications require more power than is available from a single module. Therefore, multiple
modules are combined in series/parallel arrangements into arrays. As has been mentioned previously,
series combination will increase the array voltage, but comes with performance and reliability penalties.
Parallel combination of PV modules requires each module to be maintained at the same voltage. This will
be accomplished by the DC-DC converter, which will determine the operating voltage of the PV array
based on the MPPT algorithm. One disadvantage to this method is that the MPPT will be applied for the
array as a whole, and cannot take into account variations in individual modules or partial shading
conditions. Module-integrated converters have been proposed as a solution for this problem. Every panel
would have an integrated DC-DC converter with MPPT to bias each module individually [17].
The current-voltage (I-V) characteristic of PV devices is unique in that it can be approximated as
an ideal current source for part of its operational range, and as an ideal voltage source for the other part.
In addition, this I-V characteristic is dependent on the operating irradiance (λ) and temperature (T). The
short circuit current (ISC) is strongly dependent on λ, but is relatively insensitive to changes in T. Cell
open circuit voltage (VOC) decreases with increasing temperature by approximately 0.5%/ oC above rated.
This decreased voltage also limits the power produced by a PV cell at higher operating temperature [11].
Typical I-V relationships for a PV module under various irradiance values are given in Figure
1.2. Irradiance is given in watts per meter squared (W/m2). This graph also plots power output (P) for the
module. From this, is can be observed that there is a point at which the power produced by the PV module
is at its maximum value; this corresponds to the knee point of the I-V curve. An important capability for
any effective PV application is the ability to dynamically track this value under varying operating
conditions. This task is accomplished through MPPT.
6
10
160
9
140
1,000 W/m2
8
Current [A]
100
6
600 W/m2
5
80
4
60
3
40
200 W/m2
2
1
20
0
0
0
5
Power [W]
120
7
10
15
20
25
Voltage [V]
30
35
Current
Power
Figure 1.2 Typical I/V and P characteristics for a PV module under various irradiance values.
1.3.4
Maximum Power Point Tracking
Extracting the maximum useful power from renewable energy systems, including PV, is essential
for maintaining cost effectiveness. In PV applications, this is accomplished through the use of a MPPT
control scheme. At least nineteen distinct MPPT methods have been developed in the past [20]. Simple
algorithms include Constant Voltage (CV), in which the converter maintains the PV array at a constant
reference voltage value (Vref) that has been determined to yield the maximum power under a certain set of
conditions. This is therefore an approximate MPPT, and cannot achieve the true maximum power point
(MPP). It is very simple and inexpensive to implement, but is not capable of adapting to dynamically
changing operating conditions. However, the CV method has been proven to be more effective than other,
more complex algorithms in low irradiance conditions; for this reason, CV can be combined with other
MPPT techniques [21].
Related to the CV method is the Open Circuit Voltage (OCV) method, which periodically open
circuits the PV array. A PV output voltage set point is determined as a certain percentage of VOC,
typically between 71-78% [20]. This algorithm is capable of compensating for temperature effects, which
affect the output voltage of the PV. A downside is that no power is generated while the PV array is in
open circuit. Again, this method can only approximate the MPP.
Another simple method for MPPT is the Short Current Pulse (SCP) method. This is akin to the
OCV method, but the panel is short-circuited rather than open-circuited. The converter is commanded by
a current control loop and the operating current is commanded to be a percentage of the ISC, often around
7
92% [21]. Like the OCV method, no power is produced while the PV array is being short circuited.
Because ISC is dependent on irradiance, but is relatively insensitive to temperature, the SCP method is
more effective at responding to varying irradiance than to differences in module temperature. Also, the
converter will experience large stresses during the switching operations; this is true for both OCV and
SCP. Like the CV and OCV, the SCP method only approximates the MPP.
More complex methods are available which are capable of determining the true MPP. Extremumseeking control theory can be used to establish a feedback system in order to induce oscillations around
the equilibrium point, thereby attempting to determine the MPP [22]. The Perturb-and-Observe (P&O)
method periodically adjusts the operating point and measures the instantaneous power output. If the
power increases, the converter will continue to adjust the operating point in the same direction, and if it
decreases the direction of adjustment will be reversed. This method is effective but has a tendency to
oscillate around the MPP and may not be able to adjust to rapidly varying conditions [21].
The Incremental Conductance (IC) method improves on the P&O method be eliminating the
oscillations around the output. This method uses the relationship between the instantaneous and
incremental conductance (I/V and
) values to determine both the magnitude and direction of adjustment
required to achieve the MPP. It requires more complex controls and greater computational resources [21].
Both P&O and IC algorithms may make use of Fuzzy Logic to increase performance and accuracy [20],
[22]. In [21], a hybrid combination of IC and CV was found to yield the highest energy capture in a study
of 10 different MPPT techniques [21].
1.4
PV Power System
A typical PV power system block diagram is shown in Figure 1.3. Here, a PV array is connected
to a DC-DC boost converter to raise it to the required DC link voltage. An energy storage system (e.g.,
battery) connects through a bidirectional charge controller that steps the battery voltage up to the DC link,
and allows power to flow either from the DC link to the battery (charging) or from the battery to the DC
link (discharging). An inverter is connected to the DC link in order to produce AC power, with an LCL
filter to limit the harmonics [24]. For grid-connected systems, this AC output would be connected to the
utility grid, along with any AC loads. The inverter could be unidirectional or bidirectional, depending on
whether it is desired to allow grid power to charge the battery.
8
Figure 1.3 Typical PV power system block diagram.
A full day simulation of this system was conducted using PSIM, a power electronics simulation
software. One simulation second was equal to eight hours of real time. At the start, the PV was producing
close to full rated output, supplying the 2 kW resistive load, and charging the battery. At simulation time
(tS) = 8 hours (hr), the PV stopped producing power, and the battery supplied the 2 kW load. At tS ≈ 19 hr,
the battery state of charge (SOC) dropped to about 10%. At this point, the battery disconnected, and the
load was supplied by the grid. The power outputs from the various sources are plotted in Figure 1.4.
Figure 1.4 Power outputs for full system simulation.
Figure 1.5 shows the battery SOC, and Figure 1.6 plots the DC link voltage, and the inverter
voltage and current waveforms.
9
Figure 1.5 Battery SOC for full system simulation.
Figure 1.6 DC link voltage, inverter voltage and current.
These results illustrate how different power electronics elements interact to supply the load under
various operating conditions. Here, it was not desired to use grid power to charge the battery, or to inject
surplus power into the grid, thus the grid power was zero until neither the PV nor battery were available,
at which point it was used to serve the load. The waveforms illustrate the effectiveness of the LCL filter
in providing a sinusoidal voltage and current. Total Harmonic Distortion (THD) was determined to be
around 4.9% for the current, and was negligible for the voltage waveform. The DC link voltage was
maintained around 400 V with minimal ripple.
1.5
Scope and Contributions
The contributions of this these include: 1) performing a quantitative comparison of DC-DC
converter performance, 2) developing an improved, discrete, dual-loop, linear feedback controller for the
10
FIBC, 3) implementing an advanced MPPT capability, and 4) development of a high fidelity hardware
prototype and presenting experimental results.
Many DC-DC converter topologies have been implemented, from very simple boost converter
circuits to very complex resonant mode converters. Chapter 2 includes a quantitative simulation analysis
of FIBC compared to other, more conventional converter topologies. Each will be evaluated using a
simulated PV array, at rated load, with simple open-loop controls dictating the switching duty cycle.
In order to have a more realistic hardware implementation of the FIBC, an embedded
microcontroller was chosen for implementation, rather than a real time simulation engine. This requires
the development of a discrete control algorithm that can be executed using a commercially available
microcontroller. This will use a linear feedback control architecture and will control both the inductor
currents and output capacitor voltagse. MPPT control will also be included. The performance of different
MPPT techniques in both the analog and discrete domains will be evaluated, and one method will be
chosen for implementation.
The previous hardware prototypes of the FIBC topology as described in [6], [7] were operating in
open-loop mode. It was also demonstrated for fuel cell applications using a dSPACE real time simulator
[5], [15], [16]. A low fidelity laboratory prototype using an embedded microcontroller was demonstrated
for electric vehicle applications [17]. This high fidelity prototype will designed specifically to
demonstrate the FIBC for PV system applications. It will incorporate MPPT capability. The prototype
will be a closer approximation of commercial hardware. All control functions will be executed by an
embedded microcontroller. Additionally, the prototype will include additional ancillary circuits that are
necessary for commercial hardware, including: gate drivers, analog signal measurement, and overvoltage
and overcurrent protection. This prototype will be demonstrated and experimental results presented.
1.6
Organization
Chapter 1 is an introduction, with key motivation and background information, highlighting the
research and project goals.
Chapter 2 provides additional background on DC-DC converters in general, and the FIBC in
particular, with a complete mathematical analysis coverage.
Chapter 3 conducts an investigation of MPPT algorithms and techniques and a description of the
MPPT algorithm to be implemented in the FIBC.
Chapter 4 describes the controller development and implementation.
11
Chapter 5 presents results of simulation studies which will confirm the correct operation and will
support the definition of performance parameters.
Chapter 6 details the design of the hardware prototype and provides justification for various
design decisions.
Chapter 7 describes the experimental setup and presents the results of the hardware testing.
Chapter 8 contains the final discussion, conclusion, and opportunities for future work.
12
CHAPTER 2
CONVERTER ANALYSIS
This chapter presents a quantitative comparison of the FIBC with conventional DC-DC boost
converter topologies. Converter performance was evaluated using different criteria, such as: efficiency,
voltage/current ripple, switching stress, and switch utilization. A mathematical analysis of the four phase
FIBC is presented, including development of the state space equations, static transfer function, and openloop transfer functions for inductor current and capacitor voltage.
2.1
Converter Simulation Study
A simulation study of several different DC-DC converter topologies was conducted. Several
converter characteristics were calculated and compared to ascertain the most appropriate converter
topology for implementation.
Efficiency is an important consideration with any device design or implementation. In renewable
energy applications, where the cost for energy may be higher than conventionally produced electricity,
minimizing loss is of even greater importance. Therefore, the efficiency of each converter under rated
conditions (Vout = 400 V, P = 5 kW) was evaluated. Efficiency (denoted by η) was calculated by the ratio
of input to output power, as shown in the following equation.
(2.1)
Ripple refers to the variation between a signal (either voltage or current) and its average value.
Excessive ripple may impair system performance by interfering with controls, or may disrupt downstream
devices which require a more constant voltage and/or current. Ripple can be minimized by appropriate
filtering, using passive elements such as inductors and capacitors. Large passive filter elements, however,
will add to the size and cost of the converter, and present a risk of component failure. The energy storage
aspect of passive filter elements will also cause the device to respond more slowly to changes in operating
conditions and control signals.
Ripple is calculated by the following equation:
( )
(
)
(2.2)
13
Although this equation uses voltages, the same equation may be applied to current for
determining ripple.
Ripple was calculated for input voltage and current, output voltage and current, and inductor
current. The maximum, minimum, and average values of each signal were determined while operating
under steady state conditions for a 100 millisecond (ms) duration.
Inductor current was an important criterion that was evaluated for each converter topology. In this
case, the ratio of inductor current to input current was compared. Large inductors with high current
carrying capability are expensive and bulky. Therefore, converters with lower average inductor currents
are preferable.
Switching stress refers to the deleterious effects of high voltages and currents on switching
elements, either typically Integrated Gate Bipolar Transistors (IGBTs) or Metal Oxide Semiconductor
Field Effect Transistors (MOSFETs). Higher stresses require a more robust device capable of sustaining
the higher currents and/or voltages. Devices subjected to increased stress are also at higher risk for failure.
Switching stress was calculated as the product of the root mean square (RMS) transistor current (It,rms) and
the peak transistor voltage (Vt,peak), and is expressed in W, as shown in the equation below.
( )
(
) (
)
(2.3)
Switch utilization is defined as the ratio of switching stress to output power. Therefore, a
converter with higher switch utilization is able to produce a greater power output for a given switching
stress. This is illustrated in the following equation.
(2.4)
A total of eight different DC-DC converter topologies were simulated and analyzed. All
topologies were non-isolated converter types. Isolated converters require transformers which add to a
converters cost, complexity, size, and weight. Additionally, transformers add to the total converter losses,
contributing to lower overall efficiency. For these reasons, non-isolated converters are typically used for
PV power system applications [12].
14
In order to maintain an equal basis for comparison, device ratings and specifications were kept as
similar as possible between different converter topologies. Table 2.1 lists these device ratings and
parameters used for the converter simulation study.
Table 2.1 Device parameters for simulation study.
Device
Description
Rating
Cin
Input capacitor
300 µF
rCin
Input capacitor Equivalent Series Resistance (ESR)
80 mΩ
L
Inductor
30 µH
rL
Inductor DC resistance
40 mΩ
rT
Switch on resistance
4.2 mΩ
VDT
Switch reverse recovery diode threshold voltage
2V
rDT
Switch reverse recovery diode resistance
11.4 mΩ
fsw
Switching frequency
19.9 kHz
Vf
Diode forward voltage drop
2V
rD
Diode resistance
11.4 mΩ
Cout
Output capacitor
1,000 µF
rCout
Output capacitor ESR
120 mΩ
RL
Load resistance
32 mΩ
The results for the six converters are summarized in Table 2.2. The PV was operating under
Standard Test Conditions (STC), defined as an irradiance of 1,000 W/m2 and temperature of 25oC. The
output voltage (VOUT) was 400 VDC and the output power was 5 kW.
15
Table 2.2 Device parameters for simulation study.
Converter
η
VIN
Ripple
VOUT
Ripple
IIN
Ripple
IOUT
Ripple
Switching
Stress
(kW)
Switch
Utilization
1.0
37.156
0.13
1.121
46.225
0.09
IL,avg
/IIN,avg
Boost
91.0%
9.5%
4.1%
74.8%
1,105.3%
BuckBoost
86.0%
21.7%
4.6%
148.8%
4.6%
Cúk
84.8%
10.0%
2.4%
72.8%
2.4%
1.0
49.695
0.09
SEPIC
83.1%
9.7%
5.8%
75.2%
5.8%
1.0
50.863
0.08
Zeta
84.0%
27.7%
3.1%
176.4%
3.1%
1.0
48.157
0.09
2P FIBC
90.1%
6.4%
3.5%
47.3%
3.5%
0.561
12.023
0.39
4P FIBC
94.4%
1.5%
0.5%
11.5%
0.5%
0.282
6.728
0.73
6P FIBC
94.9%
0.6%
0.3%
4%
0.2%
0.187
5.009
0.99
Of the eight converters which were simulated, only four were at least 90% efficient under rated
conditions: the boost converter and the three different FIBC topologies. These included the two phase
(2P), four phase (4P), and six phase (6P) FIBC. Of these three, the 6P FIBC had the highest efficiency;
however, it was only marginally higher than the 4P efficiency. FIBC topologies had the lowest input
current ripple among any of the topologies which were investigated.
Because the interleaved topology splits the current among multiple inductors, the average current
through each inductor was much lower. The boost converter had very high output current ripple, which
would require a large low pass filter. The FIBCs had much lower output current ripple, and lower output
voltage ripple, than the other converter types. Because of the fact that they use multiple switching
devices, the FIBCs had much lower switching stress and higher switch utilization than any other
topology. Thus, while they do require more switching devices, FIBCs would be able to use less expensive
switches with lower voltage and current specifications, and these devices would be subjected to lower
stress.
16
2.2
Mathematical Analysis
First, the average state space equations governing the 4P FIBC were developed, using the
methodology [18]. Note that all equations developed in this section are relevant only when the converter
is operating in continuous conduction mode (CCM).
The circuit for the 4P FIBC is shown in Figure 2.1.
Figure 2.1 Circuit for 4P FIBC.
The equations were derived assuming ideal devices and components. Figure 2.2 shows the ideal
4P FIBC with ideal switching elements. The switching states are defined such that ux = 0 corresponds to
the non-conducting mode of switch x (where x = 1, 2, 3, or 4); the corresponding diode dx will be
conducting. Therefore, a total of 24 (16) states are possible.
17
Figure 2.2 4P FIBC with ideal switch representation.
The first state examined is one in which all four switches are non-conducting (u1 = u2 = u3 = u4 =
0). This is shown in Figure 2.3.
Figure 2.3 4P FIBC, switching state one.
18
The six state variables for this state can be expressed as:
(2.5)
(2.6)
(2.7)
(2.8)
⁄
(2.9)
⁄
(2.10)
(2.11) where the output DC link voltage (vDC) can be expressed in terms of the input voltage and state
variables by the equation:
(2.12)
This expression for the output voltage is valid for all switching states.
The next state examined is u1 = u2 = u3 = 0, u4 = 1. This state is illustrated in Figure 2.4.
19
Figure 2.4 4P FIBC, switching state two.
The state equations for this state were determined to be:
(2.13)
(2.14)
(2.15)
(2.16)
⁄
⁄
20
(2.17)
(2.18)
The third state is defined as u1 = u2 = u4 = 0, u3 = 1. The circuit corresponding to this state is
shown in Figure 2.5, followed by the state equations for this state.
Figure 2.5 4P FIBC, switching state three.
(2.19)
(2.20)
(2.21)
(2.22)
⁄
⁄
21
(2.23)
(2.24)
The fourth state is u1 = u3 = u4 = 0, u2 = 1. This state is illustrated in Figure 2.6.
Figure 2.6 4P FIBC, switching state four.
The state equations for this state are:
(2.25)
(2.26)
(2.27)
(2.28)
(2.29)
⁄
⁄
22
(2.30)
The fifth, and final, state which was examined is u2 = u3 = u4 = 0, u1 = 1, and is illustrated in
Figure 2.7, followed by the corresponding state equations.
Figure 2.7 4P FIBC, switching state five.
(2.31)
(2.32)
(2.33)
(2.34)
(2.35)
⁄
⁄
23
(2.36)
State-space equations can then be developed for each switching state of the converter. Using an
average value for each switch (ux,avg), the average state space equations can be written as:
(
)
(
)
(2.38)
(
)
(2.39)
(
)
(2.40)
(2.37)
(
)
(
)
⁄
(2.41)
(
)
(
)
⁄
(2.42)
Next, it is assumed that all inductors and capacitors have equal values, that is L1 = L2 = L3 = L4 =
L, and C1 = C2 = C. The average values of each switch are also assumed to be equal, thus u1,avg = u2,avg =
u3,avg = u4,avg = U. The state equations can then be rewritten as normalized average equations by making
the following substitutions [18]:
24
√
√
√
√
( )
(
√
(
(2.43)
)
)
The six average, normalized state space equations for the 4P FIBC can be expressed as:
̇
(2.44)
̇
(2.45)
̇
(2.46)
̇
(2.47)
(2.48)
̇
(2.49)
̇
where the normalized output voltage
is
and
25
√ .
The control objective is to regulate the output of the converter to an equilibrium value. This is
done by applying the appropriate control input u which results in an average switch value U. The 4P
FIBC is typically operated with all switches operating with the same duty cycle, each phase shifted 90 o
apart [15]. Therefore, for normal operation, the average values of the four switches u1,avg = u2,avg = u3,avg =
u4,avg = U. Under normal, steady state operation where the output variable(s) are controlled to their
equilibrium values, the time derivatives of the state variables will be zero. Therefore, the static transfer
function of the converter can be determined by setting the normalized average state equations to zero,
using the average equilibrium values of the state currents and voltages (written as ̅̅̅) [18].
(
)
(
(
)
̅̅̅
̅̅̅
)
̅̅̅
̅̅̅
̅̅̅
(̅̅̅)
)
(
(
) (
)
(
(
) (
)
(2.50)
(
)
)
Solving these equations yields:
̅̅̅
(
̅̅̅
̅̅̅
)
(
̅̅̅
)
̅̅̅
(
)
(2.51)
(2.52)
(
)
(2.53)
̅̅̅
Assuming that the steady state, equilibrium current is identical through each inductor, the first
two equations can be rewritten as:
̅̅̅
̅̅̅
̅̅̅
̅̅̅
(
)
(
)
The steady state, static transfer function for the output voltage is thus determined to be:
26
(2.54)
( )
̅̅̅
̅̅̅
(2.55)
This reveals one of the implicit advantages of the FIBC as compared to a conventional boost
converter, whose static transfer function is [14]:
( )
(2.56)
The (1+U) expression in the numerator of the static transfer function for the FIBC allows it to
produce a higher voltage gain for the same duty cycle than a conventional boost converter.
Next, it is assumed that in each switching period the average voltage across the inductors and the
average current through the capacitors are null. In addition, in steady state the average current is assumed
to be identical through each inductor, and the average voltage is equal across both capacitors. Then, the
output/input voltage ratio (voltage gain) can be found by analyzing one of the passive elements that
transfers energy from input to output. Choosing the inductor L1 operating in CCM, the following equation
can be defined:
(
)[
(
)]
(2.57)
Based on (54) and (56) the desired transfer functions may be found, such that U’ is the duty cycle
complement (1-U) [15].
( )
( )
( )
( )
( )
( )
(
)
(
(
) (
(
where:
27
(2.58)
)
)
)
(2.59)
√
√
(
)
(
)
(
(
)
(
)
[
(
(
)]
)
(
)
(
)
(
(
2.3
)
)
)
Bidirectional Converter
For battery system applications, a bidirectional converter is required that can interface between
the battery voltage and the DC-link voltage, which is typically of much greater magnitude. Unlike
converters for fuel cell or PV application, in which current flows only from the source (low voltage) side
to the DC link (high voltage) side, current in a battery system must be able to flow in either direction to
charge or discharge the battery. The FIBC could be adapted for this purpose. If the four diodes (D1-D4)
were replaced with additional switching devices with complementary switching signals, current would be
able to flow in either direction. This is illustrated in Figure 2.8. The PSIM simulation results of the power
flow, shown in Figure 2.9, illustrate the ability of this topology to go from charging (negative power
flow) to discharging (positive power flow) at time t = 2s.
28
Figure 2.8 Bidirectional 4P FIBC.
Figure 2.9 Power results for bidirectional 4P FIBC.
2.4
Conclusion
This chapter presented the results of a quantitative simulation study of different, non-isolated DC-
DC boost converter topologies. The results highlighted the advantages of the FIBC topology over other,
conventional topologies. These included: improved efficiency, lower ripple, and reduced switching stress.
Increasing the number of phases in the FIBC increases these benefits. However, the performance
29
advantages of the 6P over the 4P were marginal, and thus were deemed insufficient to justify the
additional components required. For this reason, the 4P FIBC converter was chosen as the most promising
candidate for this application. A method for developing a bidirectional version of this circuit was also
presented with simulation results.
A mathematical analysis of the 4P FIBC was conducted. The average state space equations for the
six state variables (four inductor currents and two capacitor voltages) were developed for CCM operation.
These were used to obtain the steady state, static transfer function for the output voltage. This verified
that the 4P FIBC has a higher voltage gain compared to a conventional boost converter for a given duty
cycle. Using the steady state, static transfer functions, the transfer functions for the inductor current vs.
duty cycle and capacitor voltage vs. duty cycle were developed. These will be used to develop the linear
feedback controllers in Chapter 4. In addition to regulating current and voltage, the controller must be
able to execute MPPT. Chapter 3 provides an overview of different MPPT techniques, and a description
of the chosen method for this prototype.
30
CHAPTER 3
MAXIMUM POWER POINT TRACKING
Solar PV modules have a non-linear voltage-current relationship with a complex dependence of
the PV module performance upon solar-irradiance intensity and PV module temperature. For part of their
operational range, PV modules can be considered approximately current sources, while for the other
portion of their range they can be considered to be voltage sources. The result of this is that there exists
one point along the voltage/current curve for which the power produced by the PV module is at its
maximum. Therefore, the MPP varies under varying irradiance and temperature conditions, and a realtime impedance matching with the load is necessary for optimization of the power conversion.
Due to the relatively low conversion efficiency and high cost of PV technology, extracting the
maximum useful power is an important design criterion for PV power systems. Therefore, a number of
techniques have been developed in order to operate PV systems at their MPP. These techniques are
known collectively as MPPT.
3.1
MPPT Algorithms
Many different MPPT algorithms have been developed and used [20], [21]. Some are very
simple, and can be easily accomplished using analog control techniques. One of the simplest is the CV
technique, which maintains the PV array voltage at a predetermined limit, which corresponds to the MPP
under a specific set of atmospheric conditions [21]. When operating outside of the predetermined
conditions, this will only approximate the true MPP. Other approximate MPPT techniques include the
short current pulse and open circuit voltage techniques. The SCP periodically shorts the PV module (or
array). A current reference can be calculated as a percentage of the short circuit current (typically 92%)
[21]. The OCV works similarly by open circuiting the array and determining a voltage reference based on
the open circuit voltage (generally around 76% of the open circuit voltage) [21]. Each of these suffers the
disadvantage of requiring additional switches to short or open the PV modules (or arrays). In addition, no
power is produced during the period in which the panel is in a short or open condition [21].
Another approximate method, known as the beta method, uses an intermediate variable, . This
variable is defined by the following equation [26].
(
)
where the constant c is related by:
31
(3.1)
(3.2)
Here, q is the electron charge, η is the diode ideality factor of the panel, KB is the Boltzmann
constant, T is the rated temperature, and Ns is the number of PV cells in series. This method works by
continuously calculating
reference value
using measurements of the voltage and current, and comparing it against a
The MPPT algorithm can then operate using a conventional feedback control loop.
One disadvantage to this method is that
is a function of temperature. Therefore, this technique will not
accurately track the MPP when operating outside rated temperature, unless c and
are updated in
response to temperature.
Figure 3.1 P&O MPPT algorithm.
These approximate MPPT methods are best suited for analog implementation. More accurate
methods attempt to determine the exact MPP rather than an approximation, but are best implemented
using a digital controller. One of these, the P&O method, works by inducing small changes in the
operating voltage or current of the PV module and determining whether the power increases or decreases.
If the induced change increases the power output, the operating conditions will be incremented in the
32
same direction. If the power decreases, the increments will be reversed. A flow diagram, shown in Figure
3.1, illustrates the decision structure utilized by the P&O technique. This method has a tendency to
oscillate around the MPP, and can be ineffective under rapidly changing atmospheric conditions [20].
The IC method attempts to remedy these shortcomings [27]. It works based on the fact that the
derivative of the power with respect to the voltage should zero at the MPP. This derivative can be
expressed by [20]:
(
)
(3.3)
From this, it can be determined that:
⁄
at MPP
⁄
left of MPP
⁄
right of MPP
(3.4)
Using these inequalities, the MPP can be achieved. Additionally, the IC technique indicates both
the direction and distance of the operating condition from the MPP. A modification to this technique uses
a feedback control loop to drive
⁄
to zero [20]. The flow diagram in Figure 3.2 shows the
decision structure for the IC technique [27]. The main disadvantage for the IC algorithm is that it is
computationally complex, requiring many division operations.
33
Figure 3.2 IC algorithm flow diagram.
Two exact MPPT techniques, P&O and IC, were implemented in simulation using both an analog
and a digital controller. These were chosen because they have the best demonstrated performance [20],
[21]. In addition, they do not require additional hardware components, such as switching devices to open
or short the array, as are required by the open circuit voltage and short current pulse methods. These
techniques are also not temperature dependent, which is the case for the beta technique [26].
The output of the MPPT was added to the current reference from the voltage controller (see
Chapter 4). For the analog version, both methods used an increment/decrement interval (Δ) of 0.2 mA.
For the digital implementation, the controller exhibited a greater tendency to overshoot. In order to
compensate for this, Δ was scaled according to the output voltage error (
(
)).
Thus, when the DC link voltage was far from the desired value, the MPPT used a larger Δ to converge
more quickly. As the converter approached the nominal DC link voltage, Δ was decreased to minimize
oscillations and deviations from the nominal voltage. This adaptation allowed the controller to quickly
converge to the MPP while minimizing overshoot. However, it can only be applied in situations where no
other device is regulating the DC link voltage. If another device is regulating this voltage (e.g., an
inverter, battery, etc.) then this technique cannot be used.
34
One notable issue with implementing MPPT for the 4P FIBC was in accurately determining the
total input current (IIN); many MPPT strategies require IIN in order to work correctly. For the FIBC, IIN is
the sum of the inductor currents (where P is the number of phases) minus the load current:
∑(
)
(3.5)
This is because the load (output) current is common to both the inductors on the non-floating and
floating phases. Therefore, in order to obtain the input current, a fifth current sensor must be added to
measure either the total input current, or the output current, so that the input current can be obtained as in
(3.5). As the magnitude of the output current would be significantly lower, it would be more economical
to measure this current.
3.2
Conclusion
MPPT is necessary to extract the maximum usable power from solar PV systems operating under
varying temperature and irradiance conditions. Many different MPPT methods have been developed and
implemented. These techniques vary from simple, approximate methods, which are best suited for analog
implementation. More advanced, exact methods can be implemented using digital controls. The P&O
method has a tendency to oscillate around the MPP, and can be negatively affected by rapidly changing
atmospheric conditions; the IC method attempts to remedy these shortcomings.
When implementing these MPPT, the total input current is required. In the case of the FIBC, an
additional current sensor is required. Either the input or output current must be measured in addition to
the four inductor currents to obtain this value.
Chapter 5 presents the simulation results for the IC and P&O techniques under various operating
conditions, using both analog and digital control algorithms. The development of the analog and digital
controllers is discussed in Chapter 4.
35
CHAPTER 4
CONTROL DESIGN
The controllers were designed for the 4P FIBC using a frequency analysis based on Bode
diagrams. Proportional-integral (PI) controllers were used for the voltages and currents. The controller
gains were defined by the crossover frequency (fc) and phase margin (PM), such that infinite gain was
related to zero steady-state error, and the crossover frequency was related to the setting time of the
compensated system. First, an analog controller was developed, using the Bode diagram frequency
analysis. Then, a discrete controller was developed based on the analog controller.
4.1
Analog Control Design
The analog controller had two outer voltage control loops that independently regulated the two
output capacitor voltages in order to achieve the desired DC link voltage. This used the fact that the
output DC link voltage of the FIBC is the series combination of the two capacitor voltage, minus the input
(PV) voltage, or:
(4.1)
The reference value for the two capacitors can be expressed as a function of the desired output
voltage (VDC*) and input voltage by:
)⁄
(
(4.2)
This approach is different from the dual loop controller used by Kabalo, et al., in [16], in which
the outer loop controller regulated the total DC link voltage. Garcia, et. al., in [17] used a similar strategy
in which both output capacitor voltages were controlled independently. For this application, controlling
the two capacitors individually was found to yield better performance, particularly in low irradiance
condition and the corresponding voltage-current response of the PV.
The open-loop input and output voltage response for the 4P FIBC is shown in Figure 4.1. The
figure illustrates that past a certain point, increasing the duty cycle causes the PV to enter its current
source region, and the voltage to decrease. The decreased input voltage leads to decreased output voltage.
36
Figure 4.1 Open loop input and output voltage response.
If only the output voltage is controlled, an overshoot in the controller will cause the voltage to
cross the knee-point of the curve, and then decrease. The controller will attempt to compensate by
increasing the duty cycle, which will cause the output to go even lower, until the controller eventually
saturates. In contrast, by controlling the capacitor voltages, the reference is dependent on the magnitude
of the input voltage, as shown in (4.2). Therefore, the input voltage can act as a feed-forward term,
making the controller more robust and allowing faster crossover frequency.
The benefits of this strategy are most apparent in low irradiance conditions, where the knee point
of the voltage curve occurs at a lower value of input current. This is illustrated in Figure 4.2, in which the
irradiance steps from 200 to 300 W/m2 at time t=1 s.
Figure 4.2 Power response for VC and VDC voltage control strategies for a step change in irradiance from
200 to 300 W/m2 at time t=1 s.
37
The capacitor voltage (VC) control scheme showed a much more stable response. The VDC
control scheme showed steady state stability problems, and failed to converge following the step
irradiance change.
The output from the voltage controller [Cv(s)] then fed four, independent, PI current controllers
[Ci(s)] that regulated the four inductor currents. An additional term from the MPPT was added to this
current reference. The outputs from the current control loops were then used as the modulation signals for
four Pulse Width Modulation (PWM) controllers, which provided the gate pulse signals for the four
MOSFET switches independently. The PWM controllers used 20 kHz switching frequency, where
triangle wave carrier signals were phase shifted 90o apart. This control scheme topology is illustrated in
Figure 4.3.
Figure 4.3 Control block diagram for 4P FIBC.
38
4.2
Current Control Loop
The previous studies supported the choice of a dual loop controller was used. A faster, inner
current control loop integrated the MPPT functions, while an outer voltage control loop maintained the
desired DC link voltage. The current and voltage control loops represented in Figure 4.3 can be
incorporated in closed-loop, as indicated in Figure 4.4. All sensor gains, current (Ki) and voltage (Kv),
were taken to be unity, as well as the PWM transfer function.
Inner current control loop
V*1,2
+-
ev
Cv(s)
i*L
+-
ei
Ci(s)
Ki
m
iL
PWM
u
Gv(s)
v1,2
Gi(s)
Kv
Figure 4.4 4P FIBC control loops.
The inner current control loop was designed first, considering only the closed control loop inside
of the dashed box in Figure 4.4. The fc and PM were defined as 1.5 kHz and 75°, respectively. Using
classic frequency control methods, the Bode diagram of the open loop response for the uncompensated
and compensated system has been plotted in Figure 4.5.
( )
(
)
(4.3)
39
Figure 4.5 Bode diagram of the open loop uncompensated and compensated current control loop of the
FIBC control scheme.
4.3
Voltage Control Loop
After the current controller, the voltage control loop was designed, which depended on the inner
current control loop. The desirable fc and PM were designed to be 5 Hz and 85°. This low crossover
frequency was used to help with steady state stability; at higher values of fc, there were oscillations in the
steady state current response. This may have been due to the voltage ripple across these capacitors; using
low pass filters with a low fc might allow the bandwidth of this controller to be increased.
The PI controller was designed based on these values for fc and PM, and the Bode diagram of the
open loop, compensated system is shown in Figure 4.6, which showed that fc = 5 Hz and PM = 85°.
( )
(
)
(4.4)
40
Figure 4.6 Bode diagram of the open loop uncompensated and compensated voltage control loop of the
FIBC control scheme.
4.4
Discrete Controller
A discrete controller was developed using the previously developed analog controller. For the
discrete controller, the analog PWM was replaced with a discrete PWM [25].
The PI controllers were replaced with discrete versions. Several methods for developing discrete
versions of PI controllers exist [25]. For the backward Euler method output of the integration,
( ),
utilizes the following expression:
( )
where
is the integral gain,
( )
(
)
(4.5)
is the sampling period, and ( ) is the error for sample k [25]. The digital
expression of the complete PI loop can then be expressed as:
( )
where
(
)
(
)
is the proportional gain.
41
( )
(
)
(4.6)
Another method of implementing a digital approximation of a PI controller uses a trapezoidal
technique known as the Tustin method. This uses the weighted average of the present and previous error
terms for the integration, reducing low frequency distortion [25]. This is expressed by:
( )
(
) (
)
( )
(
)
(
)
(4.7)
Both the backward Euler and Tustin methods were employed in simulation and hardware. The
Tustin appeared to perform better than the backward Euler technique, and was therefore used, although
the performance difference was very slight.
According to the Nyquist theorem, the sampling frequency should be more than twice (and up to
an order of magnitude greater than) the switching frequency. However, sampling at this high rate would
impose an unnecessarily high computational burden. Also, as the modulation index is only updated once
per switching cycle, the feedback sampling rate should also be updated once per cycle. In order to obtain
a working controller while only updating the state feedback values once per cycle, the signals can be
filtered using a low pass filter to extract the average value. This filter must have a crossover frequency
that is much lower than the switching frequency, which reduces the system’s bandwidth and increases the
controller’s response time. Another solution is to synchronize the samples according to the switching
pulses.
Assuming that the ripple in the state variables is equal to the switching frequency, the average
value occurs during the middle of the switch on or off period. By timing the sampling to occur during this
time, the average value of the state variable can be obtained. This allows the controller to function
without requiring low pass filtering to obtain the signal’s average value [25]. For the discrete controller,
each inductor current was sampled at the middle of the switch on or off period. The voltages, which were
subject to higher frequency ripple than the currents, had to be filtered through a low pass filter with a 50
kHz crossover frequency prior to sampling. By employing these strategies, all feedback variables could be
sampled only once per switching cycle, thereby minimizing the computational burden.
4.5
Conclusion
This chapter provided an overview of the development of a discrete, dual-loop, linear feedback
controller for the 4P FIBC. First, an analog controller was developed, which was then discretized. Four
independent, inner current loops regulated the current through the four inductors. An outer voltage loop
controlled the voltage across the two output capacitors. Controlling the two capacitor voltages
42
independently was found to offer improved performance compared to controlling the complete DC link
voltage. The output of the MPPT was added to the output of the voltage control loops.
PI controllers were used for each control loop. The proportional and integral gain terms were
calculated using frequency analysis based on Bode diagrams. The output of the four current control loops
set the modulation index for the four PWM controllers.
A discrete controller was developed from the analog controller. The analog controllers were
replaced with discrete versions using the Tustin approximation method. By synchronizing the sampling
times to occur at the center of the switch on or off pulse, the average value of the inductor currents could
be obtained without the use of low-pass filters. A digital PWM replaced the analog PWM. Simulation
results comparing the performance of the analog and discrete controllers, using two different MPPT
techniques, are provided in Chapter 5.
43
CHAPTER 5
MODELING AND SIMULATION
Computer based modeling and simulation techniques have been important to evaluate the
controller performance. The control tools available in Matlab/Simulink (a block diagram based simulator)
were used to assist in the control development, and final simulations were conducted using PSIM (a
circuit based simulator). Both analog and discrete controllers were simulated to evaluate the performance
of the discrete controller with respect to the analog version. Two different MPPT methods were simulated
using both analog and discrete controllers.
5.1
Simulation Description
Matlab/Simulink was used to develop the analog and digital controllers. After being designed in
frequency domain, the analog controller was then implemented using PSIM software, and validated
against the Simulink results. The discrete controller was simulated in C code using a C block function
available in PSIM.
Two MPPT methods, the P&O and IC techniques, were implemented using the analog controller.
Their performance was evaluated in response to step changes in solar irradiance at various temperatures.
The controllers were evaluated according to the total energy delivered to a resistive load, and the input
current and voltage ripple.
The output of each MPPT algorithm was added to the inductor current reference that came from
the voltage control loops. A Δ of 0.2 milliamperes (mA) was used.
Both MPPT algorithms were tested with two step changes in irradiance: 1) 1,000 W/m2 to 500
W/m2, and 2) 500 W/m2 to 600 W/m2. These two step changes were conducted at three different
temperatures: 1) 10° C, 2) 25° C, and 3) 40° C. Thus, a total of six simulations were conducted for each
algorithm.
After conducting the simulations using the analog controller, the P&O and IC algorithms were
also evaluated using the discrete controller, using the same six simulation scenarios.
All the simulations were conducted using PSIM with a fixed simulation time step of 0.5 µs. The
input to the 4P FIBC was a PV array based on 26 Kyocera KC200GT PV modules in a 2 series/13 parallel
configuration. This PV module was selected because it has been well characterized and accurate models
have been developed by Villalva, et al., in [28].
44
The output, a resistive load, was varied in accordance with the power produced by the PV array,
so that a constant voltage could be maintained under varying irradiance conditions. For the three
irradiance conditions—1,000, 600, and 500 W/m2—the resistor values used were 27, 45 and 54 Ω,
respectively.
5.2
Simulation Results
The step change in the PV power output in response to a step decrease in λ from 1,000 W/m2 to
500 W/m2 for the P&O method using the analog linear feedback controller is plotted in Figure 5.1. The
response for the IC was nearly identical, and has been omitted.
Figure 5.1 Step response for analog P&O.
When used with the analog controller, the P&O and IC techniques had virtually indistinguishable
performance. Both delivered nearly identical amounts of energy to the load, and both were able to operate
with very little ripple. Input voltage and current ripple were calculated to be less than 1% for both MPPT
algorithms. Next, the P&O and IC algorithms were evaluated using the discrete controller.
One issue that was encountered with the discrete controller implementation was that the voltage
control loop tended to overshoot, driving the inductor current reference too high, and causing the system
to saturate at the PV array’s short circuit current. This was particularly evident under low solar irradiance
conditions. To compensate, the gain values for the voltage control loop were reduced. A reset for the
integral term was introduced; when the PV voltage was detected to drop below a certain threshold (e.g.,
20 VDC), the integral term of the voltage control loop was reset to zero.
In order to increase the convergence time while avoiding overshoot, an adaptive MPPT method
was developed. Rather than a fixed Δ, it was scaled according to the output voltage error. The Δ was set
45
to equal 5*10-6*(VDC*-VDC). In this way, the MPPT converged quickly but avoided overshoot. Figure 5.2
shows the PV power responses for a fixed versus a variable Δ using the discrete IC controller with a step
change in irradiance from 1,000 W/m2 to 500 W/m2 at 25 oC. It shows that the variable delta was able to
converge much more quickly following the change in irradiance. This technique, however, is only valid
when only the PV boost converter is controlling the DC link voltage. If another device is regulating this
voltage (e.g., an inverter or other DC converter) then this technique will no longer work, and a fixed Δ
must be used.
Figure 5.2 Fixed versus variable delta for IC MPPT, with step change in irradiance from 1,000
W/m2 to 500 W/m2 at t = 0.5 s.
The PV power for the discrete P&O and IC MPPT controllers in response to a step change in
irradiance from 1,000 W/m2 to 500 W/m2 at 25 oC is plotted in Figure 5.3 and Figure 5.4. In the discrete
implementation, the P&O technique had a more observable ripple and tended to oscillate. The IC method,
in contrast, was much smoother and more stable, particularly in response to the step change in irradiance
at t = 1 s.
46
Figure 5.3 Step response for discrete P&O.
Figure 5.4 Step response for discrete IC.
The energy delivered to the load, in Joules (J), for the analog and discrete versions of the two
MPPT methods is listed in Table 5.1. (Note: 1 J is 1 W/s.) While in the analog mode, input current ripple
was very low (< 1%), the discrete P&O and IC methods had input current ripple values of 6.36% and
2.90%, respectively. Ripple is increased because of the discretely sampled feedback values; in the analog
mode, the MPPT controller could respond instantaneously to variations in the operating conditions. In
contrast, when using the discrete controller, feedback variables were sampled only once per switching
period. This increased ripple resulted in lower energy capture, as the ripple causes the PV to deviate from
its MPP. Overall, the discrete P&O delivered on average 11.84% less energy. The discrete IC had better
performance, delivering on average 1.69% lower energy.
47
Table 5.1 MPPT Simulation Energy Results Comparison
T=10o C
T=25o C
T=40o C
Step
Step
Step
Step
Step
Step
decrease
increase
decrease
increase
decrease
increase
P&O
4,514
3,312
4,287
3,151
4,058
2,988
IC
4,514
3,312
4,287
3,151
4,056
2,988
P&O
3,718
2,762
3,789
2,940
3,694
2,703
IC
4,358
3,159
4,250
3,132
4,013
3,001
Technique
Analog
Discrete
Percentage Difference
P&O
-17.63%
-16.61%
-11.62%
-6.70%
-8.97%
-9.54%
IC
-3.46%
-4.62%
-0.86%
-0.60%
-1.06%
+0.44%
These results show that the P&O and IC methods had nearly identical performance when
implemented with the analog controller. In the discrete version, both MPPT algorithms delivered less
energy to the load, particularly at low temperature. However, the P&O performance was much more
degraded with the discrete controller compared to the IC method.
5.3
Conclusion
These simulation results validated the effective performance of the analog and discrete controllers
for the 4P FIBC. They demonstrated that both the P&O and IC MPPT algorithms were able to effectively
respond to a step change in irradiance. When using the analog controller, in which state feedback
48
variables were continuously updated, both MPPT algorithms had virtually indistinguishable responses.
When the system was discretized, and feedback variables were discretely sampled once per switching
cycle, the performance of both MPPT algorithms decreased, as measured by the amount of energy
delivered to the load. However, the P&O method was more severely impacted by the discrete controller
than the IC. Overall, the discrete P&O delivered nearly 12% less energy as compared to the analog
version. The IC, in contrast, had a less than 2% reduction in energy capture compared to the analog
version. Therefore, the IC method appears to be the better solution for implementation in a digital
microcontroller. Chapter 6 describes the development of the hardware prototype and experimental setup.
49
CHAPTER 6
EXPERIMENTAL PROTOTYPE DEVELOPMENT
A hardware prototype was constructed based on a Microchip dsPIC33FJ256GP710A embedded
microcontroller. The prototype was designed for a low voltage input in the range of 48-72 VDC, with a
nominal 400 VDC output at 5 kW. The implemented control functions were: sampling analog feedback
signals, implementing the dual-loop linear feedback control algorithms, performing MPPT, and providing
the switching signals to the MOSFETs.
Four LEM LAH-25 NP Hall Effect Current Transducers (CTs) measured the inductor currents,
while four LEM LV-20 P Hall Effect voltage sensors monitored the input, output and capacitor voltages.
The outputs from the measurement devices were passed through op-amp signal conditioning circuits that
scaled the outputs to match the analog measurement range of the microcontroller, and provided active low
pass filtering.
An overcurrent protection circuit sensed if any inductor current exceeded 50 A. If an overcurrent
was detected, the switching pulses were disabled, and a 200 A relay was opened to isolate the fault.
Overvoltage protection was also included. If the output voltage exceeded 475 V, a 2 kΩ, 100 W resistor
was connected to the DC link by an IGBT to provide dynamic braking. Finally, four gate drivers had to be
designed. These receive the switching signals from the microcontroller and provided the necessary
voltage and current to switch the MOSFETs.
Table 6.1 Selected Component Ratings and Part Numbers.
Name
Cin
C1, C2
Description
Rating
Input
330 µF
capacitor
350 V
Output
1,000 µF
capacitors
250 V
Power
D1-D4
L1-L4
Q1-Q4
diodes
Inductors
50 A
250 µH
50 A
MOSFET
650 V
switches
84 A
50
Part number
LNT2V331MSEC
ECOS2EP102DX
RHRG560
N/A
STW88N65M5
Selected device ratings and part numbers are given for key components in Table 6.1. The inductor
components were custom-manufactured, as commercially available inductors that met the desired current,
inductance, and operational frequency specifications could not be found.
Other hardware related activities included: thermal management and heat sink sizing, signal and
power isolation between different parts of the circuit, and developing basic, proof of concept (POC)
systems.
6.1
Inductor
Custom inductor circuit elements had to be manufactured and procured, as no commercially
available inductors were available which satisfied the following criteria:

20 kilohertz (kHz) operational frequency

Average current of 34.4 Amperes (A)

Peak current of 41.1 A

Inductance value of 250 micro-Henreys (µH) at full rated current

Maximum operating temperature of 180 oC
Magnetics, Inc. provided eight (8) Kool Mu E cores, which are distributed air gap cores made
from a ferrous iron alloy powder for low losses at elevated frequencies [29]. Magnetics, Inc. 00B802001
bobbins were also provided. These materials were delivered to Badger Magnetics for manufacturing.
The Kool Mu 00K8044E026 core has a nominal inductance factor (AL ) of 91 +/-8% nano-Henrys
per Telsa squared (nH/T2) . Using the worst case value of 83.72 nH/T2 and a desired inductance (L) value
of 250 µH, the initial number of turns (N) was determined to be:
√
√
(6.1)
where L is specified in nano-Henrys (nH). Next, the DC bias in Ampere turns per centimeter (AT/cm)
must be calculated, using:
(6.2)
51
where
is the path length of the core, in centimeters (cm).
Based on the permeability vs. DC bias curve found in [29], the permeability at this bias would be
roughly 75% of nominal, yielding an inductance value of roughly 250*0.75=187.5 µH at peak rated
current. In order to compensate, the DC inductance value should be increased by increasing the number of
turns. This is done iteratively by using different values for N, calculating the DC bias, and determining the
derated inductance. Using this process, a total of 68 turns was determined to be required. This would yield
an open-circuit inductance of 421 µH +/-8%, and at full rated current the inductance would be 295 µH +/8%. The test report, included in Appendix A, shows that the open circuit inductance of the four inductors
was between 422.8-436.4 µH. The DC resistance (DCR) for all inductors was 22 mΩ.
It was desired to maintain a peak current density of 500-600 A/cm. Using 9 AWG wire with a
cross sectional area of 70.2*10-3 cm with a peak current of 41.1 A yields a peak current density of 585.5
A/cm, which is within the desired range. The core was able to accommodate 68 turns of 9 AWG wire
with a 35.1% fill factor. Fill factor can be calculated by:
(6.3)
where
is the cross-sectional area of the wire and
is the window area of the core. This fits within
the range for “Full winding,” which spans fill factors between 30-45% [29].
After winding, the completed coils were varnished with Class H insulation. The final inductors
included 6” (15.24 cm) long, 8 AWG, Teflon wire leads that were terminated with soldered ring
terminals. The four completed inductors are shown mounted to the chassis in Figure 6.1. The input
capacitor, bus bars, and heat sink are also visible.
52
Figure 6.1 Completed inductors attached to chassis
6.2
Thermal Management
Initially, IGBT semiconductor switching devices were chosen for the design because of their high
power handling capacity and ability to withstand voltage transients. The IRG7PH35UD IGBT from
International Rectifier (IR) was originally planned to be used, and was implemented as part of the first
POC system. However, switching and conduction losses were determined to be too high with these
devices.
Conduction losses are approximately equal to the collector-emitter voltage during the conduction
period (VCE(on)) times the average current through the device times the duty cycle. Through simulation, the
average current under rated power and voltage conditions was determined to be 27.6 A, with a duty cycle
of 0.75. The typical value for VCE(on) was given as 1.9 V on the manufacturer’s data sheet; the maximum
value was 2.3 V. Using the worst case, conduction losses were calculated as:
(
(6.4)
)
53
Switching losses for the IGBTs were calculated by the sum of the turn-on energy (EON) and the
turn-off energy (EOFF) times fsw. The values for EON and EOFF came from the manufacturer’s data sheet,
and 20 kHz was used for the value of fsw. From this, switching losses were calculated as:
(
)
(
)
(6.5)
Total power dissipation is the sum of conduction and switching losses, or 105 W per transistor.
The basic equation for heat transfer can be written as:
(6.6)
where:
TJ = the junction temperature in oC. (150 oC maximum)
TA = ambient air temperature in oC. (30 oC used)
RθJC = thermal resistance from junction to case of the semiconductor device in oC per Watt (oC/W)
(0.7 oC/W, from manufacturer’s data sheet).
RθCS = thermal resistance through the interface between the semiconductor device and the surface
on which is it mounted in oC/W. (0.35 oC/W from silicon mounting pad data sheet).
RθSA = thermal resistance of the heat sink in oC/W.
From this equation, the required thermal resistance of the heat sink for a single IGBT can be
specified by using:
(
)
(
)
(6.7)
This is an unrealistically small number. No commercially available heat sinks could be identified
that were capable of meeting this requirement. Moreover, this is for a single device. If multiple devices
54
were to be mounted to a single heat sink, thereby increasing the power dissipation, the required thermal
resistance of the heat sink would have to be a negative value.
For this reason, the IR IRG7PH35UD IGBT was replaced with the STMicroelectronics
STW88N65M5 MOSFET. This differed from the previous laboratory FIBC prototypes, which used
IGBTs [5], [17]. Conduction losses for the MOSFET were calculated by:
(
(
)
)
(6.8)
Switching losses were calculated using:
(
)
(
)
(
)
(6.9)
where VDS is the drain to source voltage, ID is the drain current, tr and tf are the rise and fall times (from
manufacturer’s data sheet), and tsw is the switching period (1/fsw).
From these, total power dissipation for the STW88N65M5 was calculated to be 19.46 W, less
than one fifth of the losses compared to the IGBT.
Power dissipation in the Fairchild Semiconductor RHRG5060 power diode consisted only of the
conduction loss, and was calculated by:
(
)
(6.10)
Two heat sinks were used, each supporting two MOSFETS and two power diodes. Total power
dissipation was 67.92 W per heat sink. To maintain a maximum junction temperature of 150 oC, with an
ambient air temperature of 30 oC, the required heat sink thermal resistance was determined to be:
(
(
)
)
Here, RθJC was taken as the average of the MOSFET (0.28 oC/W) and the diode (1.0 oC/W).
55
(6.11)
The 10.08” extruded aluminum heat sink from Heatsink USA, LLC has a thermal resistance of
approximately 0.8 oC/W/3”. Doubling the length will decrease the thermal resistance by approximately
2/3. Therefore, a 6” piece of this heat sink would have a thermal resistance of approximately 0.53 oC/W.
This provides a significant margin of safety, as it is about 32% below the minimum required thermal
resistance.
Changing the IGBT for a MOSFET necessitated a redesign of the gate driver. Because MOSFETs
are more susceptible to transient overvoltages, the snubber was also redesigned, and a Transient Voltage
Suppression (TVS) diode was added.
6.3
Proof-of-Concept Development
Two POC systems were constructed and tested. These were low fidelity, laboratory test circuits
used to evaluate and debug the power stage and ancillary circuits.
The first POC system is shown in Figure 6.2. A single stage boost converter was implemented
using an available inductor. This was not the custom-manufactured inductor that was used for the final
prototype. This system was constructed prior to changing the IGBT for a MOSFET, so the IRG7P35UD
and its associated gate driver were used. The input source was a DC power supply. The switching signal
was provided by a pulse generator. A detailed look at the breadboard is provided in Figure 6.3.
56
Figure 6.2 POC 1.
Figure 6.3 POC 1 annotated breadboard.
After changing from the IGBT to the MOSFET devices, a second POC was constructed to
evaluate the performance of the new semiconductor and gate driver. This did not include the sensor or
signal conditioning circuitry, or the overcurrent protection. A 12 V car battery, protected by a 25 A fuse,
served as the source. In this prototype, the switching signal came from the dsPIC33F microcontroller,
rather than the pulse generator. The custom-manufactured inductors for the final prototype had been
received from the manufacturer; one of these was used as the inductor for the second POC system. A 5
µF, high frequency, polypropylene (PPE) capacitor was added in parallel with the existing electrolytic
output capacitor to minimize output voltage transients.
Figure 6.4 shows the second POC system in operation. The microcontroller provided the pulses
for the switching signal. Once again, this system was operated in open loop. The microcontroller sampled
a 0-10 V analog voltage source, and set the duty cycle from 0-1 based on this external signal. The
incoming 12 V from the battery is stepped up to 35.3 V, a voltage gain of about 3, at a duty cycle of 0.75.
57
Figure 6.4 POC 2.
Figure 6.5 shows the breadboard for the second POC system. This much smaller board consisted
of an: inverting and (nand) gate, optocoupler (for signal isolation), gate driver, and snubber, along with
the diode and MOSFET.
Figure 6.5 POC 2 annotated breadboard.
58
6.4
Snubber Development
The purpose of the snubber is to minimize transients during switching operations. The snubber
consisted of a capacitor and resistor connected in series across the transistors collector and emitter (for
IGBTs) or drain and source (for MOSFETS). Because they are designed to damp high frequency
transients, the capacitors and resistors used must be tolerant of voltage and current transients. For this
reason, PPE film capacitors and carbon composite resistors were used. For IGBT, which was less
sensitive to these transients, snubber values were chosen arbitrarily as 100 nF for the snubber capacitor
(CS) and 1 kΩ, 5 W for the snubber resistor (RS). The waveforms, in Figure 6.6 show minimal transients.
Figure 6.6 VCE (yellow) and IL (blue) waveforms for POC 1, duty cycle = 0.75.
For this test, the input source was the 12 V car battery, and the Tranex Badger custom inductor
was used. The switching source came from a BK Precision 3300 Pulse Generator. The input voltage and
current were 11.8 V and 16.6 A, and the output was 36.1 V and 4.35 A, for an overall efficiency of 80.2%
When the IGBT was replaced with a MOSFET in POC 2, problematic transients were observed,
particularly, at higher duty cycles.
59
Figure 6.7 VDS (yellow) and IL (blue) waveforms for POC 2, duty cycle = 0.75.
For this test, the input source was the 12 V car battery, and the Tranex-Badger custom inductor
was used. The switching pulses came from the dsPIC33F microcontroller. The large transient observed in
the inductor current waveform when the MOSFET was turned off caused the gate driver to fail and made
obtaining accurate measurements difficult. The sinusoidal oscillation observed in the VDS waveform was
the result of a longer 12 AWG wire connection between the diode and output capacitor, and not the result
of the snubber. Input voltage and current were 11.84 V and 14.44 A and output voltage and current were
35.0 V and 4.21 A, for an overall efficiency of 86.2%
Based on the quick snubber design technique described in [30], CS should be about twice the sum
of the output capacitance of the MOSFET (COSS) and the estimated mounting capacitance. At the time, the
IR IRFP4868 MOSFET was being considered, which has a COSS is about 612 pF according to the
manufacturer’s data sheet. Mounting capacitance was estimated to be 40 pF. Therefore, CS should be
around 1,304 pF. Thus, a 1,500 pF PPE capacitor was selected and procured. In the end, however, the ST
Microelectronics (STM) STW88N65M5 MOSFET was selected because of its higher voltage tolerance,
making it less susceptible to transient overvoltages. This MOSFET has a COSS is around 223 pF, which
means that the 1,500 pF snubber capacitor was oversized. However, it was not deemed necessary to resize
60
this capacitor for the new MOSFET; the consequence of this being slightly oversized is the potential for
increased power dissipation in the snubber.
The snubber resistor size was determined based on the drain to source voltage across the
transistor (VDS), which is about 230 V for an output voltage of 400 V and an input voltage of 60 V, and ID,
which was determined to be around 32 A. Thus, RS was calculated to be:
⁄
⁄
(6.12)
The power dissipation required by the resistors can be calculated based on the stored energy in
the capacitor, or:
(6.13)
Carbon composite resistors where chosen due to their improved transient performance compared
to the more common carbon fiber. As 1.5 W or 2 W carbon composite resistors were not found to be
readily available for the desired resistance, two 15 Ω, 1 W carbon composite resistors in parallel were
used for the snubber resistors.
Figure 6.8 shows the improved waveforms for POC 2 with the redesigned snubber. Note that for
these waveforms, the resolution on the current probe was decreased from 100 mV/A to 10 mV/A in order
to ensure that the entire current transient was captured and not clipped due to the output range of the
current probe. This shows that the improved snubber was able to reduce the magnitude and severity of the
current transients, alleviating the interference with the gate driver and measurement instruments.
Reducing the length of the 12 AWG connecting the diode to the output capacitor eliminated the ringing in
the voltage waveform. Input voltage and current were 11.9 V and 15.2 A and output voltage and current
were 37.1 V and 4.47 A, for an overall efficiency of 91.7%. These results validated the correct
performance of the gate driver and snubber circuits. Overall, POC 2, which used the MOSFET, had much
better efficiency compared to POC 1, using the IGBT. This validates the decision to switch from the
IGBT to the MOSFET.
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Figure 6.8 VDS (yellow) and IL (blue) waveforms for POC 2, duty cycle = 0.75.
6.5
Gate Driver
The gate driver circuit is shown in Figure 6.9. The input signal (u1) had to first pass through an
inverting and (nand) gate (U1). The other input of the nand gate was an enable bit; if the enable bit went
low, the switching inputs were disabled (see Section 6.7). The switching signal then passed through an
RC circuit to a Fairchild HCPL2531 optocoupler (U2). This optocoupler allowed the signal ground to be
decoupled from the gate driver, which was referenced to the source of the MOSFET. A 12 V source
connected through a 5.6 kΩ pull-up resistor (R2) provided a 0-12 V input to the STM L6387E gate driver
(U3). This is a dual channel gate driver, but in this instance only the low-side driver was used. The gate
driver was connected to the MOSFET (Q1) through a gate resistor (R3). Like the snubber resistor, this
was a carbon composite material in order to be more robust against voltage transients. An anti-parallel
diode (D2) allowed the transistor to turn off more quickly. Two zener diodes (Z1 and Z2) prevented the
gate to source voltage (VGS) from exceeding the specified maximum of +/-25 V, and protected the gate
against transient overvoltages.
62
Figure 6.9 Gate driver circuit schematic.
6.6
Analog Signal Conditioning
The analog signal conditioning circuits had two primary goals: 1) to provide a 0-3.3 V input that
could be read by the microcontrollers analog input channels, and 2) to provide noise rejection. This was
done using a three stage op-amp analog circuit. The CT circuit is shown in Figure 6.10.
Figure 6.10 CT signal conditioning circuit schematic.
The CTs were LEM LAH 25-NP closed loop, Hall effect sensors that provided a 0-55 mA output
for currents from 0-55 A (1 mA/A). This output current passed through a 100 Ω resistor (R1) to ground,
thus generating a 0-5.5 V signal (100 mV/A). This passed through a TL074 quad op-amp (U1). The first
stage of the op-amp was a non-inverting, unity gain buffer to provide high input impedance. The second
stage was an inverting op-amp with a 10 kΩ trimming potentiometer (trimpot) (P1) that allowed for
variable gain. The final stage was a unity gain, inverting op-amp to negate the inversion of the previous
stage. It contained a capacitor in the feedback loop in order to act as an active low pass filter, with fc near
200 kHz, or 10 times the switching frequency (20 kHz), as given by:
63
(6.14)
The voltage sensor signal conditioning circuit is similar, and is shown in Figure 6.11.
Figure 6.11 Voltage sensor signal conditioning circuit schematic.
A LEM LV-20P Hall Effect voltage sensor has been used, which worked based on a 0-14 mA
input. An appropriately sized resistor was therefore provided to produce the necessary input current based
on the magnitude of the voltage to be measured. The Hall Effect voltage sensor produced a 0-35 mA
output that was passed across a 133 Ω resistor to provide a 0-4.655 V output. Again, this passed through a
three stage op-amp circuit, using a TL074 quad op-amp. Because the voltages are subject to higher ripple
than the inductor currents, a 3,300 pF capacitor was used with a 1 kΩ resistor to provide a low pass filter
with a 48.2 kHz fc.
6.7
Overcurrent Protection
The overcurrent protection circuit used four comparator circuits to compare the voltage output
from the four CTs against a reference value. If the current in any one of the inductors exceeded the
reference, it caused the normally high (5 V) output to go low. This then caused the output of the logic
inverter (U4) to go high. U4 is connected to the clock input of a D-type, positive edge triggered flip-flop
(U5), causing it to change its output Q from high (5 V) to low. As this was an edge triggered device, it
acted very quickly. The output Q was an enable signal that was connected through the nand gate in the
gate drive circuit (see Section 6.5). The inverse output of U5 ( ̅ ) sent a disable signal to the
microcontroller, and opened Relay 2. Relay 2 breaks the neutral connection for the 12 V supply that
powered the coil for the 200 A input relay. The emergency stop button (SW2) is also located on this
neutral path. The circuit returns to normal by pushing the reset button (SW1).
64
Figure 6.12 Overcurrent protection circuit schematic.
65
6.8
Overvoltage Protection
The overvoltage protection system worked on the principle of dynamic braking. A rotary
potentiometer (P1) and a 1 kΩ resistor formed a voltage divider to scale VDC. A Schmitt trigger
comparator circuit (U1) compared this against a 5 V reference value. P1 changed the midpoint of the
hysteresis and the trimpot controlled the high and low trigger values. These were set to turn on at 475 V
and turn off at 425 V. When the overvoltage circuit turns on, transistor Q1 provided a 12 V on signal to
the IR2117 gate driver circuit (U3). U3 is used to drive the IR IRG7PH35UD IGBT. The IGBT was used
for this circuit because of its higher voltage rating, and the fact that IGBTs are more robust against
voltage transients. Q1 closed the neutral connection on a 2 kΩ, 100 W resistor, R10. The additional
output impedance helped to drive the DC link voltage back towards its nominal value.
Figure 6.13 Overvoltage protection circuit schematic.
66
6.9
Complete Circuit
The complete circuit consists of:

Power stage

Four gate drivers

Four analog current signals

Four analog voltage signals

Overcurrent protection

Overvoltage protection
This is shown in Figure 6.14. The complete components list is provided in Appendix B.
67
Figure 6.14 Complete circuit schematic diagram.
68
69
6.10 Hardware Design
The FIBC prototype was built using a 16.75” x 23.5” (42.5 x 59.7 cm) rack for a rack mount
enclosure. The incoming low voltage DC connected to two 1” (2.54 cm) wide, 1/4” (.635 cm) thick,
copper bus bars. The positive bus bar was broken by an OMRON G9EC-1 DC12 200 A, normally open
relay. The 12 V source providing the coil voltage for this relay could be broken in the event of an
overcurrent, or by pushing the emergency stop button. Each bus bar had lugged connections to two
inductors; L1 and L2 were connected to the positive bus bar, L3 and L4 were connected to the negative
bus bar. Additionally, two 8 AWG copper wires connected the neutral bus bar to the Printed Circuit
Board (PCB), where they connected to the source of transistors Q1 and Q2. Two more 8 AWG wires
connected the positive bus bar to the drain of Q3 and Q4.
A pair of 12 AWG wires from the line (positive) side of the 200 A relay connected to a terminal
block on the PCB to provide voltage to the isolated power supplies, so that the on-board controls could be
activated prior to the application of primary power. A 330 µF, 350 V, chassis mount input capacitor was
installed between the positive and neutral bus bars on the load (negative) side of the 200 A relay. A 40 kΩ
resistor in parallel with the input capacitor to provide a path for inductor currents to flow if Relay 2 was
opened.
All primary power connections to the PCB were soldered, 12 AWG wire. The 8 AWG wire from
the inductors and bus bars were terminated on a terminal block. From the terminal block, each 8 AWG
was transmitted by 2 12 AWG wires to the PCB in order to facilitate soldering.
The PCB measured 10” x 16” (25.4 x 40.64 cm) and was placed between two 10.08” (25.6 cm)
heat sinks. The heat sinks were affixed the rack with angled aluminum brackets. The dsPIC33F
microcontroller was used with the Microchip Explorer 16 board. This board was placed in a steel
enclosure that was installed above the PCB, supported by additional angled aluminum brackets. An
additional piece of aluminum was installed across the two heat sinks at the front of the rack to hold the
emergency stop switch, the reset switch for the overcurrent protection, the chassis mount PPE capacitors,
and the panel-mount potentiometer for the overvoltage protection circuit. The high voltage output was
accessed from the front of the PCB; two two-circuit, 60 A Molex terminal blocks were connected to the
positive and negative outputs.
A two layer PCB was designed, using 2 ounce per square foot (oz/ft2) copper thickness and 1/8”
FR4 dielectric. The thicker dielectric was chosen to minimize electromagnetic interference and thermal
heat transfer between layers. This thickness, however, impeded soldering. For future systems, it is
70
recommended to use a thinner dielectric. The board was organized with high current carrying traces along
the outer edges, and control and signal processing circuits near the interior. The high current traces were
required to handle a peak current of 41.1 A. For external traces in air with 2 oz/ft 2 copper weight, the
trace width must be 511 mils in order to limit the temperature rise of these traces to 30 oC [31]. The PCB
is shown in Figure 6.15.
Figure 6.15 PCB for 4P FIBC.
The microcontroller was on the Explorer 16 development board from Microchip. It was
connected to the PCB by 15-pin D-sub connectors. The 15 pins were connected to:

Eight analog inputs (four voltages, four currents)

One digital input (disable)

Four digital outputs (four PWM switching pulses)

Two common wires.
A picture of the hardware prototype is shown in Figure 6.16.
71
Figure 6.16. Hardware prototype.
6.11 Isolation and Electromagnetic Interference
One technical challenge that was unique to this circuit was the multiple numbers of electrical
neutral (common) points within the circuit. A total of five common points existed within the circuit; these
are defined as:

Input source neutral (GND 0) – this will most likely be earth-grounded in most
installations

Signal ground for control electronics (GND 1) – this was kept isolated with respect to the
input ground to prevent circulating currents within the control electronics

DC link negative (GND 2) – this was floating with respect to the input

The source of MOSFET Q3 (GND 3) – the source of this transistor was floating below
ground potential. The associated gate driver must be referenced to this to provide the
proper VGS to turn the transistor on and off.

The source of MOSFET Q4 (GND 4) – see previous.
In addition, the chassis was connected to earth ground, which was kept isolated from all the other
commons. To maintain isolation, a number of isolated power supplies were required to provide control
voltage with respect to the different common potentials. Small, isolated, switching DC-DC power
72
supplies were specified and procured which had a wide input range, from 18 – 75 VDC, and could
therefore be powered from the input source. This would have allowed the hardware prototype to be
completely self-powered. The PCB with the switching DC-DC supplies is shown in Figure 6.17.
Figure 6.17 PCB with switching DC-DC converters.
MOSFETs Q1 and Q2 had their sources at the same potential as the input, so a 12 V power
supply referenced to this common was required for their associated gate drivers. The control electronics
required +/- 12 V and 5 V, so supplies referenced to the signal ground were provided. A switching DCDC supply provided +/- 12 V, and a linear 5 V regulator provided the 5 V using the +12 V supply. The
overvoltage protection circuitry for the DC link had to be with respect to the DC link negative, and
required 12 V and 5 V; the 12 V was provided by a switching DC-DC supply, and the 5 V was from a
linear 5 V regulator. Finally, the gate drivers for Q3 and Q4 each needed their own isolated 12 V power
supply referenced to their sources. Optocouplers were used to maintain isolation between the gate signals
originating from the microcontroller, which was referenced to the signal ground, and the gate drivers,
which were all referenced to the source of their associated MOSFETs.
Although the switching DC-DC supplies were convenient, allowed the prototype to be completely
self-powered, and required very little space on the PCB, they were found to produce significant
Electromagnetic Interference (EMI). The EMI was most noticeable in the analog feedback signals from
the CTs and Halle Effect voltage sensors, particularly in the 350 kHz and 2 Megahertz (MHz) range. As
73
no other circuits were operating at this frequency, the switching power supplies were identified as the
likely culprit. The magnitude of these transients was so severe that it caused the overcurrent protection to
act, disabling the system.
In order to resolve this issue, the switching DC-DC supplies had to be removed, and replaced
with external linear power supplies running off of line voltage. The prototype system, with linear power
supplies, is shown in Figure 6.18.
Figure 6.18 Hardware prototype with external linear power supplies.
Replacing the switching DC-DC supplies with linear power supplies did resolve the EMI issue.
However, this change led to some notable disadvantage: 1) the prototype was no longer self-powered –
120 VAC line voltage was now required, 2) the prototype was now bulkier due to the linear power
supplies, 3) set-up and tear-down of the prototype became more complicated and time consuming due to
the external power connections. Therefore, in order to mitigate these disadvantages, as well as the EMI
issue, future systems should install the switching DC-DC supplies on a separate PCB housed inside a
shielded enclosure. This will allow the system to enjoy the advantages of the switching DC-DC supplies,
notably, being smaller, lighter, and completely self-powered. Housing the supplies separately in a
shielded enclosure will prevent the EMI from impacting the control and/or protection systems of the
FIBC.
74
In addition to the EMI produced by the switching DC-DC supplies, EMI was generated by the
switching transients for each MOSFET, most noticeably in the current and voltage measurement feedback
signals. To prevent these noise transients from impacting the microcontroller, it was run separately on its
own board from the main PCB, and housed inside a steel electrical enclosure. For the low power
conditions under which testing was conducted, this EMI did not appear to adversely impact system
performance. At high power, however, these transients could begin to interfere with the analog feedback
and/or digital switching pulses to a degree that may be detrimental. Further reductions in EMI could be
accomplished by:

Improved snubbers to reduce switching transients

Changing the connector between the microcontroller and the PCB from 15-pin to 26-pin
so that each signal can be a twisted pair with its own common

Separating the control circuitry from the power circuitry and shielding
6.12 Microcontroller Code
The microcontroller code for the dsPIC33FJ256GP710A was written primarily in C, with some
assembly code, using Microchip MPLAB IDE v8.70 and compiled for the device using the MPLAB C30
C compiler. The dsPIC was run at its maximum operating speed of 40 Mega-Instructions Per Second
(MIPS), using an external 8 MHz oscillator and the on-chip Phase-Locked-Loop (PLL).
The four, phase-shifted PWM outputs were generated using a timer with a 2,048 cycle period to
generate a 19.53 kHz switching frequency. This lower frequency was used (as opposed to exactly 20 kHz)
because 2,048 is a power of two, which had computational time benefits when using the fixed-point
calculations (more on this later).
In order to stagger the four PWM outputs, the Continuous Pulse Mode of the Output Compare
channels had to be used, rather than the normal PWM mode for the microcontroller. Typically, when
using digital PWM, the output is set high at the start of each counter period and goes low when the
counter value matches the modulation index. However, for this particular dsPIC, only two of the nine
timers were available for PWM. For this reason, there was no way to stagger the pulses 90o apart using
the normal PWM mode. The Continuous Pulse mode allowed the high and low times for each channel to
be set independently. Although this mode is typically associated with fixed, not variable, pulse widths, it
did not appear to have any adverse impacts on operation. Additional code was required to implement this
switching mode. For future work, it is recommended to investigate the Motor Control (MC) class of
dsPIC33F microcontrollers to see if they can accommodate more flexibility in PWM configuration.
75
Four additional Output Compare channels were configured with periods half the length of the
PWM channels. These triggered an Interrupt Service Routine (ISR) at the center of the on or off period of
each switching pulse. For low duty cycle (< 40%), the ISR was triggered at the center of the off pulse, and
for high duty cycle (>40%) is occurred at the center of the on pulse. This allowed the sample to be taken
on whichever slope was smaller, thus minimizing skewing error. Inside this ISR, the corresponding
inductor current was sampled, the PI control calculations for that current were executed, and the duty
cycle for the next switching period was written. The entire computation time for each current samplecontrol ISR was approximately 5.6 microseconds (µs).
An additional ISR was triggered using a timer with a period of ten switching cycles (512 µs).
This ISR sampled the input voltage and two capacitor voltages and ran the voltage control loops. This
interrupt had a lower priority than the current sample-control ISRs, so that the microcontroller would
continue to execute the current control ISRs at the correct times. This used the Nested Interrupt capability
of the dsPIC microcontroller. The microcontroller required approximately 38.8 µs to sample the three
analog inputs and run the control equations.
For these experiments, which were conducted using a fixed resistive load, it was not possible to
have the MPPT and voltage control loops working simultaneously. A fixed output voltage with a fixed
resistive load would result in fixed power, in which case the MPPT could not function. Therefore, the
MPPT was included in a separate program. First the CV method was implemented, which maintained the
input voltage at a fixed value. The CV method is one of the simplest MPPT methods to perform, and was
used as a baseline against which other methods could be evaluated. The input voltage control loop used
the same techniques and gain terms as the output voltage capacitor control. The MPPT control loop was
in a separate ISR that was executed every 2,048 µs.
In addition to the CV algorithm, the IC method was also implemented. The output of the IC
MPPT was a voltage reference for the input voltage controller used by the CV algorithm, using a variation
(Δ) of 41.7 millivolts (mV). The total computation time required to run the IC algorithm was about 39 µs.
As was mentioned in Chapter 3, the MPPT required the total input current in order to work correctly. This
was approximated as the sum of the inductor currents minus the output voltage divided by the load
resistance.
All calculations were executed using fixed-point arithmetic to allow for very fast computation
time, using 16 bit signed integers. The controller must be modified as follows in order to function with
fixed point integers.
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Figure 6.19 Fixed-Point Integer Control Block Diagram
The controller gain values were determined for unity gain for the feedback signals, and a
modulation index varying between zero and one. In reality, however, the analog feedback signals were
subjected to scaling as they were converted to 10 bit integers by the Analog to Digital Converter (ADC).
All mathematical calculations were performed using 16 bit signed integers; therefore, the modulation
index varied from zero to 215 (32,768). Integral anti-windup was inherently present because after the
controller exceeds this value it would reset to zero. In order to adapt the original gain terms for the fixed
point integer controller, they had to be scaled by m/ Ki where m is the maximum value of the modulation
index (215) and Ki is the signal gain caused by the ADC. To adapt this modulation index to the PWM
carrier varying from zero to a peak value COUNTP, it had to be scaled by COUNTP /m. Making this value
a power of two was beneficial for computational speed; for this reason, the counter period was increased
from 2,000 (corresponding to a switching frequency of 20 kHz) to 2,048 (211) (corresponding to a
switching frequency of 19.53 kHz). Finally, the scaled modulation index was written to the duty cycle
register for the PWM; the duty cycle was limited to 85% for safety and protection reasons.
6.13 Cost
The complete bill of materials for the hardware prototype is included as Appendix C. The total
cost for all parts, components, and materials was approximately $2,367. High volume pricing quotes for
all major components were obtained from manufacturers and/or vendors. It is estimated that with volume
manufacturing, the material cost could be reduced to about $1,330 (roughly 44%). Assuming that the
material cost represents 60% of the total manufacturing cost, the total cost for commercial production of
this device is estimated to be about $2,217.
6.14 Conclusion
A hardware prototype of the 4P FIBC was constructed. Custom inductor components that were
capable of meeting the circuit specifications had to be designed and manufactured. Thermal dissipation
calculations led to the eventual use of MOSFET devices over IGBTs, due to the lower losses within the
MOSFETs. These calculations were used to appropriately size and select a heat sink. Two POC systems
77
were constructed and tested to validate certain aspects of the design and debug issues with the circuits,
including the snubber. A snubber was designed to minimize transients that occurred during the switching
operations of the MOSFETs.
In addition to the power stage, ancillary circuits had to be designed and built. These included four
isolated gate drivers capable of receiving the switching pulses from the microcontroller and driving the
MOSFETs. Analog signal conditioning circuits were required to scale and filter the CT and voltage sensor
measurement signals and provide them to the microcontroller. Overcurrent and overvoltage protection
were implemented as well.
The chassis for the prototype was a 16.75” x 23.5” (42.5 x 59.7 cm) rack for a rack mount
enclosure. The low voltage DC was connected to a 1” x 1/4” (2.54 x 0.635 cm) bus bar. The positive bus
bar was broken by a 200 A, normally open relay contact. The overcurrent protection would trip this relay
to isolate the source in the event of a fault. The PCB was installed between two 10.08” (25.6 cm) heat
sinks that were affixed to the chassis.
The dsPIC33 microcontroller was run on the Microchip Explorer 16 board, which was placed
above the PCB in an aluminum enclosure. The microcontroller was responsible for executing all control
functions for the prototype. These included: sampling analog feedback signals, implementing the dualloop linear feedback control algorithms, performing MPPT, and providing the switching signals to the
MOSFETs. Fixed point integer calculations were used to reduce computational time.
The total cost for the prototype was $2,357. For full commercial production, the total estimated
system cost is approximately $2,210, including manufacturing.
A few design issues were identified that should be noted, and can easily be rectified in future
designs. First, a thinner dielectric (e.g., 1/16”) should be used to facilitate ease of soldering. Second, EMI
from the switch-mode DC-DC supplies must be mitigated by placing these devices on a separate board
and using metal shielding. Third, additional EMI reductions could be accomplished by improved snubbers
for the MOSFETs and/or separating and isolating the control circuitry from the power stage. Finally,
changing the connector between the microcontroller and the PCB from 15-pins to 26-pins would allow
each signal to be paired with its own common, allowing them all to be twisted pairs, further reducing
EMI.
Chapter 7 describes the experimental testing and results using the prototype described in this
chapter, where a comprehensive evaluation and comparison of simulated and experimental data is
performed.
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CHAPTER 7
EXPERIMENTAL TESTING AND RESULTS
Experimental testing of the hardware prototype that was described in Chapter 6 was conducted to
verify correct operation and validate the control algorithms that were described in Chapter 5. First, open
loop operation was conducted to verify the correct operation of the gating signals, gate drivers, and power
stage. Figure 7.1 shows the four PWM pulses from the microcontroller, which were staggered 90 o (12.8
µs) apart. Next, the steady state and step response of the current controller was demonstrated. After that,
the outer voltage control loop was implemented. Finally, the MPPT was applied and validated. All testing
was conducted under low power conditions. This was due to the fact that no low voltage, high current
input source was available, nor was there a suitable high power load bank capable of withstanding 400
VDC.
Figure 7.1 Staggered PWM pulses.
7.1
Current Controller
The current controllers were tested using a 900 W HP 6439B DC power supply for the input and
a 33 Ω resistive load bank at the output. The experimental test setup for these tests is shown in Figure 7.2.
Each of the four stages of the converter was tested individually, then all four together. Figure 7.3 shows
the four inductor currents under steady state conditions for a 3 A reference. The signals came from the onboard CTs, which provided an output of 100 mV/A. Note that EMI from the switching transients can be
79
observed in these output signals. Figure 7.4 shows two inductor currents (IL1 and IL3) along with the input
current (IIN).
Figure 7.2 Experimental test setup for current control testing.
Figure 7.3 Four inductor currents, steady state, 3 A reference.
80
Figure 7.4 Inductor currents IL1 and IL3 and input current IIN, steady state, 3 A reference.
Note that although the inductor currents have the characteristic triangle wave shape typical of a
conventional boost converter, the effect of the interleaving was to yield an input current that was much
more linear. Input current ripple was calculated to be approximately 8.6% under these operating
conditions, whereas the current through the inductors had about 67% ripple.
The step response for a single inductor current, IL2, for a step change in reference from 4 to 8 A at
time t = 2 ms is plotted in Figure 7.5. The plot shows the current waveform as measured by a current
probe, plotted at 1 A per division. Also plotted are the external current reference signal (I*), provided by a
function generator, and the error signal from the microcontroller (e I2). The time is plotted at 2 ms per
division. As the microcontroller did not have a digital to analog converter, the error signal was written as
the duty cycle for an unused PWM channel, and filtered through an RC low pass filter to obtain the
average value. The scaling factor for this signal was 477 mV/Amp error, and it was plotted at 200
mV/division. The step response for the change in reference from 8 A down to 4 A is plotted in Figure 7.6.
Figure 7.7 shows several cycles of the inductor current responding to the step change in reference.
81
Figure 7.5 Step response for inductor current IL2 for a reference from 4 to 8 A at time t = 2 ms, 1
A/division, 2 ms/division.
Figure 7.6 Step response for inductor current IL2 for a reference from 8 to 4 A at time t = 2 ms, 1
A/division, 2 ms/division.
82
Figure 7.7 Step response for inductor current IL2 for a reference from 4 to 8 A, multiple cycles.
The step response for all four inductor currents is shown in Figure 7.8. Because the oscilloscope
only had four channels, the reference is not plotted. Figure 7.9 shows the same condition with the
reference plotted in place of IL3. Figure 7.10 shows multiple cycles of the four inductor currents
responding to the step change in reference value.
Figure 7.8 Step response for four inductor currents for a reference from 2.5 to 4 A at time t = 1 ms, 2
A/division, 1 ms/division.
83
Figure 7.9 Step response for four inductor currents (IL3 not shown) for a reference from 2.5 to 4 A at time
t = 2 ms, 2 A/division, 2 ms/division.
Figure 7.10 Step response for four inductor currents for a reference from 2.5 to 4 A, multiple cycles,
2A/division, 100 ms/division.
These results show that the inner, current control loop was able to quickly and accurately respond
to a step change in input with minimal overshoot.
84
7.2
Voltage Controller
The voltage controller was tested under low voltage, low power conditions due to limitations on
input current and load dissipation capability. The input DC source provided 20 V; the 4P FIBC prototype
increased this to 140 V at the output (a voltage gain of 7). The resistive load consisted of a 157 Ω load
bank and a 300 Ω resistor connected in parallel by a switch. This switch allowed the output load to be
varied from 157 to 103 Ω in order to validate the ability of the voltage controller to maintain output
voltage under a varying load. The experimental setup for the voltage control testing is shown in Figure
7.11.
Figure 7.11 Experimental test setup for voltage control testing.
The output voltage response is plotted in Figure 7.12. These measurements were taken using the
output of the Hall Effect voltage sensor, after the analog signal conditioning. The scale factor for this is
169.7 V/V. The waveform was plotted on the oscilloscope at 50 mV/division (which corresponds to 8.5
V/division when considering the scale factor), 50 ms/division. At the moment when the output load was
decreased from 157 to 103 Ω, the voltage sagged to 131.3 V (6.2%); when the load returned to 157 Ω the
voltage rose to 15.4 V (8.9%). The transient for the load decrease was approximately 76 ms, while when
the load resumed the transient lasted approximately 136 ms.
85
Figure 7.12 Output voltage response to step change in load from 157 Ω to 103 Ω and back, 50
mV/division, 50 ms/division.
Figure 7.13 shows the result for the input current, measured by a current probe, and three of the
four inductor currents (IL1, IL2, and IL4, as measured by the on-board current sensors. (Note that these
sensors produce an output voltage of 100 mV/A.) Figure 7.14 shows the four inductor currents, as
measured by the Hall Effect current sensors.
Figure 7.13 Input and inductor current response for a step change in load from 157 Ω to 103 Ω and back,
2 A/division, 100 ms/division.
86
Figure 7.14 Four inductor current response for a step change in load from 157 Ω to 103 Ω and
back, 2 A/division, 100 ms/division.
These results show that the voltage controller was able to effectively regulate the output voltage
of the 4P FIBC under a varying load. The controller overshoot was acceptable—within 10%. While the
control response was somewhat slow, it was deemed adequate for solar PV applications, which do not
experience extremely rapid changes in operating conditions. Using a low pass filter to eliminate the ripple
from the capacitor voltage feedback signals could allow the bandwidth of the voltage controller to be
increased, which would improve performance.
7.3
Maximum Power Point Tracking
Finally, the MPPT control capability was evaluated. As a PV input source was unavailable, this
was tested by using Thevinin’s theorem for maximum power transfer, which states that for a source with a
series impedance, the maximum power that can be transferred to a series load is achieved when the load
impedance is equal to the source impedance. The 4P FIBC reduces the load resistance as seen by the input
according to:
(
(
87
)
)
(7.1)
By placing a resistor in series with the DC input power supply, the MPPT was expected to vary
the duty cycle such that the load resistance as seen by the input (RIN) was equal to the series source
resistance. The experimental test setup with the source resistance is shown in Figure 7.15. The input
power supply was set for 40 V. Two 15 Ω, 4.47 A rheostats, connected in parallel, were used for the
source resistance. A 102 Ω resistive load was used for the output.
Figure 7.15. MPPT testing setup.
First, the CV algorithm was tested. CV is not the most effective algorithm when using a PV input
source, as the maximum power voltage varies with operating temperature. For this testing scenario,
however, CV would always yield the correct answer if it was set to maintain the input voltage to the
converter at half the source voltage. This made the CV method very useful for the purposes of debugging,
calibrating, and evaluating the IC method.
The source resistance was varied between 2-4 Ω. Table 7.1 compares the input power for the CV
and IC MPPT algorithms compared to the theoretical value. The CV results were taken to be correct, with
any discrepancy attributed to imprecision in the rheostat resistance, and the IC results were evaluated
against these. These results show that both algorithms were able to converge to operating points at or near
the actual maximum power for each value of source resistance. The IC algorithm results were very close
to the CV results for source resistance of 3 Ω and 4 Ω, but diverged for 2 Ω. This is because the IC
algorithm allowed the input voltage to rise for low source impedance, causing it to deviate from the
maximum power point. It is anticipated that for a PV input source, which has higher input impedance, this
will perform better. This is supported by simulation results.
88
Table 7.1 MPPT power comparison.
Source
Input Power
Resistance
(Calculated)
CV Input Power
IC Input Power
Percent
Difference
4Ω
100 W
99.4 W
98.1 W
1.3%
3Ω
133.3 W
132.8 W
132.3 W
0.4%
2Ω
200 W
203.8 W
182.9 W
10.3%
Figure 7.16 shows the simulation results for input power for a duty cycle sweep when a
mathematical model of a PV array was used as the input source, and the input power result using the IC
MPPT method. This figure shows that, when using the PV model as an input source, the IC MPPT
converged to the maximum input power. However, when this array was replaced with a DC source with a
series resistor, the results shown in Figure 7.17 indicate that the same IC MPPT was unable to converge
to the maximum input power, but instead converged to a slightly lower value. For this reason, although
the IC method failed to converge to the maximum power point in these experimental results, it believed
that this algorithm will be capable of reaching the maximum power point when operating with a PV input
source.
Figure 7.16 Simulation result for IC MPPT method with duty cycle sweep using PV model input
source.
89
Figure 7.17 Simulation result for IC MPPT method with duty cycle sweep using DC input source
with series resistance.
Figure 7.18 shows the input voltage and current response for the CV and IC algorithms in
response to a change in source resistance from 2 Ω to 3 Ω. The input voltage was measured using the on
board Hall Effect voltage sensor. This was scaled using the 26.303 V/V scale factor; a five point moving
average was used to reduce the appearance of the ripple resulting from switching frequency EMI that was
present in the sensor output. The input current was measured using a current probe. Note that the CV
algorithm holds the input voltage steady at 20 V (half the source voltage) and only the current varies. This
matches the expected performance for this algorithm, and translates to the maximum power under these
particular operating conditions. In contrast, for the IC algorithm, both input voltage and frequency vary in
response to the changing source resistance. This resulted in lower power capture for the IC method as
compared to the CV, as plotted in Figure 7.19.
90
Figure 7.18 Input voltage and current response for CV and IC MPPT algorithms in response to a
change in source resistance from 2 Ω to 3 Ω.
200
Power [W]
180
160
140
120
Power (CV)
Power (IC)
100
0
2
4
6
8
Time [s]
Figure 7.19 Power response for CV and IC MPPT algorithms in response to a change in source
resistance from 2 Ω to 3 Ω.
The input voltage and current response for the CV and IC MPPT algorithms is plotted in Figure
7.20. Once again, the CV was able to hold the input voltage constant at 20 V, while for the IC method this
voltage varied with source resistance. The input power response for the two methods is plotted in Figure
7.21.
91
Figure 7.20 Input voltage and current response for CV and IC MPPT algorithms in response to a
change in source resistance from 4 Ω to 3 Ω.
Figure 7.21 Power response for CV and IC MPPT algorithms in response to a change in source
resistance from 4 Ω to 3 Ω.
These results show that both the CV and IC methods were able to converge at or near the
maximum power conditions for varying values of source resistance. The CV method was useful for
providing a baseline against which the IC results could be compared. The dynamic results illustrate the
ability of these two methods to respond to changing operating conditions and converge to the new
maximum power. The IC method diverged from the optimal conditions; it is believed that this divergence
is due in part to the different voltage/current relationship for a DC voltage source with a series resistor
when compared to a PV source. Future testing with either a PV simulator or PV array will be necessary to
evaluate the MPPT algorithms under more realistic testing conditions.
92
7.4
Conclusion
These experiments successfully demonstrated all control algorithms for the 4P FIBC under low
power conditions. High power testing was precluded due to the lack of a suitable low voltage, high
current, high power input supply and high power, 400 VDC load bank. The four current controllers were
able to respond very quickly to step changes. Comparing the input current against the individual inductor
currents demonstrated that the interleaving of the FIBC was able to significantly reduce the input current
ripple to less than 10%. The voltage controller was able to maintain the desired value with acceptable
deviation during step changes in load. The voltage controller performance could be increased by using a
low pass filter with a lower fc to more effectively remove the ripple from the voltage feedback signal,
which would then allow the controller bandwidth and gain terms to be increased. Two MPPT algorithms,
the CV and IC, were successfully demonstrated. These were both able to converge at or near the
theoretical maximum power point when tested using a DC input source with series source resistance.
Future testing efforts are necessary to better evaluate the prototype under high power conditions, and with
a real or simulated PV input source.
93
CHAPTER 8
CONCLUSION AND FUTURE WORK
This thesis presented an analysis, design, and implementation of a prototype 4P FIBC for PV
power system applications. This converter was chosen as a promising candidate for PV because of its
high voltage gain, improved efficiency, and reduced input ripple when compared against other nonisolated DC-DC boost converter topologies. These advantages have led the FIBC topology to be
demonstrated for fuel cell and electric vehicle applications. These same advantages also make the FIBC
an improved solution for PV power system applications.
A simulation study of eight different, non-isolated DC-DC converts was conducted. Of these, the
FIBC showed the best performance in terms of efficiency, input and output ripple, and switching stress. A
mathematical analysis was also performed to derive the state space equations, steady state, static transfer
function, and transfer function. These were used for developing the dual loop, linear feedback controller.
A bidirectional FIBC was also presented.
In addition to the voltage and current control, this converter also required MPPT capability for
use with PV power systems. MPPT is required due to the non-linear current and voltage relationship of
PV modules. For each set of operating conditions, there is one unique point at which the maximum power
of the PV can be obtained. This point varies with irradiance and temperature, and the MPPT controller is
responsible for dynamically tracking to obtain the optimal output. Two MPPT algorithms, the IC and the
P&O, were compared in simulation, and the IC was implemented for the prototype. For the FIBC, the
total input current is the sum of the four inductor currents minus the output (load) current. Therefore, for
some MPPT methods that require the input current, another current measurement of either the input or
output current must be made.
The dual loop, linear feedback controller was designed using Bode diagram frequency analysis.
Four faster, inner current control loops regulated the current through each inductor. Two independent
voltage control loops, which were slower than the current controllers, regulated the voltage across the two
output capacitors. Controlling the capacitors individually, as opposed to attempting to regulate the total
DC link output voltage, was found to lead to more stable operation, particularly for a PV input
experiencing low irradiance conditions. After developing the analog controllers, they were discretized in
order to be implemented using an embedded microcontroller. The digital PWM used a single counter with
four Output Compare channels operating in the Continuous Pulse method to generate four, independent
PWM outputs that were phase shifted 90o apart from one another. The PI controllers were replaced with
discrete versions using the Tustin integration approximation.
94
Modeling and simulation studies of the complete prototype, with current and voltage controllers
and MPPT algorithms, were conducted. These explored the performance variation between two MPPT
methods, the P&O and IC techniques, using both the analog and discrete controllers. With analog
controls, the P&O and IC techniques had virtually indistinguishable performance. However, when using
the discrete controller, the IC method was observed to converge more quickly and accurately, and without
the steady state oscillation that occurred with the P&O technique. For this reason, the IC method was
chosen for implementation with the hardware prototype.
A hardware prototype of the 4P FIBC was constructed, using a Microchip dsPIC33FJ256GP710A
embedded microcontroller. This prototype used MOSFETs as opposed to IGBTs, due to the loss
calculations and estimated thermal dissipation for the IBGTs. Two small POC systems, which were
conventional boost converters, were constructed and tested in order to better refine the final prototype and
evaluate system performance parameters. This was particularly helpful in designing the snubber for the
MOSFET devices. In addition to the power stage, gate drivers, analog signal condition, overcurrent
protection, and overvoltage protection circuits were also designed. All of these circuits were implemented
on a single 10”x16” (25.4 x 40.64 cm), two layer PCB with 2 oz/ft 2 copper weight and 1/8” FR4
dielectric. The inductors were mounted directly to the chassis, and the microcontroller was housed
separately and run from the Microchip Explorer 16 Development Board.
The final prototype was built using a 16.75” x 23.5” (42.5 x 59.7 cm) rack for a rack mount
enclosure. This rack served as the chassis and held all the buswork, inductors, printed circuit board, heat
sink, terminal blocks, etc. Mounting brackets allowed the Microchip Explorer 16 Development Board,
which held the embedded microcontroller, to be placed above the main PCB, inside a steel electrical
enclosure.
One unique challenge for the 4P FIBC was the multiple common points within the circuit. The
high voltage DC link output of the device is floating with respect to the input source. In addition, the
MOSFETs for the floating phases of the converter have their source floating with respect to the output
and to each other. In all, five common points existed within the circuit: the input neutral, the output
neutral, the source of MOSFET Q3, the source of MOSFET Q4, and the control/signal common, which
was kept isolated from all others to prevent circulating currents. In addition, the chassis was connected to
earth ground, which was kept isolated from all the other commons. A number of isolated power supplies
were required to provide the necessary control voltages with respect to the different common points.
Several issues related to EMI were identified with this prototype. Originally, small, on-board DCDC power supplies were included to provide the various isolated control voltages that were required.
95
However, these were observed to be a major source of EMI. This EMI was so severe that noise transients
triggered the overcurrent protection circuit, disabling the prototype. In order to resolve this, these had to
be replaced with external, linear power supplies. However, the advantages of the DC-DC supplies are
their smaller size, weight, cost, and the fact that no external AC power supply is required. For these
reasons, it is recommended that future prototypes use the isolated DC-DC supplies, but house them
separately and use adequate shielding to prevent EMI from interfering with the control or protection
circuitry.
In addition, EMI was generated by switching transients from the MOSFETs. These transients
were especially noticeable in the outputs of the on board current and voltage sensors. Under the low
power conditions at which the hardware testing took place, these did not appear to noticeably impact
system performance. However, at higher power, these transients could begin to significantly interfere with
either the analog feedback signals or the digital switching pulses. Future work should be focused on
minimizing these transients. Soft-switching of the MOSFETs would be beneficial. If necessary, the
control circuitry could be separated from the power stage entirely, and run on a separate, shielded PCB.
The microcontroller code was written primarily in C, with some assembly language. All
calculations were performed using 16-bit signed, fixed point integers. Fixed point integer arithmetic was
beneficial for computation time. The sample/control loops for each inductor current took approximately
5.6 µs, and were run once per cycle. Sampling was synchronized to occur at the center of either the on or
off switching pulse to extract the average value. The voltage sample and control loop was executed in a
separate ISR that occurred every ten switching cycles (512 µs) and took about 38.8 µs; the MPPT
algorithm was executed in another ISR with a 20 cycle (1,024 µs) period and required 39 µs. The nested
interrupt capability of the dsPIC microcontroller ensured that the slower, outer controls (voltage and
MPPT) did not interfere with the inner current control loops.
The total cost for all parts, components, and materials for the prototype was approximately
$2,357. It is estimated that with volume manufacturing, the material cost could be reduced to about
$1,326 (roughly 44%). Assuming that the material cost represents 60% of the total manufacturing cost,
the total cost for commercial production of this device is estimated to be about $2,210.
Experimental testing of the hardware prototype was conducted to verify correct operation of all
circuits and control functions. The current, voltage, and MPPT controls were tested all evaluated. The
current controllers were demonstrated under steady state and step response conditions. Comparing the
input current against the individual inductor currents demonstrated that the interleaving of the FIBC was
able to significantly reduce the input current ripple to below 10%. The voltage control was evaluated with
96
a step change in load. It was able to maintain the desired output voltage with acceptable overshoot and
settling time. Finally, two different MPPT algorithms, the CV and IC were demonstrated. These were
both able to converge at or near the maximum power point when tested using a DC input source with
series source resistance.
Future experimental work should focus on evaluating the prototype under rated voltage and
power conditions. EMI issues will have to be closely monitored, and mitigations may be required if EMI
begins to degrade system performance with increased voltage and current. The performance of the MPPT
algorithms must be evaluated using a real or simulated PV input. The FIBC must be demonstrated as part
of a complete PV power system. This will involve using the 4P FIBC as an initial stage to raise the PV
array voltage up to the requisite value for an inverter, and using the high voltage DC link output of the 4P
FIBC as an input for an inverter. Finally, the development of a bidirectional hardware prototype, suitable
for battery system applications, is necessary.
97
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99
APPENDIX A
INDUCTOR TEST REPORT
100
101
APPENDIX B
COMPONENT LIST
102
Table B-1 Component List.
Subcircuit
Item
Value/ Type
C1
1,000 µF
C2
1,000 µF
C3
330 µF
C4
1,500 pF
C5
1,500 pF
C6
1,500 pF
C7
1,500 pF
C76
5 µF
C77
5 µF
CT1
CT
CT2
I or P
Rating
V
Rating
Manufacturer
Manuracturer Part #
PANASONIC
ECO-S2EP102DX
PANASONIC
ECO-S2EP102DX
NICHICON
LNT2V331MSEC
CORNELL DUBILIER
715P15256JD3
CORNELL DUBILIER
715P15256JD3
CORNELL DUBILIER
715P15256JD3
CORNELL DUBILIER
KEMET
715P15256JD3
C4BTJBX4500ZAJ
J
C4BTJBX4500ZAJ
J
25 ADC
LEM USA
LAH 25-NP
CT
25 ADC
LEM USA
LAH 25-NP
CT3
CT
25 ADC
LEM USA
LAH 25-NP
CT4
CT
25 ADC
LEM USA
LAH 25-NP
D1
Power diode
50 A
FAIRCHILD
RHRG5060
D2
Power diode
50 A
FAIRCHILD
RHRG5060
D3
Power diode
50 A
FAIRCHILD
RHRG5060
D4
Power diode
FAIRCHILD
RHRG5060
TRANEX BADGER
N/A
TRANEX BADGER
N/A
TRANEX BADGER
N/A
TRANEX BADGER
STMICROELECTRONI
CS
STMICROELECTRONI
CS
STMICROELECTRONI
CS
STMICROELECTRONI
CS
N/A
Main
250
VDC
250
VDC
350
VDC
600
VDC
600
VDC
600
VDC
600
VDC
700
VDC
700
VDC
KEMET
L1
250 µH
L2
250 µH
L3
250 µH
L4
250 µH
50 A
41.1
ADC
41.1
ADC
41.1
ADC
41.1
ADC
Q1
MOSFET
84 ADC
Q2
MOSFET
84 ADC
Q3
MOSFET
84 ADC
Q4
MOSFET
84 ADC
R1
15 Ω
1W
OHMITE
OA150KE
R2
15 Ω
1W
OHMITE
OA150KE
R3
15 Ω
1W
OHMITE
OA150KE
R4
15 Ω
1W
OHMITE
OA150KE
100
VDC
100
VDC
100
VDC
100
VDC
650
VDC
650
VDC
650
VDC
650
VDC
103
STW88N65M5
STW88N65M5
STW88N65M5
STW88N65M5
Subcircuit
Item
Value/ Type
I or P
Rating
R5
15 Ω
R6
15 Ω
R7
V
Rating
Manufacturer
Manuracturer Part #
1W
OHMITE
OA150KE
1W
OHMITE
OA150KE
15 Ω
1W
OHMITE
OA150KE
R8
R87
15 Ω
40 kΩ
1W
6.5 W
OHMITE
VISHAY
OA150KE
CW00540K00JE73
RELA
Y1
--
200
ADC
400
VDC
OMRON
G9EC-1 DC12
50 A
300 V
MOLEX
38280-0112
MICROCHIP
dsPIC33FJ256GP71
0A
LITTELFUSE
P6KE350A
LITTELFUSE
P6KE350A
LITTELFUSE
P6KE350A
LITTELFUSE
P6KE350A
VISHAY
K103K10X7RF5U
H5
TB1
TERMINAL
BLOCK
U1
Microcontroller
Z1
TVS
600 W
Z2
TVS
600 W
Z3
TVS
600 W
Z4
TVS
600 W
350
VDC
350
VDC
350
VDC
350
VDC
Gate Driver – 1 of 4
C8
10 nF
C9
D5
0.47 µF
1N914
0.2 A
50
VDC
50
VDC
100 V
D6
STTH102
1A
200 V
R9
390 Ω
R10
R11
NICHICON
FAIRCHILD
STMICROELECTRONI
CS
UPW1HR47MDD
1N914BTR
1/4 W
STACKPOLE
CF14JT390R
5.6 kΩ
1/4 W
STACKPOLE
CF14JT5K60
4.7 Ω
1/2 W
STACKPOLE
RC12JB4R70
FAIRCHILD
STMICROELECTRONI
CS
MICRO
COMMERCIAL CO
MICRO
COMMERCIAL CO
HCPL2531
U2
Optocoupler
8 mA
U3
Gate Driver
400 mA
Z5
18 V Zener
18 VDC
Z6
18 V Zener
18 VDC
0-30
VDC
17
VDC
STTH102
L6387E
1N5355B-TP
1N5355B-TP
Gate Driver – 2 of 4
50
VDC
50
VDC
VISHAY
K103K10X7RF5U
H5
NICHICON
UPW1HR47MDD
FAIRCHILD
STMICROELECTRONI
CS
1N914BTR
1/4 W
STACKPOLE
CF14JT390R
1/4 W
STACKPOLE
CF14JT5K60
C10
10 nF
C11
0.47 µF
D7
1N914
0.2 A
100 V
D8
STTH102
1A
200 V
R9
390 Ω
R10
5.6 kΩ
104
STTH102
Subcircuit
Item
Value/ Type
I or P
Rating
R11
4.7 Ω
1/2 W
U4
Optocoupler
8 mA
U5
Gate Driver
400 mA
Z7
18 V Zener
18 VDC
Z8
18 V Zener
18 VDC
V
Rating
0-30
VDC
17
VDC
Manufacturer
Manuracturer Part #
STACKPOLE
RC12JB4R70
FAIRCHILD
STMICROELECTRONI
CS
MICRO
COMMERCIAL CO
MICRO
COMMERCIAL CO
HCPL2531
L6387E
1N5355B-TP
1N5355B-TP
Gate Driver – 3 of 4
50
VDC
50
VDC
VISHAY
K103K10X7RF5U
H5
NICHICON
UPW1HR47MDD
FAIRCHILD
STMICROELECTRONI
CS
1N914BTR
1/4 W
STACKPOLE
CF14JT390R
5.6 kΩ
1/4 W
STACKPOLE
CF14JT5K60
4.7 Ω
1/2 W
STACKPOLE
RC12JB4R70
FAIRCHILD
STMICROELECTRONI
CS
MICRO
COMMERCIAL CO
MICRO
COMMERCIAL CO
HCPL2531
C12
10 nF
C13
0.47 µF
D9
1N914
0.2 A
100 V
D10
STTH102
1A
200 V
R9
390 Ω
R10
R11
U6
Optocoupler
8 mA
U7
Gate Driver
400 mA
Z9
18 V Zener
18 VDC
Z10
18 V Zener
18 VDC
0-30
VDC
17
VDC
STTH102
L6387E
1N5355B-TP
1N5355B-TP
Gate Driver – 4 of 4
50
VDC
50
VDC
VISHAY
K103K10X7RF5U
H5
NICHICON
UPW1HR47MDD
FAIRCHILD
STMICROELECTRONI
CS
1N914BTR
1/4 W
STACKPOLE
CF14JT390R
5.6 kΩ
1/4 W
STACKPOLE
CF14JT5K60
4.7 Ω
1/2 W
STACKPOLE
RC12JB4R70
FAIRCHILD
STMICROELECTRONI
CS
MICRO
COMMERCIAL CO
MICRO
COMMERCIAL CO
HCPL2531
C14
10 nF
C15
0.47 µF
D11
1N914
0.2 A
100 V
D12
STTH102
1A
200 V
R9
390 Ω
R10
R11
U8
Optocoupler
8 mA
U9
Gate Driver
400 mA
Z11
18 V Zener
18 VDC
Z12
18 V Zener
18 VDC
0-30
VDC
17
VDC
CT Signal Conditioning – 1 of 4
105
STTH102
L6387E
1N5355B-TP
1N5355B-TP
Subcircuit
I or P
Rating
Item
Value/ Type
C16
82 pF
C17
100 nF
C18
100 nF
P1
10 kΩ
1/2 W
R21
10 kΩ
1/4 W
R22
10 kΩ
1/4 W
R23
4.7 kΩ
1/4 W
R24
100 Ω
1/2 W
U10
QUAD OP AMP
V
Rating
50
VDC
50
VDC
50
VDC
Manufacturer
VISHAY
Manuracturer Part #
K820J15C0GF5TH
5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
BOURNES INC.
3362P-1-103LF
STACKPOLE
TEXAS
INSTRUMENTS
CF12JT100R
VISHAY
VISHAY
TL074CN
CT Signal Conditioning – 2 of 4
50
VDC
50
VDC
50
VDC
C19
82 pF
C20
100 nF
C21
100 nF
P2
10 kΩ
1/2 W
R25
10 kΩ
1/4 W
R26
10 kΩ
1/4 W
R27
4.7 kΩ
1/4 W
R28
100 Ω
1/2 W
U11
QUAD OP AMP
VISHAY
K820J15C0GF5TH
5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
BOURNES INC.
3362P-1-103LF
STACKPOLE
TEXAS
INSTRUMENTS
CF12JT100R
VISHAY
VISHAY
TL074CN
CT Signal Conditioning – 3 of 4
50
VDC
50
VDC
50
VDC
C22
82 pF
C23
100 nF
C24
100 nF
P3
10 kΩ
1/2 W
R29
10 kΩ
1/4 W
R30
10 kΩ
1/4 W
R31
4.7 kΩ
1/4 W
R32
100 Ω
1/2 W
U12
QUAD OP AMP
VISHAY
K820J15C0GF5TH
5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
BOURNES INC.
3362P-1-103LF
STACKPOLE
TEXAS
INSTRUMENTS
CF12JT100R
VISHAY
VISHAY
TL074CN
CT Signal Conditioning – 4 of 4
C25
82 pF
C26
100 nF
50
VDC
50
VDC
C27
100 nF
50
106
VISHAY
K820J15C0GF5TH
5
K104K10X7RF5U
H5
VISHAY
K104K10X7RF5U
VISHAY
Subcircuit
Item
Value/ Type
I or P
Rating
P4
10 kΩ
1/2 W
R33
10 kΩ
1/4 W
R34
10 kΩ
1/4 W
R35
4.7 kΩ
1/4 W
R36
100 Ω
1/2 W
U13
QUAD OP AMP
V
Rating
VDC
Manufacturer
Manuracturer Part #
H5
BOURNES INC.
3362P-1-103LF
STACKPOLE
TEXAS
INSTRUMENTS
CF12JT100R
TL074CN
PT Signal Conditioning – 1 of 4
C28
3,300 pF
C29
100 nF
C30
100 nF
C31
100 nF
P5
10 kΩ
50
VDC
50
VDC
50
VDC
50
VDC
1/2 W
500
VDC
PT1
VISHAY
K332K15X7RF5TL
2
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
BOURNES INC.
3362P-1-103LF
LEM USA
LV 20-P
MFR-25FBF52133R
VISHAY
VISHAY
VISHAY
R37
1 kΩ
1/4 W
R38
1 kΩ
1/4 W
R39
4.7 kΩ
1/4 W
R40
133 Ω +/-1%
1/4 W
YAEGO
R41
6.2 kΩ
2W
U14
QUAD OP AMP
STACKPOLE
TEXAS
INSTRUMENTS
RSF2JT6K20
TL074CN
PT Signal Conditioning – 2 of 4
C32
100 nF
C33
100 nF
C34
100 nF
C35
3,300 pF
P6
10 kΩ
50
VDC
50
VDC
50
VDC
50
VDC
1/2 W
500
VDC
PT2
VISHAY
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K332K15X7RF5TL
2
BOURNES INC.
3362P-1-103LF
LEM USA
LV 20-P
VISHAY
VISHAY
VISHAY
R42
40 kΩ
6.5 W
VISHAY
R43
133 Ω +/-1%
1/4 W
YAEGO
CW00540K00JE73
MFR-25FBF52133R
R44
4.7 kΩ
1/4 W
R45
1 kΩ
1/4 W
R46
1 kΩ
1/4 W
U15
QUAD OP AMP
TEXAS
TL074CN
107
Subcircuit
Item
Value/ Type
I or P
Rating
V
Rating
Manufacturer
INSTRUMENTS
Manuracturer Part #
PT Signal Conditioning – 3 of 4
C36
100 nF
C37
100 nF
C38
100 nF
C39
3,300 pF
P7
10 kΩ
50
VDC
50
VDC
50
VDC
50
VDC
1/2 W
500
VDC
PT3
VISHAY
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K332K15X7RF5TL
2
BOURNES INC.
3362P-1-103LF
LEM USA
LV 20-P
VISHAY
VISHAY
VISHAY
R47
22 kΩ
5W
TE CONNECTIVITY
R48
133 Ω +/-1%
1/4 W
YAEGO
1623782-7
MFR-25FBF52133R
R49
4.7 kΩ
1/4 W
R50
1 kΩ
1/4 W
R51
1 kΩ
1/4 W
U16
QUAD OP AMP
TEXAS
INSTRUMENTS
TL074CN
PT Signal Conditioning – 4 of 4
C40
100 nF
C41
100 nF
C42
100 nF
C43
3,300 pF
P8
10 kΩ
50
VDC
50
VDC
50
VDC
50
VDC
1/2 W
500
VDC
PT4
VISHAY
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K332K15X7RF5TL
2
BOURNES INC.
3362P-1-103LF
LEM USA
LV 20-P
VISHAY
VISHAY
VISHAY
R52
22 kΩ
5W
TE CONNECTIVITY
R53
133 Ω +/-1%
1/4 W
YAEGO
1623782-7
MFR-25FBF52133R
R54
4.7 kΩ
1/4 W
R55
1 kΩ
1/4 W
R56
1 kΩ
1/4 W
U17
QUAD OP AMP
TEXAS
INSTRUMENTS
TL074CN
Overcurrent Protection
Comp 1
C44
10 nF
C45
10 nF
C46
10 µF
50
VDC
50
VDC
50
VDC
108
KEMET
C315C103M5U5C
A
C315C103M5U5C
A
PANASONIC
EEU-FC1H100
KEMET
Subcircuit
Comp 2
Comp 3
Comp 4
Main
Item
Value/ Type
I or P
Rating
P9
10 kΩ
R57
22 Ω
R58
10 kΩ
1/4 W
R59
10 kΩ
1/4 W
C47
10 nF
C48
10 nF
P10
10 kΩ
1/2 W
R60
10 kΩ
1/4 W
R61
10 kΩ
1/4 W
C49
10 nF
C50
10 nF
C51
10 µF
P11
10 kΩ
R62
V
Rating
Manufacturer
Manuracturer Part #
1/2 W
BOURNES INC.
3362P-1-103LF
1/4 W
YAEGO
CFR-25JB-52-22R
50
VDC
50
VDC
50
VDC
50
VDC
50
VDC
KEMET
C315C103M5U5C
A
C315C103M5U5C
A
BOURNES INC.
3362P-1-103LF
KEMET
KEMET
C315C103M5U5C
A
C315C103M5U5C
A
PANASONIC
EEU-FC1H100
1/2 W
BOURNES INC.
3362P-1-103LF
22 Ω
1/4 W
YAEGO
CFR-25JB-52-22R
R63
10 kΩ
1/4 W
R64
10 kΩ
1/4 W
C52
10 nF
C53
10 nF
P12
10 kΩ
1/2 W
R65
10 kΩ
1/4 W
R66
22 Ω
1/4 W
C54
10 µF
C55
100 nF
C56
1 µF
C57
100 nF
C58
100 nF
C59
100 nF
D13
LED
13 mA
R67
22 Ω
1/4 W
R68
4.7 kΩ
1/4 W
R69
10 kΩ
1/4 W
R70
390 Ω
1/4 W
R71
560 Ω
1/4 W
50
VDC
50
VDC
50
VDC
50
VDC
50
VDC
50
VDC
50
VDC
50
VDC
5
VDC
109
KEMET
KEMET
C315C103M5U5C
A
C315C103M5U5C
A
BOURNES INC.
3362P-1-103LF
PANASONIC
VISHAY
EEU-FC1H100
K104K10X7RF5U
H5
K105K20X7RF5U
H5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
K104K10X7RF5U
H5
KINGBRIGHT
WP710A10ID5V
YAEGO
CFR-25JB-52-22R
KEMET
VISHAY
VISHAY
VISHAY
VISHAY
Subcircuit
Item
Value/ Type
I or P
Rating
R72
RELA
Y2
1 kΩ
1/4 W
SW1
SW2
U18
U19
U20
U21
U22
U23
U24
2 ADC
PUSH BUTTON
SWITCH
EMERGENCY
STOP
DUAL
COMPARATOR
DUAL
COMPARATOR
DUAL
COMPARATOR
HEX LOGIC
INVERTER
2A
10 ADC
V
Rating
Manufacturer
Manuracturer Part #
30
VDC
PANASONIC
DS2E-SL2-DC5V
JUDCO
40-2531-01
OMRON
A22E-M-01
FAIRCHILD
LM393N
FAIRCHILD
LM393N
FAIRCHILD
TEXAS
INSTRUMENTS
TEXAS
INSTRUMENTS
TEXAS
INSTRUMENTS
LM393N
TOSHIBA
ULN2803
PANASONIC
VISHAY
EEU-FC1H100
K104K10X7RF5U
H5
NICHICON
UPW1HR47MDD
CORNELL DUBILIER
715P15256JD3
KINGBRIGHT
STMICROELECTRONI
CS
WP710A10ID5V
14 V
24
VDC
D FLIP FLOP
QUAD NAND
GATE
RELAY
DRIVER
SN74HC14NE4
SN74HC74
SN74ACH00N
Overvoltage Protection
C60
10 µF
C61
100 nF
C62
0.47 µF
C63
1,500 pF
D14
LED
13 mA
50
VDC
50
VDC
50
VDC
600
VDC
5
VDC
D15
STTH102
1A
200 V
P13
220 kΩ
3W
VISHAY
PE30L0FL224KAB
P14
500 Ω
1/4 W
BOURNES INC.
3362P-1-501LF
R73
1 kΩ
1/4 W
R74
22 Ω
1/4 W
R75
10 kΩ
1/4 W
R76
R77
820 Ω
4.7 Ω
1/4 W
1/2 W
STACKPOLE
RC12JB4R70
R78
3.3 kΩ
1/4 W
R79
47 Ω
1/4 W
R80
15 Ω
1W
OHMITE
OA150KE
R81
15 Ω
1W
OHMITE
OA150KE
R84
2 kΩ
100 W
RIEDON
ON
SEMICONDUCTOR
PF2472-2KF1
Q5
BJT
600 mA
40
VDC
110
STTH102
P2N2222AG
Subcircuit
Item
Value/ Type
Q6
IGBT
DUAL
COMPARATOR
HEX LOGIC
INVERTER
U25
U26
I or P
Rating
50 ADC
U27
Gate Driver
200/420
mA
Z13
18 V Zener
18 VDC
Z14
18 V Zener
18 VDC
V
Rating
1200
VDC
10-20
VDC
Manufacturer
INTERNATIONAL
RECTIFIER
Manuracturer Part #
FAIRCHILD
TEXAS
INSTRUMENTS
INTERNATIONAL
RECTIFIER
MICRO
COMMERCIAL CO
MICRO
COMMERCIAL CO
LM393N
PANASONIC
EEU-FC1E101S
PANASONIC
EEU-FC1E101S
PANASONIC
EEU-FC1E101S
PANASONIC
EEU-FC1E101S
PANASONIC
EEU-FC1E101S
PANASONIC
EEU-FC1E101S
PANASONIC
25SEP10M+TSS
PANASONIC
EEU-FC1E101S
PANASONIC
25SEP10M+TSS
PANASONIC
EEU-FC1E101S
PANASONIC
EEU-FC1E101S
NICHICON
UHE2A101MPD
KINGBRIGHT
WP710A10ID5V
KINGBRIGHT
WP710A10ID5V
LITTELFUSE
EMERSON NETWORK
POWER
0312005.HXP
GE CRITICAL POWER
SHHD001A3B41Z
CUI INC.
EMERSON NETWORK
POWER
EMERSON NETWORK
POWER
PYB10-Q48-D12
IRG7PH35UDPBF
SN74HC14NE4
IR2117PBF
1N5355B-TP
1N5355B-TP
On-board Power Supplies
C64
100 µF
C65
100 µF
C66
100 µF
C67
100 µF
C68
100 µF
C69
100 µF
10 µF, ESR =
0.06 Ω
C70
C71
C72
100 µF
10 µF, ESR =
0.06 Ω
C73
100 µF
C74
100 µF
C75
100 µF
D16
LED
13 mA
D17
LED
13 mA
F1
Fast acting fuse
12 V Isolated
DC-DC
12 V Isolated
DC-DC
+/-12 V Isolated
DC-DC
12 V Isolated
DC-DC
12 V Isolated
DC-DC
5A
PS1
PS2
PS3
PS4
PS5
500 mA
1.3 ADC
416
mA/Ch
500 mA
500 mA
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
25
VDC
100
VDC
5
VDC
5
VDC
250V
18-75
VDC
18-75
VDC
18-75
VDC
18-75
VDC
18-75
VDC
111
ASA00B36-L
ASA00B36-L
ASA00B36-L
Subcircuit
Item
I or P
Rating
PS6
Value/ Type
12 V Isolated
DC-DC
R82
820 Ω
1/4 W
R83
820 Ω
5 V Linear
regulator
5 V Linear
regulator
1/4 W
Z15
Z16
500 mA
150 mA
150 mA
V
Rating
18-75
VDC
6-26
VDC
6-26
VDC
112
Manufacturer
EMERSON NETWORK
POWER
Manuracturer Part #
FAIRCHILD
TL750L05CLPR
FAIRCHILD
TL750L05CLPR
ASA00B36-L
APPENDIX C
BILL OF MATERIALS LIST
113
Table C-1 Bill of Materials.
Item
Qty
Component Number
Manufacturer
Manuracturer Part #
$/each
Subtotal
1
2
C1,C2
PANASONIC
ECO-S2EP102DX
5.02
10.04
2
1
C3
LNT2V331MSEC
15.47
15.47
3
5
715P15256JD3
1.65
8.25
4
12
K103K10X7RF5U
H5
0.202
2.424
5
6
C4,C5,C6,C7,C63
C8,C10,C12,C14,C44,
C45,C47,C48,C49,C50,
C52,C53
C9,C11,C13,C15,C62,C
82
NICHICON
CORNELL
DUBILIER
0.35
2.10
6
4
0.34
1.36
7
25
0.37
9.25
8
0.31
1.24
0.44
1.76
0.94
0.94
VISHAY
NICHICON
UPW1HR47MDD
K820J15C0GF5TH
5
C16,C19,C22,C25
C17,C18,C20,C21,C23,
C24,C26,C27,C29,C30,
C31,C32,C33,C34,C36,
C37,C38,C40,C41,C42,
C55,C57,C58,C59,C60,
C61
VISHAY
4
C28,C35,C39,C43
VISHAY
9
4
C46,C51,C54,C60
PANASONIC
10
1
C56
VISHAY
EEU-FC1H100
K105K20X7RF5U
H5
11
9
C64,C65,C66,C67,C68,
C69,C71,C73,C74
PANASONIC
EEU-FC1E101S
0.34
3.06
12
2
C70,C72
PANASONIC
25SEP10M+TSS
1.56
3.12
13
1
C75
NICHICON
0.56
0.56
14
2
C76,C77
KEMET
11
22
15
1
C83
VISHAY
UHE2A101MPD
C4BTJBX4500ZAJ
J
K224K20X7RF5TH
5
16
4
CT1,CT2,CT3,CT4
LEM USA
LAH 25-NP
22.88
91.52
17
4
D1,D2,D3,D4
FAIRCHILD
RHRG5060
4.59
18.36
18
4
D5,D7,D9,D11
1N914BTR
STTH102
0.064
0.256
19
5
D6,D8,D10,D12,D15
FAIRCHILD
STMICROELECTRO
NICS
0.51
2.55
20
4
D13,D14,D16,D17
KINGBRIGHT CO
WP710A10ID5V
0.33
1.32
21
1
F1
LITTELFUSE
0312005.HXP
0.38
0.38
22
2
J1
FCI
10090770-S154ALF
1.02
2.04
23
1
J1
ASSMANN WSW
AK532-2-R
6.08
6.08
24
2
J4,J5
MOLEX
399100102
6.92
13.84
25
2
J6,J7,J8
TE CONNECTIVITY
282858-2
1.76
3.52
TRANEX BADGER
N/A
115.78
463.12
MAGNETICS INC
00K8044E026
4.36
17.44
MAGNETICS INC
00B802001
5.54
22.16
26
4
L1,L2,L3,L4
K104K10X7RF5U
H5
K332K15X7RF5TL
2
VISHAY
114
Item
Qty
Component Number
P1,P2,P3,P4,P5,P6,P7,P8
, P9,P10,
P11,P12
Manufacturer
Manuracturer Part #
$/each
Subtotal
27
12
BOURNES, INC.
3362P-1-103LF
0.81
9.72
28
1
P13
VISHAY
PE30L0FL224KAB
23.9
23.9
29
1
P14
3362P-1-501LF
0.98
0.98
30
4
PS1,PS4,PS5,PS6
BOURNES, INC.
EMERSON
NETWORK PWR
ASA00B36-L
18.31
73.24
31
1
PS2
GE CRITICAL PWR
SHHD001A3B41Z
18.91
18.91
32
1
PS3
CUI INC.
PYB10-Q48-D12
25.87
25.87
33
4
PT1,PT2,PT3,PT4
LV 20-P
42.35
169.4
34
4
Q1,Q2,Q3,Q4
STW88N65M5
20.9
83.6
35
1
Q5
P2N2222AG
0.38
0.38
36
1
IRG7PH35UDPBF
9.18
9.18
37
10
Q6
R1,R2,R3,R4,R5,R6,R7,
R8,R80,R81
LEM
STMICROELECTRO
NICS
ON
SEMICONDUCTOR
INTERNATIONAL
RECTIFIER
OHMITE
OA150KE
2.62
26.2
38
5
R9,R12,R15,R18,R70
STACKPOLE
CF14JT390R
0.08
0.4
39
4
R10,R13,R16,R19
STACKPOLE
CF14JT5K60
0.08
0.32
40
4
STACKPOLE
RC12JB4R70
0.56
2.24
41
17
R11,R14,R17,R20,
R21,R22,R25,R26,R29,
R30,R33,R34,R58,R59,
R60,R61,R63,R64,R65,
R69, R75
TE CONNECTIVITY
1623927-4
0.0512
0.87
42
4
STACKPOLE
CF12JT100R
0.14
0.56
43
9
R24,R28,32,R36
R23,R27,R31,R35,R39,
R44,R49,R54, R68
STACKPOLE
0.08
0.72
44
4
R40,R43,R48,R53
YAEGO
CF14JT4K70
MFR-25FBF52133R
0.1
0.4
45
1
R41
STACKPOLE
RSF2JT6K20
0.44
0.44
46
2
R42,R87
VISHAY
CW00540K00JE73
1.19
2.38
47
2
R47,R52
TE CONNECTIVITY
1623782-7
0.57
1.14
48
4
R57,R66,R67,R74
YAEGO
CFR-25JB-52-22R
0.1
0.4
49
1
R71
YAEGO
CFR-25JB-52-560R
0.1
0.1
50
10
R37,R38,R45,R46,R50,
R51,R55,R56,R72,R73
STACKPOLE
CF14JT1K00
0.08
0.8
51
3
R74,R82,R83
STACKPOLE
CF14JT820R
0.08
0.24
52
2
R77,R79
STACKPOLE
CF14JT47R0
0.08
0.16
53
1
R78
STACKPOLE
CF14JT3K30
0.08
0.08
54
1
R84
Riedon
PF2472-2KF1
7.22
7.22
55
1
RELAY 1
OMRON
G9EC-1 DC12
237.15
237.15
56
1
RELAY 2
PANASONIC
DS2E-SL2-DC5V
6.37
6.37
57
1
SW1
JUDCO
40-2531-01
2.67
2.67
58
1
SW2
OMRON
A22E-M-01
27.3
27.3
115
Item
Qty
Component Number
Manufacturer
Manuracturer Part #
$/each
Subtotal
38280-0112
19.64
19.64
59
1
TB1
MOLEX
60
1
U1
MICROCHIP
DM240001
97.5
97.5
61
4
U2,U4,U6, U8
HCPL2531
2.21
8.84
62
4
L6387E
2.07
8.28
63
8
U3,U5,U7,U9
U10,U11,U12,U13,U14,
U15,U16,U17
FAIRCHILD
STMICROELECTRO
NICS
TEXAS
INSTRUMENTS
TL074CN
0.62
4.96
64
3
U18,U19,U24
LM393N
0.41
1.23
65
2
U20,U26
SN74HC14NE4
0.52
1.04
66
1
U21
SN74HC32N
0.36
0.36
67
1
U22
SN74HC74
0.36
0.36
68
1
U23
FAIRCHILD
TEXAS
INSTRUMENTS
TEXAS
INSTRUMENTS
TEXAS
INSTRUMENTS
TEXAS
INSTRUMENTS
SN74ACH00N
0.36
0.36
69
1
U24
ULN2803
2.33
2.33
70
1
U27
TOSHIBA
INTERNATIONAL
RECTIFIER
IR2117PBF
3.03
3.03
71
4
Z1,Z2,Z3,Z4
LITTELFUSE
P6KE350A
0.61
2.44
1N5355B-TP
Z5,Z6,Z7,Z8,Z9,
Z10,Z11,Z12,Z13,Z14
MICRO
COMMERCIAL
CO
0.52
5.2
TL750L05CLPR
0.7
1.4
N/A
430.1
430.1
RA7031-23
94.68
94.68
72
10
73
2
Z15,Z16
74
1
75
1
FAIRCHILD
ADVANCED
CIRCUITS
RACKMOUNTMAR
T
76
1
MOLEX
38280-0112
19.64
19.64
77
11
TE CONNECTIVITY
1-390261-2
0.181
1.991
78
13
1-390261-3
0.22
2.86
79
1
TE CONNECTIVITY
ON SHORE
TECHNOLOGY
0.2
0.2
80
3
MILL-MAX
ED18DT
917-43-103-41005000
1.89
5.67
81
1
05200101Z
1.22
1.22
82
55
LITTELFUSE
KEYSTONE
ELECTRONICS
5012
0.2252
12.386
83
1
ERITECH
55
55
84
2
HEAT SINK USA
EGBA14212NN
10.080" Wide
Extruded Aluminum
Heatsink
32.76
65.52
85
4
SOUTHWIRE
0.322
1.288
86
6
SOUTHWIRE
0.116
0.696
87
1
0.076
0.076
88
8
SOUTHWIRE
HARBOUR
INDUSTRIES
M22759/11-22-0
0.35
2.8
89
3.4
GRAINGER
2EYN8
1.42
4.7586
116
Item
90
Qty
2.4
Component Number
Manufacturer
Manuracturer Part #
$/each
Subtotal
GRAINGER
1NZD4
5.92
14.05208
BURNDY
YA8CLBOX
1.65
13.2
1.175
18.8
91
8
92
16
93
8
FASTENAL
1128854
0.0726
0.5808
94
24
FASTENAL
76344
0.1115
2.676
95
16
FASTENAL
1133070
0.0304
0.4864
96
8
FASTENAL
1133610
0.0172
0.1376
97
12
FASTENAL
1128879
0.0249
0.2988
98
4
FASTENAL
1128930
0.1288
0.5152
HILLMAN GROUP
99
32
FASTENAL
1136024
0.0308
0.9856
100
14
FASTENAL
33071
0.0303
0.4242
101
14
FASTENAL
0177556
0.1087
1.5218
102
24
FASTENAL
1129162
0.054
1.296
103
6
FASTENAL
76357
0.141
0.846
104
6
FASTENAL
1133618
0.0154
0.0924
TOTAL
$2,367.09
117