Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
Enpirion EN2390QI DC-DC Converter
w/Integrated Inductor Evaluation Board
Introduction
Thank you for choosing Altera Enpirion power products!
This evaluation board user guide applies to the EN2390 devices mounted on PCB’s with
the part number 06907 Rev A. and two extra components on the backside. In addition to
this document, you will also need the latest device datasheet.
•
The EN2390QI features integrated inductor, power MOSFETS, controller, a bulk
of the compensation network, and protection circuitry against system faults. This
level of integration delivers a substantial reduction in footprint and parts count
over competing solutions. The evaluation board is optimized for engineering ease
of testing through programming options, clip leads, test points etc.
•
The EN2390QI features a customer programmable output voltage by means of a
resistor divider. The resistor divider allows the user to set the output voltage to
any value within the range 0.75V to 3.3V. The evaluation board, as shipped is
populated with a 4 resistor divider option. The upper resistor is fixed and has a
phase lead capacitor in parallel. One of the 4 lower resistors is selected with the
jumper option for different output voltages. To change VOUT , retain the upper
resistor and capacitor and change only the lower resistor.
•
The input and output capacitors are X5R or X7R multi-layer ceramic chip
capacitors. The Soft-start capacitor is a small value X7R MLCC. Pads are
available to have multiple input and output capacitors. This allows for evaluation
of performance over a wide range of input/output capacitor combinations.
•
Clip-on terminals are provided for ENA and POK. Banana jacks are provided for
12VIN, AVIN, and VOUT terminals. Several signal and GND clip-on test points are
also provided to measure VIN, VOUT , and GND nodes.
•
A jumper is provided for controlling the Enable signal. Enable may also be
controlled using an external switching source by removing the jumper and
applying the enable signal to the ENA clip-on terminal.
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Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
•
Foot print is also provided for an SMA connector to S_IN input. A switching input
to this pin allows the device clock to be phase locked to an external signal. This
external clock synchronization allows for moving any offending beat frequency to
be moved out-of-band. A swept frequency applied to this pin results in spread
spectrum operation and reduces the peaks in the noise spectrum of emitted EMI.
•
A two pin header footprint is provided for the S_OUT pin. This signal can be used
to synchronize another EN2390 to the switching frequency coming out of the
S_OUT pin.
•
The board comes with input decoupling and PVIN (12VIN) reverse polarity
protection to guard the device against common setup mishaps. Please note there
is no reverse polarity protection on AVIN input.
Quick Start Guide
STEP 1: Set the ENA jumper J3 to the Disable Position, as shown in Figure 1.
Figure 1: Shows the Enable jumper in the DISABLE position.
STEP 2: With power off, connect the 12V nominal Power Supply to the input power
connectors, 12VIN (J7) and GND (J11) as indicated in Figure 4.
CAUTION: Be mindful of the polarity. Even though the evaluation board comes
with reverse polarity protection diodes, it may not protect the device under all
conditions.
STEP 3: Make sure the two-in header J1 is properly populated depending on how you
want to power AVIN. If you want to use the device in a single input supply mode, and
use the on-chip AVINO pin, then populate J1 with a shorting jumper. If you want to
supply your own external AVIN, then remove the jumper from J1, and connect a 3.3V
nominal power supply to the AVIN (J9) and GND (J11).
NOTE: When using the external AVIN mode with long wires coming to the board,
it may be necessary to populate an 0805 tantalum capacitor in the C16 position.
This capacitor should not be on the board when using the single-supply mode.
CAUTION: be mindful of the AVIN input polarity. There is no reverse polarity
protection on this input.
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Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
CAUTION: Do not apply an external AVIN to the device with the J1 jumper
populated. Doing so will damage the device.
STEP 4: Connect the load to the output connectors VOUT (J6) and GND (J10), as
indicated in Figure 4.
STEP 5: Select the output voltage setting jumper. Figure 2 shows what output voltages
are achieved by selecting each jumper position. Note that depending on the tolerance of
the resistors populated on the board, each output voltage setting may have a larger
tolerance than just the VFB pin as specified in the datasheet. Please see Figure 5 and
the Bill of Materials section.
Figure 2: Output Voltage selection jumpers J5. Nominal jumper position voltages from left to
right are: 3.31V, 1.8V, 1.2V and 1.0V. Jumper shown selects 1.20V output Do not
change jumper positions while the board is powered.
Please note: The loop compensation circuit for this version of evaluation board
has been chosen for a wide range of PVIN and VOUT values using output
capacitors for best performance. In order to optimize the loop for any specific
PVIN/VOUT operating point, please see the compensation table in the datasheet.
See Figures 4 and 5.
STEP 6: Apply AVIN (either through AVINO output or through an external voltage), and
12VIN to the device. Please note the allowable slew rate range on PVIN as specified
in the datasheet. Next, move the ENA jumper to the enabled position. The EN2390QI
is now powered up. Various measurements such as efficiency, line and load regulation,
input / output ripple, load transient, drop-out voltage measurements may be conducted
at this point. The under voltage lock out thresholds, and temperature coefficient of the
output voltage may also be measured in this configuration.
Alternatively, you can leave the ENA jumper in the enabled position, and turn on the
device using the input voltage PVIN. Please note the allowable slew rate range on
PVIN as specified in the datasheet. Please review the Power Up Sequence section in
the datasheet before turning the unit on using PVIN.
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EN2390QI PowerSoC
CAUTION: Please refer to the datasheet for the maximum voltages on the 12V
(PVIN) and AVIN inputs. THIS DEVICE CANNOT BE HOT-PLUGGED INTO A 12V
RAIL.
STEP 6A: Power Up/Down Behavior – Remove ENA jumper and connect a pulse
generator (output disabled) signal to the clip-on test point below ENA and Ground. Set
the pulse amplitude to swing from 0 to 2.5 volts. Set the pulse period to 10msec. and
duty cycle to 50%. Hook up oscilloscope probes to ENA, SS, POK and VOUT with clean
ground returns. Apply power to evaluation board. Enable pulse generator output.
Observe the SS capacitor and VOUT voltage ramps as ENA goes high and again as
ENA goes low. The device when powered down ramps down the output voltage in a
controlled manner before fully shutting down. The output voltage level when POK is
asserted /de-asserted as the device is powered up / down may be observed as well as
the clean output voltage ramp and POK signals.
STEP 7: External Clock Synchronization / Spread Spectrum Modes: In order to
activate this mode, it may be necessary to a solder a SMA connector at J4. Alternately
the input clock signal leads may be directly soldered to the through holes of J4 as
shown below.
GND
Ext. Clock
Figure 3: SMA Connector for External Clock Input
Power down the device. Move ENA into disable position. Connect the clock signal as
just indicated. The clock signal should be clean and have a frequency in the range of
the nominal frequency ±10%; amplitude 0 to 2.5 volts with a duty cycle between 20 and
80%. With S_IN signal disabled, power up the device and move ENA jumper to Enabled
position. The device is now powered up and outputting the desired voltage. The device
is switching at its free running frequency. The switching waveform may be observed
between test points SW and GND. Now enabling the S_IN signal will automatically
phase lock the internal switching frequency to the externally applied frequency as long
as the external clock parameters are within the specified range. To observe phase-lock
connect oscilloscope probes to the input clock as well as to the SW test point. Phase
lock range can be determined by sweeping the external clock frequency up / down until
the device just goes out of lock at the two extremes of its range.
For spread spectrum operation the input clock frequency may be swept between two
frequencies that are within the lock range. The sweep (jitter) repetition rate should be
limited to 10 kHz. The radiated EMI spectrum may be now measured in various states –
free running, phase locked to a fixed frequency and spread spectrum.
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Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
Before measuring radiated EMI, place a 10uF X7R or X5R capacitor at the input and
output edges of the PCB (C8 and C9 positions), and connect the PVIN power and the
load to the board at or near these capacitors. The added capacitor at the input edge is
for high-frequency decoupling of the input cables. The one added at the output edge is
meant to represent a typical load decoupling capacitor. We recommend doing EMI
testing in single-supply mode only as this will simplify the test setup.
Figure 4: Evaluation Board Top and Assembly Layers.
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Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
Rev is io n
E NA
J3
R17
0805
A V IN
V FB
0805
E A IN
E NA B LE
R1
R2
C17
TP 1
E NA
TP 2 7
A GN D
C1
0805
Date
A pp rov ed
3/26/2012
CJR
Updated pin names for pins 61, 63, and 68.
7/10/2012
AG
R16
0402
0805
Des cription
Preliminary Release
1
2
3
FB 1
TP 4
12 V IN
P OK
TP 3 4
NC61
0402
V OUT
PGND
C12
J1 1
S OU T
56
S _IN
55
J9
G ND
J4
54
C5
S IN
TP 2 3
TP 2 8
A VI N
5 .5 V MA X
53
0603
C6
0402
TP 2 5
51
J1
1
2
TP 2 6
50
J6
V OUT
R11
49
V OU T
C16
C9
J1 0
0805
52
TP 2
G ND
A VI NO
48
TP 2 1
C23
TP 2 2
0603
47
46
45
44
P ro vi si o n fo r I mp le m en ti ng
A da pt iv e V ol ta g e Sc a li ng
12 V IN
43
42
41
TP 3 0
R18
40
R13
39
R12
TP 3 1
V FB
C4
R14
V R1
38
PGND
PGND
37
36
PGND
PGND
35
PGND
NC(SW)32
P V IN
C8
0805
57
POK
58
60
59
AVIN
ENABLE
M/S
AGND
62
VFB
EAIN
61
34
33
32
NC18
NC(SW)31
P V IN
NC30
P V IN
NC17
NC29
P V IN
NC16
VOUT
NC15
1 2V IN
C14
0805
TP10
VFB
0805
C2
63
65
64
SS
RCLX
FQADJ
66
67
NC67
69
70
68
CGND
NC(SW)69
NC(SW)70
72
73
71
NC(SW)71
NC72
74
P V IN
31
R5
NC73
NC14
30
R8
0805
NC74
P V IN
29
R7
0805
NC75
P V IN
NC13
19
R6
0805
75
NC12
V FB
0805
P V IN
P V IN
VOUT
18
NC10
27
0805
17
P V IN
NC11
VOUT
16
P V IN
E N2 3 9 0
VOUT
R4
NC9
26
0805
15
A V INO
U1
NC8
25
0805
14
R3
NC7
VOUT
13
PG
24
12
C7
NC6
VOUT
10
11
B TMP
23
9
NC5
VOUT
8
S _IN
+
S 2A
TP 9
S _OUT
V DDB
VOUT
7
0402
TP 5
D1
1
2
TP 2 4
NC4
VOUT
NC61
12 V IN J7
S _OUT
B GND
22
6
R20
A V IN
C19
NC3
21
5
NC76
76
4
0402
NC2
NC19
3
NC1
20
2
TP 3
R15
0402
SS
1
R19
TP29
0805
SW
NR2
08 05
CGND
CGND
TP 7
F AD J
28
R10
E NA
TP 3 3
TP 8
EAIN
TP 6
NR1
Th ru- hole
0603
P OK
C3
TP 3 2
8
6
4
2
R9
J5
C13
TP 1 4 TP 1 5
C10
TP 1 3
2
1
Short across R9
TP 1 1
when all other
routing completed
2
1
7
5
3
1
0805
TP 1 2
TP 1 6
V OU T
P GN D P GN D
C18
V IN
C15
TP 1 7
TP 1 8
C21
C3,10,18,21 are 1206
S CH
P CB
06 9 06
06 9 07
C20
C11
2
1
2
1
C11, 12,13,15,20 are
combination 1206/0805
TP 2 0
TP 1 9
Figure 5: EN2390 Evaluation Board Schematic (NR1 & NR2 are additional components on the back side)
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EN2390QI PowerSoC
Test Recommendations
Recommendations
To guarantee measurement accuracy, the following precautions should be
observed:
1. Make all input and output voltage measurements at the board using
the test points provided (TP13 to TP16). This will eliminate voltage
drop across the line and load cables that can produce false readings.
2. Measure input and output current with series ammeters or accurate
shunt resistors. This is especially important when measuring efficiency.
3. Use a low-loop-inductance scope probe tip similar to one shown below
to measure switching signals and input / output ripple to avoid noise
coupling into the probe ground lead. Input ripple, output ripple, and
load transient deviation are best measured near the respective input /
output capacitors. For more accurate ripple measurement, please see
Enpirion App Note regarding this subject.
4. The board includes a pull-up resistor for the POK signal and ready to
monitor the power OK status at clip lead marked POK.
5. This product has built-in short-circuit protection. If protection against an
overload condition is required, an appropriate external solution needs
to be used. Please refer to the Enpirion application note for further
details on this subject.
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Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
Bill of Materials
Designator
Qty
C2
C3, C10
C5
C6
C7
C12
C13, C15
C14
C19, C23
C1, C4, C8, C9,
C11, C16-C18, C20,
C21, FB1, J4, R2,
R9, R12-R15, R18,
R20, VR1
D1
FB1
J1
J3
J5
J6, J7, J9-J11
R1
R3, R7
R4
R5
R6
R8
R10
R11
R16
R17
R19
TP1, TP2, TP4,
TP13-TP16,
TP21,TP22,
TP28,TP32
TP30, TP31
U1
NR1
NR2
1
2
1
1
1
1
2
1
2
Description
CAP, 47000PF 0805 X7R 10% 50V CERAMIC
CAP, 22UF 1206 X5R 10% 25V CERAMIC
CAP CER 0.22UF 16V X5R 0402
CAP, 47000PF 0402 X7R 10% 25V CERAMIC
CAP, 33PF 0805 NP0 5% 50V CERAMIC
CAP CER 100UF 6.3V X5R 1206
CAP CER 47UF 10V X5R 1206
CAP, SMT ELECTROLYTIC, 150UF, 25V
CAP, 1.0UF 0402 X5R 10% 10V CERAMIC
NOT USED
21
1
1
1
1
1
5
1
2
1
1
1
1
1
1
1
1
1
11
2
1
1
1
S2A DIODE, Micro Commercial S2A-TP
SMT FERRITE BEAD 4A 0805, Wurth Electronik 742792012
CONNECTOR HEADER, 2 POSITION, Samtec TSW-102-07-T-S
CONNECTOR HEADER, 3 POSITION, Samtec TSW-103-07-T-S
CONNECTOR HEADER, 8 POSITION Dual, Samtec TSW-104-24-T-D
BANANA JACK, KEYSTONE 575-4
RES 100K OHM 1/16W 1% 0402 SMD
RES 200K OHM 1/8W 0.1% 0805 SMD
RES ZERO OHM 1/8W 5% 0805 SMD
RES 44.2K OHM 1/8W 1% 0805 SMD
RES 301K OHM 1/8W 0.1% 0805 SMD
RES 100K OHM 1/8W 0.1% 0805 SMD
RES 3.01K OHM 1/8W 1% 0805 SMD
RES 4.75K OHM 1/10W 1% 0402 SMD
RES 100K OHM 1/8W 1% 0805 SMD
RES 33.2K OHM 1/8W 1% 0805 SMD
RES ZERO OHM 1/10W 5% 0402 SMD
TEST POINT SURFACE MOUNT, KEYSTONE 5016
TEST POINT SURFACE MOUNT, KEYSTONE 5015
EN2390QI QFN 9A
RES 10.0 OHM 1/4W 1% AXIAL
RES 2.26K OHM 1/4W 1% 0805 SMD
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Enpirion® Power Evaluation Board User Guide
EN2390QI PowerSoC
Validation Status: EN2390QI – 02
This device is an engineering sample and may not meet one or more of the
specifications itemized in the product datasheet. Validation testing is currently in
progress. Validation tests completed and yet to be done are summarized below.
These devices are being provided for early evaluation and feedback.
VALIDATION COMPLETED TO DATE
The following tests have been completed at room temperature unless otherwise
noted:
• Efficiency and Power Loss
• Load Regulation
• Line Regulation
• Ripple
• Load Transient Response
• Stability/Bode Measurements
• Design Verification Testing (partial)
VALIDATION TO BE COMPLETED
POK Response
Efficiency and Power Loss (-40 to 85 C)
Load Regulation (-40 to 85 C)
Line Regulation (-40 to 85 C)
Vout Temperature coefficient (-40 to 85 C)
Thermal Shutdown
Startup and Shutdown – Enable Toggled
Startup and Shutdown – Supply Power Up
Overcurrent protection and short circuit testing
Design Verification Testing (complete)
Operating temperature range testing
Datasheet Electrical Characteristics compliance
CURRENTLY IDENTIFIED ERRATA
1. Some devices may exhibit higher OCP (over current protection) threshold
than expected.
CORRECTIVE ACTION PLAN
Root cause is identified. Production devices will have this issue resolved.
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EN2390QI PowerSoC
Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY,
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trademarks or service marks are the property of their respective holders as described at
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in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any
time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to
obtain the latest version of device specifications before relying on any published information and before placing orders for
products or services.
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