A Design of a Symmetry-type Floating Impedance
Scaling Circuit and
Improvement of Operation Bandwidth
Fujihiko Matsumoto, Syuzo Nishioka, Tatsuya Fujii, Takayuki Ohyama, Yuta Kobayashi, Takeshi Ohbuchi
Department of Applied Physics, National Defense Academy
1-10-20, Hashirimizu, Yokosuka, 239-8686, Japan
Telephone: +81-046-841-3810 ext 3629 Fax: +81-046-844-5912
Email: matsugen@nda.ac.jp (F. Matsumoto)
I.
v2
v1
Abstract—Low frequency and low power applications are required for biomedical devices. Thus, a large capacitance is needed
for integration of low frequency active filters. To realize a smallsize low frequency active filter, impedance scaling techniques have
been proposed. In this paper, a symmetry-type floating impedance
scaling circuit is proposed. The proposed circuit is composed of
a voltage follower and a current amplifier. The characteristics of
the proposed circuit are confirmed by simulation. The proposed
circuit works as a large capacitor, whose capacitance is multiplied
by 50 times, in the frequency range from 10 Hz to 100 kHz. The
frequency range becomes wider than the conventional circuit.
Simulation results show validities and availability of the proposed
symmetry-type floating scaling capacitor.
i1
1
i2
Z
Ni0
i0
Ni0
I NTRODUCTION
Fig. 1.
Filters are used to process various signals such as visuals,
audios, and communications. Low frequency filter processing
biomedical signals [1] [2] from a few Hz to hundreds Hz
requires a large time constant. In order to implement a large
time constant, a large capacitance and a large resistance are
needed. However, large capacitances and large resistances are
impracticable in integrated circuits, which are required to be
low-powered and downsized.
The large resistance is implemented by a transconductor of low transconductance [3]. The area occupied by a
transconductor is much smaller than that of a resistor with
the same resistance. In contrast, it is difficult to shrink the
area occupied by large capacitances. As a method to realize
a large capacitance, an impedance scaling circuit is proposed
[4]. The impedance scaling is a technique to reduce apparent
impedance using current feedback.
In this paper, a design of a symmetry-type floating
impedance scaling circuit and the improvement method of
operation bandwidth are proposed. The proposed circuit is
applied to a fully differential 1st-order lowpass filter. The fully
differential filter requires introducing of a common-mode rejection circuit. The interaction of the common-mode rejection
circuit and the proposed floating impedance scaling circuit
is confirmed by simulation. The common-mode impedance
characteristics of the proposed impedance scaling circuit are
verified by small-signal analysis. The effectiveness of the
application to the lowpass filter of the proposed circuit is
confirmed by simulation.
II.
Block Diagram of the Conventional Floating Scaling Circuit
P RINCIPLE OF C ONVENTIONAL F LOATING I MPEDANCE
S CALING C IRCUIT
Fig.1 shows the block diagram of the conventional floating
scaling circuit [5]. This circuit is a composed of Differential
Unity gain Amplifier (DUA) and a differential output current
amplifier. The output voltage of the voltage follower is a
voltage difference between v1 and v2 and is applied to the
impedance element. The output current of the voltage follower
is expressed as
v1 − v2
i0 =
.
(1)
Z
Signal currents flowing through the impedance element is
amplified by the current amplifier for current feedback. The
differential output current amplifier multiplies a signal current
i0 flowing through an impedance Z by N -times. The relationship of signal current i0 , i1 , and i2 are given by
i1 = i2 = N i0 .
(2)
The apparent impedance of this circuit is expressed as
Z
v1 − v2
= .
(3)
Zsc =
N i0
N
The impedance is reduced by current feedback. If the
impedance component Z is a capacitor which has capacitance
C, Zsc is expressed as
1
Zsc =
.
(4)
sCN
M15
M5
M6
VDD
Vb1
M16
M9
M24 M27
M23
M5 M4
M6
M28
Vb4
N :1
v1
v2
C
M1
Vb3
M2
M19
M3
i1
v1
i2
v2
M30
M20
M4
i0
M29
M22 M26
M21
M8
1: N
Vb4
M7
I1
VDD
M3
Vb3
i1
i0
i2
M2
v2
M1
v1
C
I1
M25
M1
M10 M11
M12
M13
M14
M31
Vb2
M18
Ni0
i0
1
i1
Z
i0
v2
1
i0
M10
VSS
Fig. 2. Circuit Diagram of the Conventional Floating Type Scaling Capacitor
Circuit
v1
M11
M9
gm5
i1
v1
Fig. 3. Block Diagram of the Proposed Symmetry-type Floating Scaling
Capacitor Circuit
This means that the circuit performs as floating capacitor
having capacitance N C. Fig.2 shows the circuit diagram of
the conventional circuit. The conventional circuit has current
inverting amplifier for current feedback to i2 . Thus, the conventional circuit structure is asymmetry.
P ROPOSED S YMMETRY- TYPE F LOATING I MPEDANCE
S CALING C IRCUIT
Fig.3 shows the block diagram of the proposed symmetrytype floating scaling capacitor circuit. This circuit is composed
of two voltage followers and two current amplifiers. The output
voltages of the voltage followers are applied to the impedance
element Z. The signal current flowing through the impedance
element is amplified with the current amplifier for current
feedback.
A. Basic Symmetry-type Floating Impedance Scaling Circuit
The circuit diagram of the symmetry-type floating
impedance scaling circuit based on the block diagram of
Fig.3 is shown in Fig.4. Hereinafter, this circuit is called as
“Proposed1”. The transistors M1 and M2 are source followers.
The input voltage signal is applied to the capacitor C through
the source followers. The current mirrors of M4 -M3 and M5 M6 perform as the current amplifier of N times. The signal
current flowing through the capacitor is amplified by the
current amplifier. Assuming that the resistance of the bias
current sources M9 and M10 are enough large, the signal
current flowing through the capacitor, i0 , is expressed as
i0 = (v1 − v2 )sC.
Rd
2C
rd
Fig. 5. Small Signal Equivalent Circuit of the Conventional Floating Type
Scaling Capacitor Circuit (“Proposed1”)
The impedance of this circuit is given by
Zsc =
v1 − v2
1
=
.
N (v1 − v2 )sC
sCN
(7)
Therefore, the apparent capacitance is increased by N times.
To confirm the frequency characteristics of “Proposed1”
shown in Fig.4, the small-signal characteristics are analyzed.
Assume that the fully differential voltages are applied to the
both terminals, the input voltages are expressed as
1
vin
2
1
v2 = − vin .
2
v1 =
(8)
(9)
The differential-mode half circuit of “Proposed1” is shown
in Fig.5. The resistance rd indicates the drain resistance of
the bias current source M10 . The resistance Rd indicates
the resistance component observed from terminal v1 . The
combined resistance Rd is the drain resistances connected
in parallel and expressed as Rd = rd /(2N ). Assuming that
gm rd ≫ 1, the impedance Z1 is given by
Z1 =
(6)
v2
gm2
(5)
The currents i1 and i2 are equal to N i, and expressed as
i1 = i2 = N (v1 − v2 )sC.
VSS
Fig. 4.
Circuit Diagram of the Symmetry-type Floating Type Scaling
Capacitor Circuit (“Proposed1”)
Ni0
III.
M7
1: N
N :1
gm6
i2
M8
v1
≃
i1
2gm5 Rd (2Cs + gm2 )
).
(
gm5
gm2 gm6 2Cs +
gm6 Rd
(10)
M19
M18
M17
VDD
M15
M16
rd18
Rd
gm4
Vb2
Vb2
M14 M4
M3 M13
i1
i2
M2
v2
M1
v1
Vb1
gm2
i1
v1
v2
2C
gm8
Vb1
M10
M12
M8
M11
C
M7
M6 M5
gm10
I1
gm6
M9
VSS
N : 1
:
1
1
:
1
: N
Fig. 6.
Circuit Diagram of the Symmetry-type Floating Type Scaling
Capacitor Circuit (“Proposed2”)
The pole frequency ωp and the zero frequency ωz are given
by
1
gm5
≃
(11)
gm6 Rd 2C
Rd N 2C
gm2
gm
ωz ≃
≃
,
(12)
2C
2C
where gm5 = gm2 = gm and gm6 = N gm . Because of rd >
1/gm , the pole frequency ωz is higher than the zero frequency
ωp . The pole frequency depends on the resistance component
Rd in the input terminal. The zero frequency depends on the
conductance gm of the input source followers associated with
capacitor employed in “Proposed1”.
Fig. 7. Small Signal Equivalent Circuit of the Conventional Floating Type
Scaling Capacitor Circuit (“Proposed2”)
TABLE I.
P OWER C ONSUMPTION AND A REA
Power Consumption (µW)
Area (µm2 )
42.6
35.8
37.7
1230
1100
1134
Conventional
Proposed1
Proposed2
ωp ≃
B. Improved Symmetry-type Floating Impedance Scaling Circuit
The circuit diagram of the symmetry-type floating
impedance circuit with improved operation bandwidth is
shown in Fig.6. Hereinafter, this is called as “Proposed2”. The
drain resistance of the bias current source M18 is indicated
by the resistance rd18 . The resistance components Rd in the
terminals v1 and v2 are larger, and the pole frequency is lower.
The conductance components gm1 and gm2 associated with the
capacitor are larger, the zero frequency is higher. In order to
the resistance component at the terminals v1 and v2 is enlarge,
the cascode stages configured with the common gate M11 -M14
is introduced. In order to the conductance component gm is
enlarge, the negative feedback circuits are composed of M3 M8 .
In order to confirm the frequency characteristics of “Proposed2”, the small-signal half circuit are analyzed. The smallsignal half circuit of “Proposed2” is shown in Fig.7. Assuming
that gm rd ≫ 1, the impedance Z1 is given by
v1
Z1 =
i1
2Rd [(gm4 + gm8 )2Cs + gm2 gm4 gm6 rd18 ]
(13)
≃
gm2 gm4 rd18 (gm10 Rd 2Cs + gm6 )
2
2Rd (4Cs + gm
rd )
≃ 2
,
(14)
gm rd (N Rd 2Cs + 1)
where gm2 = gm4 = gm6 = gm8 = gm , rd18 = rd , and
gm10 = N gm . The pole frequency ωp and the zero frequency
ωz are given by
1
(15)
Rd N 2C
g 2 rd
ωz ≃ m .
(16)
4C
Comparing “Proposed2” with “Proposed1”, Rd becomes gm rd
times with the cascode stages, the pole moves to lower
frequency. Comparing (16) with (12), the zero frequency is
multiplied by gm rd /2 times and moves to higher frequency.
The impedance Z1 in the range between the pole and the zero
frequencies, ωz ≫ ω ≫ ωp , is given by
ωp ≃
g2 r
d
2Rd · 4C(s + m
4C )
Z1 ≃ 2
gm rd · N Rd 2C(s + N R1d 2C )
(17)
g2 r
m d
4
· 4C
(18)
2
gm rd N
s
1
≃
.
(19)
N Cs
The “Proposed2” performs as an N -times capacitance in wider
than “Proposed1”.
≃
TABLE I shows the comparison of the power consumption
and the area. The power consumption and area are reduced by
11.5% and 7.8% in “Proposed2”, relatively.
C. Simulation Results
The validity of the proposed circuits is confirmed using simulation software SIMetrix(SIMetrix Technologies). The
transistor model used in the simulation is BISIM3 0.18µm
process model. The supply voltage is ± 0.9V. In order to
realize the scaled capacitance of 500pF, N and the capacitance
are set to 50 and 10pF, respectively. The tables of transistor
size are shown in TABLE II and TABLE III.
The impedance at the terminal v1 is confirmed simulation,
where the terminal v2 is grounded. The simulation results of
impedance and phase frequency characteristics are shown in
TABLE II.
T RANSISTOR S IZE OF P ROPOSED C IRCUIT (P ROPOSED 1)
Transistors
W (µm)/L(µm)
M3 , M6 , M8 , M11
the others
90.0 /1.8
1.8 /1.8
Vin
C1
Gm1
TABLE III.
T RANSISTOR S IZE OF P ROPOSED C IRCUIT (P ROPOSED 2)
Transistors
W (µm)/L(µm)
M9 -M14 , M16 , M19
the others
90.0 /1.8
1.8 /1.8
Vout
CMR
Gm2
Fig. 10.
Lowpass Filter Employing Symmetry-type Floating Impedance
Scaling Circuit (“Proposed LPF”)
M7
M5
M6
I1
9
10
M2
Impedance[Ω]
vCM
6
10
3
10
Ideal
Proposed1
Proposed2
Conventional
Fig. 11.
0
2
10
4
10
6
10
8
10
Frequency[Hz]
Fig. 8.
Impedance Characteristics
Phase[degree]
−180
−270 −2
10
αvinn
M9
M4
I2
αvinp
I5
Ideal
Proposed1
Proposed2
Conventional
10
0
2
10
4
10
6
10
vinp
vinn
M15
αvinp
M14
αvinn
I6
M21
ioutp
I4
M10 M11 M12 M13
vinp
M6
M17
M16
vinn
αvinn
M18
M20
I7
I9
Vss
Low-gm Linear OTA
T HE B IAS C URRENT S OURCE
Current Source
Current (nA) (µm2 )
I1 = I8
I2 = I5 = I7 = I9
I3 = I4
I6
50
100
68.3
36.6
8
10
Frequency[Hz]
Fig. 9.
I3
vinn
TABLE IV.
−90
M19
M22
M2
M3
Fig. 12.
M8
Vdd
M1
90
M9
I8
M7
αvinp
0
M10
M5
M8
ioutn
vinp
M11
Common-mode Rejection Circuit
I1
10
vCM
M4
M12
0
10 −2
10
M3
M1
Phase Characteristics
Fig.8 and Fig.9, respectively. The solid line indicates the
proposed circuit of “Proposed2”, the dash-dotted line indicates
the proposed circuit of “Proposed1”, the broken line indicates
the conventional impedance scaling circuit [5], and the dotted
line indicates the ideal capacitor of 500pF. From the impedance
characteristic of “Proposed1”, it is seen that the pole and
the zero are at the near frequencies. The phase characteristic
dose not become –90◦ even in the frequency range, thus the
operation bandwidth is very narrow. The impedance characteristic of “Proposed2” shows the capacitor characteristics in
the range from 100Hz to 100kHz. It is notice that comparing
“Proposed2” with “Proposed1”, the pole frequency is lower
and the zero frequency is higher. Furthermore, comparing to
the conventional circuit, the characteristics of “Proposed2” are
improved in range higher frequency.
IV.
A PPLICATION TO F ULLY D IFFERENTIAL F ILTER
A. Configuration of Fully differential Lowpass Filter
Employing “Proposed2”, a fully differential 1st-order lowpass Filter(LPF) shown in Fig.10 designed in this research. The
capacitor is implemented employing the floating impedance
scaling circuit. The transfer function of the lowpass filter T (s)
is expressed as
T (s) =
Gm1
,
sC1 + Gm2 + 1/R
(20)
where Gm1 and Gm2 are the transconductances of OTAs, and
R is the combined resistance composed of the symmetrytype impedance scaling circuit and the common-mode rejection
circuit. The low-gm linear OTA shown in Fig.12 is used as
Gm1 and Gm2 [6]. TABLE IV shows the bias current in the
OTA. The transconductance of the OTA is Gm1 = Gm2 =
606.7nS. In order to realize the LPF of fc =100Hz and the
scaled capacitance 965.7pF, N and the capacitance is set to
50 and 19.31pF, respectively.
0
Rd
rd18
−20
Gain
gm4
iin
vin
−40
gm2
−60
Proposed LPF
−80
Ideal Capacitor
−100
Ideal
−120
270
gm8
gm6
rd6
gm10
Fig. 14.
Small Signal Equivalent Circuit of the Floating Type Scaling
Capacitor Circuit for Common-mode Signal (“Proposed2”)
6
10
90
5
0
−90
−180
0
10
2
4
10
10
6
10
10
Impedance [Ω]
Phase [degree]
180
8
10
4
10
CMR
3
10
Frequency [Hz]
Fig. 13.
CMR + ISC
ISC
2
Frequency Characteristics of Lowpass Filter
10
90
Phase [degree]
B. Frequency Characteristics
The frequency characteristics of “Proposed LPF” shown
in Fig.10 are shown in Fig.13. The solid line indicates the
characteristics of “Proposed LPF”, the dashed line of “Ideal
Capacitor” indicates the characteristics of the LPF in which
the capacitor is an ideal element, and the dotted line of “Ideal”
indicates the ideal LPF.
0
−90
−180
From Fig.13, the proposed circuit shows the characteristics
as the floating capacitor. The pass band gain of “Proposed
LPF” is reduced comparing “Ideal”. It can be considered that
the pass band gain are reduced by the combined resistance
component R of the common-mode rejection circuit and the
impedance scaling circuits.
10
4
6
10
8
10
Frequency [Hz]
Fig. 15.
Common-mode Impedance
of the half circuit is given by
C. Common-mode Impedance Characteristics
The current never flow when the same voltage are applied
to the both terminals of passive elements, and the impedance
is obviously infinite. However, because of the impedance
scaling circuit is synthesized with transistors, the impedance
to the same voltage at both terminal is finite, practically.
Although it may not be correct expression, such an impedance
is called “common-mode impedance” in this paper. Appling
the common-mode voltage vCM to the both terminals of
“Proposed2”, the output voltages of the source followers M1
and M2 are equal, currents do not flow in the capacitor C
associated with the source followers. Thus, the capacitor C
can be considered as an open element. The common-mode half
circuit is shown in Fig.14. The rd6 , rd18 , and Rd indicates
the drain resistances of the transistor M6 , the bias current
source M18 , and the resistance component at the terminal v1 ,
respectively. Assuming that gm rd ≫ 1, the impedance ZCM
Rd rd6 (gm4 + gm8 + gm4 gm6 rd18 )
rd6 (gm2 + gm4 + gm4 gm6 rd18 ) − gm10 Rd gm4 rd18
(21)
Rd rd6 gm6
≃
.
(22)
gm6 rd6 − gm10 Rd
ZCM ≃
Moreover, assuming that we have Rd gm10 ≫ rd6 gm2 ,
rd6
,
(23)
N
where gm6 = gm , gm10 = N gm . For the common-mode signal, the symmetry-type impedance scaling circuit performs as
a negative resistance −rd6 /N due to positive current feedback.
ZCM ≃ −
The simulation results of the common-mode impedance
and the phase characteristics are shown in Fig.15. The solid
line of “CMR+ISC” indicates the result of the parallel of
the common-mode rejection circuit and the symmetry-type
Voltage [V]
0.1
0
−0.1
0
Fig. 16.
employing the proposed circuit has been confirmed through the
simulation results. By the small signal analysis, it had been
shown that the proposed impedance scaling circuit becomes
the negative conductance when the same voltages are applied
to both terminals. This negative resistance can be ignored due
to the small common-mode resistance of the common-mode
rejection circuit. The future work is the improvement of the
pass band gain and the application for the higher-order filters.
Square Wave, 50Hz, ±200mVp-p
Output Voltage
ACKNOWLEDGMENT
0.2
This study was supported by JSPS Grant-in-Aid for Scientific Research (C 24560436).
0.1
Time [Sec]
Transient Characteristic
floating impedance scaling circuit, the dashed line of “CMR”
indicates the common-mode rejection circuit, the dotted line of
“ISC” indicates the symmetry-type impedance scaling circuit
of“Proposed2”. From the phase characteristic of “ISC”, it
is shown that the symmetry-type floating impedance scaling
circuit performs as the negative resistance in lower frequency
range. The phase characteristic of “ISC+CMR” performs as
the positive resistance. Consequently, because of the combined
impedance of “CMR” and “ISC” is positive from the characteristics of “CMR+ISC”, the operation of the LPF is stable. The
transient Characteristic of the LPF employing the symmetrytype floating impedance scaling circuit, the common-mode
rejection circuit, and low-gm linear OTA, is confirm. The
simulation results of the transient Characteristic is shown
in Fig.16. The input voltage signal is the square wave that
is 50Hz, ±200mVp-p . The solid line of “Output Voltage”
indicates the output waveform. There are no oscillation in the
simulation results. It is seem that the operation proposed circuit
is stable.
V.
C ONCLUSION
In this paper, for the application of the biomedical signal
processing, a design of a symmetry-type floating impedance
scaling circuit and the improvement methods of those operation bandwidth had been proposed. The proposed circuit is
simply composed of two source followers and two current
controlled current source. The configuration of the proposed
circuit is symmetry. From the small signal analysis, the improvement methods of the operating bandwidth are found. In
order to lower the pole frequency, the resistance component
in the parts of input terminals had been increased by introducing the common gate, and to enhance the zero frequency,
the conductance component associated to the capacitor had
been enhanced by negative feedback. To realize the scaled
capacitance of 500pF, N and the capacitance are set to 50
and 10pF, respectively. The impedance characteristic of the
synthesized impedance scaling circuit had shown the capacitor
characteristics in the range from 10Hz to 100kHz. Comparing
to the conventional impedance scaling circuit, the characteristics of the proposed circuit had been improved in side of
high frequency. The power consumption and area are reduced
comparing the conventional circuit. The fully differential 1storder bandpass filter with the f c = 100 Hz has been designed
employing the proposed floating impedance scaling circuit.
The appropriate operation of the proposed circuit and the LPF
R EFERENCES
[1] C.-L. Hsu, M.-H. Ho, Y.-K. Wu, and T.-H. Chen, “Design of lowfrequency low-pass filters for biomedical applications,” in Circuits and
Systems, 2006. APCCAS 2006. IEEE Asia Pacific Conference on, Dec
2006, pp. 690–695.
[2] J. Silva-Martinez and S. Solis-Bustos, “Design considerations for high
performance very low frequency filters,” in Circuits and Systems, 1999.
ISCAS ’99. Proceedings of the 1999 IEEE International Symposium on,
vol. 2, Jul 1999, pp. 648–651.
[3] A. Veeravalli, E. Sanchez-Sinencio, and J. Silva-Martinez, “A CMOS
transconductance amplifier architecture with wide tuning range for very
low frequency applications,” Solid-State Circuits, IEEE Journal of,
vol. 37, no. 6, pp. 776–781, Jun 2002.
[4] J. Silva-Martinez and A. Vazquez-Gonzalez, “Impedance scalers for ic
active filters,” in Circuits and Systems, 1998. ISCAS ’98. Proceedings
of the 1998 IEEE International Symposium on, vol. 1, May 1998, pp.
151–154 vol.1.
[5] F. Matsumoto, T. Fujii, S. Nishioka, T. Abe, and T. Ohbuchi, “Design
of a floating-type impedance scaling circuit for large capacitances,” in
Intelligent Signal Processing and Communications Systems (ISPACS),
2013 International Symposium on, Nov 2013, pp. 391–396.
[6] F. Matsumoto, R. Sugimoto, T. Ohbuchi, and T. Abe, “A synthesis
of linear transconductors using MOSFETs operating in weak-inversion
region based on SINH circuit,” in Proc. IEEJ Int Analog VLSI Workshop,
Bali, Indonesia, Nov. 2011, pp. 15–20.