ECE3281 Electronics Laboratory
Experiment #3
TITLE:
COMBINATIONAL LOGIC
OBJECTIVE: Assess basic logic gates and synthesize a combinational function
Commentary: Logic circuits are defined in terms of binary arithmetic. For most binary logic gates, logic-1 is a voltage level
above 2.0V and logic-0 is a voltage level below 0.8V. In this exercise we will look at a logic family that uses one of the older
and tougher technologies, TTL, for which logic-1 may be as high as 5.0V.
Combinational logic is made up of combinations of gates. Multiple inputs are used to define one or more logic outputs by
means of a logic function, which is an arithmetic form of the Boolean logic that we use to effect a given requirement. Often
these logic functions find their way into special applications that are necessary to actuate a given system. In higher-level systems they are sythesized by means of software, and the function is packaged as a special-purpose integrated circuit.
The basic package used for prototyping is shown by figure 3.1a. Typically it is a dual-inline package (DIP) with pins numbered as indicated, and which typically exist with more than the 14-pins. Be aware that the numbers are not printed on the
case. The only way that they are defined is by pin-1, which is identified either by an indentation as indicated by figure 3.1b, or
by an orientation as indicated by figure 3.1c.
You will find that the DIP package fits nicely onto the white prototyping boards. And for TTL, the power supply requirement
will always be +5V, for which you should find a dedicated +5V supply on the MFJ prototyping box.
14
13
12
11
10
9
8
Figure 3.1b: Indentation marking pin 1
1
2
3
Figure 3.1a: 14-pin DIP
4
5
6
7
Figure 3.1c: Alternate method for marking pin 1
Pinout diagrams for each of the logic gates of interest to you will be in appendix 3A. You might take note of the fact that the
power supply rails (+5V, GND) are always on the opposite corners (for a 14-pin package, pins 14, and 7, respectively). So
make durn sure that you orient the pins correctly with respect to the power supply, as indicated by figure 3.1. Otherwise you
will burn up the chip, and not be able to complete the experiment, which will be reflected in your score.
Take note also that there are usually several logic gates in one package. Use that to your advantage to make your wiring as
simple as possible. The DIPs that you will need are your parts box (in the parts/wires drawer). If deficient, check with your
instructor.
PROCEDURE:
I. Basic 2-input gates
A-1: AND gate: Insert a quad (four in a package) 2-input AND gate (SN7408) into the prototyping motherboard. Check
appendix 3-A for the pinout for this package. Check figure 3-A.1 for suggestions as to placement and wiring. Do not turn on
the power until the instructor has had a chance to make a check.
A-2: Choose any one of the four logic gates in the package and cycle through the four input logic states for the AND gate
as indicated by the truth table (appendix 3A) and record the output states, both as binary values and as voltages (make up a
truth table of your own, such as indicated by figure 3.A-2. Are the output voltages the same for each of the three low states?
A-3: Disconnect the inputs altogether and record the output voltage. You should find that the “high-impedance” (disconnected) inputs will (usually) cause the output to drift “high” for TTL.
SWITCH
FREQUEBCY
BNC
OUTPUT INDICATORS
10KΩ
MULTIPLIER
(To DMM)
WAVEFORM
V+
VOLTAGE
12V
5V
AMPLITUDE
GND
DC OFFSET
1KΩ
POWER
CLOCK
PULSE
LOGIC SWITCHS
MFJ
Figure 3A-1: Recommendations for set-up. (MFJ Box with prototyping motherboard)
AND gate truth table
A
out (= AB)
B
Figure 3A-2: Logic gate and truth table
A
B out
0
0
0
1
1
0
1
1
Vout
A-4: Connect two of the 2-input AND gates to implement the function f = ABC, as shown by figure 3A-3. This arrangement is equivalent to a 3-input AND. Confirm the truth table and check output voltage levels.
3-input AND gate truth table
A
out (= ABC)
B
C
Figure 3A-2: Logic gate and truth table
A B C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
out
Vout
B-1: OR gate: Insert a quad 2-input OR gate (SN7432) into the prototyping motherboard. Check appendix 3-A for the
pinout for this package. Note that it is the same as for the AND gate. So you can use figure 3-A.1 as suggestion for your
placement and wiring, should you so choose. Figure 3B-1 is provided just to indicate the symbol used for the OR gate.
OR gate truth table
A
out (= A+ B)
B
Figure 3B-1: Logic gate and truth table
A
B out
0
0
0
1
1
0
1
1
Vout
B-2: Choose any one of the four logic gates in the package and cycle through the four input logic states as indicated by
the truth table (appendix 3A) and record the output states, both as binary values and as voltages. Are the output voltages the
same for each of the three high states?
B-3: Disconnect the inputs altogether and record the output voltage. You should find that the “high-impedance” (disconnected) inputs will (usually) cause the output to drift “high” for TTL.
C-1: NAND gate: Insert a quad 2-input NAND gate (SN7400) into the prototyping motherboard. Check appendix 3-A
for the pinout for this package. The NAND gate is the basic building block used for almost all combinational TTL logic functions. Note that it is the same as for the other two-input gates and so you can use figure 3-A.1 as suggestion for your placement
and wiring, should you so choose. Figure 3C-1 is provided just to indicate the symbol used for the NAND gate.
NAND gate truth table
A
out (= AB)
B
Figure 3C-1: Logic gate and truth table
A
B out
0
0
0
1
1
0
1
1
Vout
C-2: Choose any one of the four logic gates in the package and cycle through the four input logic states as indicated by
the truth table (appendix 3A) and record the output states, both as binary values and as voltages. Are the output voltages the
same for each of the three high states?
C-3: Disconnect the inputs altogether and record the output voltage. You should find that the “high-impedance” (disconnected) inputs will (usually) cause the output to drift “high” for TTL.
C-4: Connect three of the 2-input NAND gates to implement the function f = ABC , as shown by figure 3C-2. This
arrangement is equivalent to a 3-input NAND. Note that we had to be a little clever about the implementation, because we
needed and AND gate, and we achieved that by following a NAND gate with a NOT gate (in this case a NAND gate with the
inputs shorted together. Cycle through and confirm the truth table and check output voltage levels.
3-input NAND gate truth table
A
out (= ABC)
B
C
Figure 3C-2: Logic gate and truth table
A B C
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
out
Vout
D-1: NOR gate: Insert a quad 2-input NOR gate (SN7402) into the prototyping motherboard. Check appendix 3-A for
the pinout for this package. The NOR gate is the second of the basic building blocks used for almost all combinational TTL
logic functions. Note that it’s pinout is not exactly the same as the other two-input gates. But that’s OK. Your expertise
should be sufficient at this point to accommodate
NOR gate truth table
A
out (= A+ B)
B
Figure 3D-1: Logic gate and truth table
A
B out
0
0
0
1
1
0
1
1
Vout
D-2: Choose any one of the four logic gates in the package and cycle through the four input logic states as indicated by
the truth table (appendix 3A) and record the output states, both as binary values and as voltages. Are the output voltages the
same for each of the three low states?
D-3: Disconnect the inputs altogether and record the output voltage. You should find that the “high-impedance” (disconnected) inputs will (usually) cause the output to drift “high” for TTL.
E-1: Implement the logic function f = a ( b + c ) using any combination of logic gates you choose. Set up truth table tests
and use the MFJ prototyping platform to confirm functional behavior.
E-2: Implement the logic function f = ab + ab using any combination of logic gates you choose. Set up truth table tests
and use the MFJ prototyping platform to confirm functional behavior.
REPORT: This is an informal report, completed by checkoff from your instructor. Turn in all of your truth tables and results
arranged in neat form.
APPENDIX 3A: Pinout diagrams for selected quad 2-input DIPs:
14
13
12
11
10
9
8
SN7408
SN74LS08
+5V
Quad AND
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
+5V
2
14
3
13
4
12
5
11
6
10
B
AND
0
0
0
1
0
0
1
0
0
1
1
1
A
B
NAND
SN7400
SN74LS00
0
0
0
1
1
1
Quad NAND
1
0
1
1
1
0
A
B
OR
0
0
0
1
0
1
1
0
1
1
1
GND
1
A
7
9
8
+5V
SN7432
SN74LS32
Quad OR
GND
1
2
3
4
5
6
7
1
14
13
12
11
10
9
8
A
B
SN7402
SN74LS02
0
0
0
1
1
0
Quad NOR
1
0
0
1
1
0
+5V
GND
1
2
3
4
5
6
7
NOR