IEEE PEDS 2011, Singapore, 5 - 8 December 2011
The effect of Space Vector Modulation on Capacitor
Voltage Ripple in a Cascaded H-bridge StatCom
C.D. Townsend1 , J. Vodden2 , A.J. Watson2 , T.J. Summers1 , R.E. Betz1 , J.C. Clare2
1 School of Electrical Engineering and Computer Science
University of Newcastle, Australia
2 School of Electrical and Electronic Engineering
University of Nottingham, UK
Abstract—Employing space vector modulation in a multi-level
H-bridge StatCom (H-StatCom) can provide an excellent tradeoff between harmonic performance and switching frequency.
However the nature of the techniques used to balance the capacitor voltages in this modulation strategy can increase capacitor
voltage ripple. This paper compares the key performance indicators in differing space vector modulation techniques including
capacitor voltage ripple, total harmonic distortion and switching
losses. It is shown that while one of these techniques significantly improves the trade-off between harmonic performance
and switching loss it can also significantly reduce the capacitor
lifetime due to the form of the resultant ripple currents.
I. I NTRODUCTION
Multi-level Static Compensators (StatComs) are increasingly being implemented using cascaded H-bridge converters.
The main reasons for the choice of this topology are that the
number of components used in construction scales linearly
with the level number [1], [2] and that the H-bridges form a
modular section of each phase-leg which makes construction
and maintenance easier. The other important advantage of the
H-bridge multi-level converter is that the topology is ideally
suited to reactive power and harmonic filtering applications
as the converter does not need to handle any real power,
and therefore there is no need for expensive isolated DC
power supplies [3]. Throughout the remainder of this paper
the acronym H-StatCom will be used to refer to a multi-level
StatCom implemented using cascaded H-bridges.
Traditional techniques for controlling the firing of the Hbridges in the individual phase legs of a H-StatCom use either
multiple triangular carrier waves for each of the bridges (PSCPWM) [4], [5] or precomputed firing angles for the bridges
to implement Selective Harmonic Elimination (SHE) [6]. This
paper compares the common implementations of the Space
Vector Modulation (SVM) technique which has received an
increased research focus, in application to this topology, due to
its ability to exploit the large number of redundant switching
states. One of the main advantages of utilising SVM is the
relative ease of incorporating a capacitor voltage balancing
scheme into the modulation process. This scheme uses a
sorting algorithm to choose which H-bridges are used to create
the output voltage waveforms. This creates an extra degree of
freedom to inherently share the leg cluster voltage (the addition
of all capacitor voltages in a phase-leg) across the individual
H-bridge capacitors. A separate control loop keeps the leg
cluster voltages at a setpoint value [7]. This type of balancing
technique avoids the control loop interaction problems present
in traditional modulation strategies [8].
This paper compares two different implementations of the
SVM technique applied to H-StatComs, in terms of the trade-
Figure 1.
StatCom
Circuit configuration of the star-connected 19-level H-bridge
off between harmonic performance and switching losses. The
differences in the voltage balancing characteristics and the
corresponding effect on capacitor lifetime is also investigated.
II. BACKGROUND
Fig. 1 shows the circuit configuration for a 19-level (line to
neutral) H-StatCom. Each stack of H-bridges essentially forms
one phase of a three phase current controlled voltage source.
The purpose of the H-StatCom is to modulate the voltage
at the output of each stack so that the current through the
inductors can be controlled to provide power factor correction,
compensate for system harmonics, and alleviate other power
quality problems. In this paper a dead-beat current control
method is employed to derive the required H-StatCom voltage
demands.
Fig. 2 is a block diagram of the control scheme employed
with each type of SVM technique. Where Qr is the demanded
reactive power, Pr is the demanded real power, iQ
r is the
constituent reactive current component of the power, iPr is the
constituent real current component of the power, vrleg is the
target cluster voltage for each phase, vla , vlb and vlc are the
measured cluster voltages for each phase, ir is the reference
current, vrlim is the limited voltage generated by the dead-beat
controller, isc is the measured H-StatCom current, Vdc1..27 are
the measured capacitor voltages and vg is the measured supply
voltage. The subscript _ is used to denote a vector quantity.
978-1-4577-0001-9/11/$26.00 ©2011 IEEE
834
Power Control
Qr
PQ
Q= S
r vg
+
§ + Kp+sKi s
i
Q
r
Pr = 0
Vector
Current
Limiter
ir
P
ir
§ -
Qsc S = isc v¤g
techniques to synthesise that vector.
isc
vg
Psc
isc
i
Power
Measurement
+
Deadbeat v
r
Current
Control
vg
v rlim
vla ; vlb ; vlc
Vector
Voltage
Limiter
isc
v rlim
V dc1
State
Selection &
Capacitor
Balancing
: : 27
sw1;2;3
isc
Power
System
PWM
Gen
vg
Leg
Voltage
Control v
g
vg
vrleg
Figure 2.
Block diagram of the H-StatCom control with SVM.
As can be seen from Fig. 2 the control is hierarchical,
with the inner part of the structure executing the dead-beat
current control and state selection scheme with the outer level
responsible for the control of real and imaginary power. The
PQ block uses instantaneous power theory [9] to decompose
the demanded reactive power into its constituent reactive
current component. The Leg Voltage Control block uses the
component of the current associated with real power to balance
the cluster voltages. This is achieved by normalising system
voltage predictions (from a phase locked loop) and then
scaling these values to form the desired component of the
current associated with real power, the sign of the current
being dependent on the error between the target and measured
cluster voltages.
The current controller is based on a popular dead-beat current controller used in variable speed drive applications [10],
[11]. This control strategy has a high bandwidth (depending on
the control frequency), and is relatively simple to implement.
The basic equations used to calculate the required output HStatCom voltage are shown in (1) and (2).
L ref
(i − îk ) + v̂ref
(1)
k+0.5
T k+1
T
sys
(2)
îk = ik−1 + (vk − vk−0.5 )
L
where ik−1 is the instantaneous sample of the current at
time t = (k − 1) T and iref
k+1 is the instantaneous value of the
reference current at time t = (k + 1) T . As for the voltage
nomenclature, vk is the actual voltage applied during the
interval from (k − 1) T → kT , vref
k+1 is the desired (or reference)
voltage that the controller applies from kT → (k + 1) T , v̂ref
k+0.5
is the predicted instantaneous supply voltage at the midpoint
sys
of the control interval from kT → (k + 1) T and vk−0.5 is the
measured instantaneous supply voltage at the midpoint of the
control interval from (k − 1) T → kT . T is the control period
and L is the connection inductance between the H-StatCom
and the three-phase system.
The output of the dead-beat current controller is appropriately limited to ensure that the converter is capable of
producing the desired voltage at the output of the H-StatCom.
Having formed the desired voltage vector the State Selection
and Capacitor Balancing block implements one of two SVM
vref
k+1 =
III. S PACE V ECTOR M ODULATION
The first SVM technique is a relatively simple scheme that
chooses the switching states directly from the magnitude of
the three directional components of the desired output voltage
vector [7]. The second scheme uses an explicit vector representation that allows identification of appropriate switching
states that can synthesise a voltage space vector [12], [13].
A. SVM with Implicit Vector Representation
The scheme outlined in [7] executes the following process
each control cycle to create the desired output voltage vector.
Firstly the desired voltage vector is broken down into its
three constituent elements corresponding to the desired output
voltage from each phase. The capacitor voltages are then
sorted in descending order of voltage if the instantaneous
power flow is out of the phase leg, and in ascending order
if the power flow is into the phase leg. Then, the number of
capacitors required to create an output voltage less than or
equal to the value of the desired output voltage is determined.
This process starts at the top of the sorted queue of capacitor
voltages. The residual voltage left over by this process will be
of less magnitude than the next capacitor voltage. This residual
voltage is then produced by using symmetrical PWM of the
next H-bridge in the ordering.
The other H-bridges selected in the process are switched so
that their capacitor voltages are applied for the whole of the
next control interval. The polarity of the output voltage from
these bridges is dependent on which half of the fundamental
cycle the control interval resides. Those that are not selected
output the zero voltage. Using this algorithm the least charged
capacitors are charged, and the most charged capacitors are
discharged depending on the instantaneous power flow direction.
Fig. 3 demonstrates the implicit SVM current tracking
performance and the form of the capacitor voltages when a 19level H-StatCom is absorbing 6.7kvar inductive, with a control
frequency of 1kHz. It can be seen that the system achieves a
good current tracking performance with tight control over the
capacitor voltages.
Fig. 4 shows the performance of the same system for the
same operational condition. The number of average switching
transitions occurring on the switching components in phase ’a’
is shown in the middle plot. For the 0.6s period the average
number of switching transitions is 320. The Total Harmonic
Distortion (THD) of the H-StatCom current is 2.5%.
B. SVM with Explicit Vector Representation
The schemes outlined in [12] and [13] initially transform the
voltage space vector onto a two dimensional plane in which
the switching state vectors have only integer components.
This allows the three nearest voltage vectors to be easily
identified by rounding the two directional components of the
desired space vector. Once these vectors are identified the
associated duty cycles that are required to synthesise the
average output voltage vector can be calculated via simple
algebraic equations.
For high power H-StatCom applications it is important
to minimise the switching losses in each H-bridge module.
835
Voltage (V) : t(s)
200.0
0.0
−200.0
Vstat
400.0
Voltage (V)
Voltage (V)
400.0
−400.0
200.0
0.0
Voltage (V) : t(s)
Vsys
−200.0
−400.0
Voltage (V) : t(s)
60.0
Vdc1
Vdc2
50.0
Vdc3
Vdc4
Voltage (V)
40.0
Vdc5
30.0
Vdc6
Vdc7
20.0
Vdc8
Vdc9
10.0
Current (A) : t(s)
I_meas
Current (A)
0.0
20.0
10.0
0.0
−10.0
−20.0
0.6
0.61
0.62
0.63
0.64
0.65
0.66
0.67
0.68
0.69
0.7
t(s)
Figure 3. Simulation waveforms for phase ’a’ when utilising the implicit
vector representation SVM scheme - Top plot: output H-StatCom voltage and
system voltage, Middle plot: Nine H-bridge capacitor voltages, Bottom plot:
H-StatCom current
Voltage (V)
Voltage (V) : f(Hz)
V_stat
40.0
20.0
0.0
0.0
500.0
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
f(Hz)
Transitions
Transitions : t(s)
Sw_trans
400.0
300.0
200.0
(1.2999, 319.78)
100.0
Current (A) : t(s)
I_meas
0.0
Current (A)
50.0
0.0
I_ref
−50.0
0.7
0.8
0.9
1.0
1.1
1.2
1.3
t(s)
Figure 4. Simulation waveforms for phase ’a’ when utilising the implicit
vector representation SVM scheme - Top plot: FFT of the output H-StatCom
voltage, Middle plot: Average number of switching transitions occurring on
phase ’a’ switching components, Bottom plot: H-StatCom measured and
reference current
When the desired voltage vector in the explicit SVM scheme
moves around the two dimensional plane the vectors which are
used to create the output voltage have multiple redundancies
across the three phases. The choice of which vectors to use
is constrained by the need to minimise the resultant number
of switching transitions. By integrating this constraint into the
modulation scheme the harmonic performance trade-off with
the switching losses is greatly improved [14].
The vector representation forms a mesh of triangles of
which the vertices correspond to the different switching state
vectors. The explicit SVM scheme produces one switching
transition each control cycle per phase-leg plus any transitions
required to move the space vector between the triangles in the
two dimensional plane. A similar technique to that described
in the implicit SVM scheme can be utilised to balance the Hbridge capacitor voltages for such a progression of switching
states.
The choice of which H-bridge is switched in or out to
create each step in output voltage is determined by using the
same sorting algorithm as that described above. To balance
the capacitor voltages the scheme must have knowledge of
the instantaneous direction of the power and the direction of
the required step in output voltage [13]. With this knowledge
the step in output voltage is created by switching in or out
a capacitor whose subsequent voltage will be closer to the
average of all the voltages in the phase-leg.
While this technique is capable of balancing the capacitor
voltages, it lacks the ability to apply a maximum control action
to minimise capacitor voltage ripple, particularly as the level
number increases. This is a consequence of the number of
H-bridges which under-go a change in state being limited by
location, and subsequent progression, of the desired voltage
vector.
A voltage ripple compensation scheme has been proposed
in [13]. This scheme minimises the effect of the twice frequency power oscillations that distort the two dimensional
vector representation. This is achieved by first overlaying the
inverse of the average capacitor voltage vector onto the desired
voltage vector. The result is a circular trajectory for the output
voltage vector where the effect of twice frequency voltage
ripple is negated by the distortion introduced into the vector
representation. However this scheme uses the average of the
capacitor voltages for each phase-leg in the development of the
distorted representation. This assumes the capacitor voltages
remain tightly balanced throughout the converter’s operation.
Fig. 5 demonstrates the explicit SVM current tracking
performance and the form of the capacitor voltages when a 19level H-StatCom is absorbing 6.7kvar inductive, with a control
frequency of 1kHz. This is an example of a situation where
the assumption of tightly bounded capacitor voltages is not
valid. There is significant voltage ripple outside the typical
100Hz deviation. This is a consequence of utilising more
modestly sized capacitors with a relatively large H-StatCom
current and low switching frequency (which is required in high
power applications to minimise the cooling requirements of
the H-bridge modules). These conditions increase the rate of
change in the capacitor voltages that can be experienced per
control cycle. With the limited control action that the balancing
scheme is able to employ, it is not possible to restrict these
increased deviations. Section IV will consider the effects of
these increased deviations on capacitor lifetime.
The increased capacitor voltage ripple will also have important consequences for the current tracking performance when
using the explicit SVM scheme. Some of the capacitor voltages
are no longer sufficiently close to their mean value, meaning
that if these capacitors are used to create the output voltage
there will be a significant error in the average voltage vector
that is synthesised at the output of the H-StatCom. This will
result in the creation of lower order harmonic distortion into
the output voltage waveforms, and hence an increase in the
836
300.0
200.0
200.0
100.0
0.0
-100.0
t(s)
Va_stat
100.0
Voltage (V) :
0.0
-200.0
-300.0
-300.0
-400.0
-400.0
t(s)
Va_sys
-100.0
-200.0
Voltage (V) : f(Hz)
30.0
Voltage (V)
400.0
300.0
Voltage (V)
Voltage (V)
Voltage (V) :
400.0
Mag(a)
20.0
10.0
0.0
0.0
Voltage (V) :
500.0
1.0k
1.5k
2.0k
2.5k
3.0k
3.5k
4.0k
4.5k
Voltage (V) : t(s)
Vdc1
90.0
ea1
60.0
Vdc2
ea2
80.0
Vdc3
ea3
70.0
58.0
ea4
Vdc5
Vdc6
50.0
Voltage (V)
Voltage (V)
Vdc4
60.0
Vdc7
40.0
5.0k
f(Hz)
t(s)
ea5
56.0
ea6
Vdc8
ea7
30.0
Vdc9
ea8
54.0
Current (A)
30.0
20.0
10.0
0.0
-10.0
-20.0
-30.0
90.0m
:
ea9
t(s)
Ia
52.0
Transitions : t(s)
Sw_trans
200.0
0.1
0.11
0.12
0.13
0.14
t(s)
0.15
0.16
0.17
0.18
0.19
0.2
Transitions
Current (A)
20.0
100.0
(0.7, 135.89)
Figure 5. Simulation waveforms for phase ’a’ when utilising the explicit
vector representation SVM scheme - Top plot: output H-StatCom voltage and
system voltage, Middle plot: Nine H-bridge capacitor voltages, Bottom plot:
H-StatCom current
Current (A)
0.0
Current (A) : t(s)
I_meas
20.0
10.0
0.0
-10.0
-20.0
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
t(s)
harmonic content of the H-StatCom current waveforms.
Fig. 6 shows the performance of the explicit SVM scheme
for the same operational condition as Fig. 5 with significantly larger (10x) capacitance values utilised in the H-bridge
modules. For this condition the capacitor voltage ripple will
not affect the harmonic performance trade-off with switching
losses. The number of average switching transitions occurring
on the switching components in phase ’a’ is shown in the
middle lower plot. For the 0.6s period the average number
of switching transitions is 136. The THD of the H-StatCom
current is 2.1%.
This result translates to more than a three times improvement in the harmonic performance trade-off with the switching
losses, when utilising the explicit rather than implicit SVM
scheme. However it is important to note that this explicit SVM
performance is only achieved in steady state operational conditions. For more dynamic situations where the output voltage
vector moves transiently around the vector representation a
larger number of switching transitions will result.
The authors have developed a H-StatCom simulation which
implements PSC-PWM. This simulation replicates the performance of the implementation described in [8]. This simulation
provides the theoretical values of total harmonic distortion
which can be achieved within the H-StatCom system. To gain
the same harmonic performance (identical THD values) to that
of the explicit SVM scheme described in this paper, the PSCPWM simulation requires a carrier frequency of 200Hz. For
PSC-PWM each switching device will undergo two switching
transitions per period of the carrier waveform, this is due to
the fact that PSC-PWM switches in each bridge during every
period of the carrier waveform. This means the total switching
transitions per component for a 0.6s period of time will be 240.
Given that the explicit SVM scheme produced 136 transitions
with the same harmonic performance indicates that explicit
Figure 6. Simulation waveforms for phase ’a’ when utilising the explicit
vector representation SVM scheme - Top plot: FFT of the output H-StatCom
voltage, Middle upper plot: Nine H-bridge capacitor voltages, Middle lower
plot: Average number of switching transitions occurring on phase ’a’ switching
components, Bottom plot: H-StatCom measured and reference current
SVM is capable of exceeding the performance of PSC-PWM
by up to 75%.
IV. C APACITOR L IFETIME
The explicit SVM scheme increases the excursions of the
capacitor voltages outside of the normal 100Hz ripple which is
typically seen on H-StatCom capacitors. The implicit scheme
however maintains very tight control over the capacitor voltages. Given these differences, it is possible to investigate the
relationship between the form of capacitor voltage ripple and
capacitor lifetime.
The majority of converters utilise electrolytic capacitors
to provide stiff DC link voltages. A particular model of
an electrolytic capacitor is shown in Fig. 7. This relatively
complex model is utilised in this paper as it has been shown
to more accurately predict heating effects which are of interest
in determining capacitor lifetime [15]. Resistance R3 accounts
for the relatively small resistance of the foil, tabs and terminals
while resistance R2 represents the resistance of the electrolyte.
The parallel combination of C1 and R1 account for the complex
impedance of the dielectric material and C2 is the nominal
capacitance value.
Electrolytic capacitors have a relatively high Equivalent
Series Resistance (ESR) which when coupled with ripple
current results in real power loss causing an increase in
the operational temperature. Through degradation mechanisms
inside the capacitor the increase in temperature results in an
increasing ESR until such time that the recommended value
837
C2
R2
R3
:
f(Hz)
Icap1
10.0
(100.0, 12.018)
0.0
200.0
400.0
600.0
800.0
1.0k
1.2k
1.4k
1.6k
1.8k
2.0k
2.2k
2.4k
2.6k
f(Hz)
Current (A)
R1
Magnitude (A)
(50.0, 8.8718)
0.0
Electrolyte Resistance
Voltage (V)
C1
20.0
Dielectric Resistance
Resistance of Terminals
Current (A)
50.0
:
t(s)
Voltage (V) :
t(s)
Icap1
0.0
-50.0
Vdc1
100.0
50.0
Current (A)
0.0
Current (A)
Dielectric Loss
Capacitance
Magnitude (A)
Capacitance
50.0
:
t(s)
Ia
0.0
-50.0
0.1
0.11
0.12
0.13
0.14
0.15
0.16
0.17
0.18
0.19
0.2
t(s)
is exceeded which signifies that the capacitor is at the end of
its lifetime [15].
Increases in capacitor lifetime will occur when the real
power loss due to ESR is minimised. The ESR of an electrolytic capacitor is frequency dependent as shown in (3).
Np
2
· ESR (ωn )
∑ Icap,n
Magnitude (A)
(100.0, 4.0809)
(4)
n=0
where N p is the largest multiple of the chosen frequency
interval at which to calculate the harmonics, this analysis
:
f(Hz)
Icap1
(200.0, 2.4283)
(1700.0, 1.4262)
0.0
where R2b is the base resistance of the electrolyte measured
at temperature Tb , Tc is the core temperature of the capacitor
and E is a constant defining the sensitivity of the resistance
to changes in temperature.
From (3) it is obvious that the resistance is highest at low
frequencies which means if the current ripple that the capacitors are subject to contains higher frequency components, the
ESR and hence power loss is less than when the capacitor is
subject to currents with lower frequency components.
Fig. 8 shows the resulting form of the capacitor current
when utilising the explicit vector representation while the
H-StatCom is absorbing 6.7kvar inductive. The associated
Fourier spectrum of the capacitor current is also shown. It can
be seen that the majority of the ripple current is in the lower
end of the spectrum with the largest components at 50Hz and
100Hz.
Fig. 9 shows the resulting form of the capacitor current
when utilising the implicit vector representation for the same
operational condition. The associated Fourier spectrum of
the capacitor current is also shown. It can be seen that by
switching the H-bridges to maintain a tighter control over the
capacitor voltage ripple a significant proportion of the ripple
current is moved to the higher end of the spectrum with a
corresponding decrease at 50Hz and 100Hz.
Equation (4) can be evaluated to determine the power loss
which the two SVM schemes would dissipate in a typical
electrolytic capacitor.
Ploss =
6.0
4.0
2.0
0.0
200.0 400.0 600.0 800.0
1.0k
(3)
1.2k
1.4k
1.6k
1.8k
2.0k
2.2k
2.4k
2.6k
2.8k
3.0k
f(Hz)
Current (A)
Tb −Tc
R1
E
+
R
e
+ R3
2b
2
2
1 + ω 2C1 R1
Voltage (V)
ESR =
Figure 8. Simulation waveforms for phase ’a’ when utilising the explicit
vector representation SVM scheme - Top plot: Fourier spectrum of capacitor
current, Middle upper plot: Capacitor current, Middle lower plot: Capacitor
voltage, Bottom plot: H-StatCom current
Magnitude (A)
Model of the electrolytic capacitor
Current (A)
Figure 7.
Current (A)
20.0
:
t(s)
Voltage (V) :
t(s)
Icap1
0.0
−20.0
Vdc1
70.0
60.0
50.0
40.0
Current (A)
50.0
:
t(s)
Ia
0.0
−50.0
0.58
0.6
0.62
0.64
0.66
0.68
0.7
t(s)
Figure 9. Simulation waveforms for phase ’a’ when utilising the implicit
vector representation SVM scheme - Top plot: Fourier spectrum of capacitor
current, Middle upper plot: Capacitor current, Middle lower plot: Capacitor
voltage Bottom plot: H-StatCom current
considers a frequency interval of 5Hz up to 2kHz (twice the
switching frequency), therefore N p = 400.
The parameters of the electrolytic capacitor considered in
this analysis are shown in Table I. This capacitor was chosen
as it is suitable for operation in typical converter applications
at the voltage ratings considered in the simulations, based on
size and cost requirements.
Evaluating (4) for the operational conditions depicted in
Figs. 8 and 9 shows that there is an approximately 300%
increase in the ESR power loss when utilising the explicit
SVM scheme, compared to when the implicit scheme is
employed. This is a direct result of the current ripple having
more significant low frequency components in the explicit
scheme.
Equation (5) defines the relationship between the power
dissipated due to ESR in an electrolytic capacitor and the
operating temperature.
838
Parameter
R1
R2b
R3
E
C1
C2
Value
71mΩ
8.0mΩ
22.9mΩ
16.1◦ K −1
11.4mF
2200µF
shown to come at a cost. The cost being the possible degradation of the current tracking performance and the resultant
capacitor voltage ripple and its affect on capacitor lifetime.
The performance increase gained when utilising the explicit
rather than implicit scheme, in terms of harmonic performance
and switching loss, has been quantified. The dependency of
capacitor lifetime for varying capacitor model parameters has
also been investigated.
Table I
E LECTROLYTIC C APACITOR PARAMETERS
4T = Ploss Rth = Tc − TA
R EFERENCES
(5)
where TA is the ambient temperature and Rth is the thermal
resistance between the case and surrounding air. The thermal
resistance is dependent on the surface area of the capacitor
and the type of cooling within the installation.
For electrolytic capacitors a reasonable value for the thermal
resistance is 1◦C/W [16]. The increase in power dissipation
with the use of the explicit SVM scheme is approximately
9W , therefore it is reasonable to assume a 9◦C increase in the
operating temperature of the capacitor. An industry standard
rule of thumb for electrolytic capacitors is that increasing
the operating temperature by 10◦C halves the lifetime [17].
Therefore it is obvious that the form of the capacitor voltage
ripple seen in the explicit SVM scheme has significant effects
on the lifetime of the H-bridge capacitors.
The magnitude of the power loss due to ESR is highly
dependent on the particular capacitors utilised in the H-bridge
modules. From the model of the electrolytic capacitor it is obvious that for very low frequencies the majority of the capacitor current will flow through the dielectric resistance. While
high frequency currents will flow predominantly through the
dielectric capacitance. The associated cut-off frequency for this
parallel combination of passive components is shown in (6).
1
(6)
2πR1C1
If the cut-off frequency occurs between approximately
200Hz − 400Hz (as is the case for the considered capacitor
model) then from the spectrums of the capacitor currents
shown in Fig.s 8 and 9 it is clear that the majority of the current
in the explicit SVM scheme will flow through resistance R1 .
While in the implicit scheme the majority of the current will
flow through capacitance C1 . This of course will result in a
large differential power loss due to ESR between the two
schemes. This highlights the importance of considering the
type of capacitors used in construction of the H-StatCom and
will often mean that higher quality more expensive capacitors
are required when utilising the explicit SVM scheme, if the
same lifetime is to be achieved.
fc =
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This paper presents simulation results demonstrating the
performance of two SVM schemes applied to H-StatComs.
The SVM scheme that uses an explicit vector representation
has an excellent harmonic performance trade-off with the
switching losses. However this performance gain has been
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