Lab 1
EECE473 Computer Organization & Architecture
University of Maine
Lab 1: Combinational Logic Design and Timing in Altera Quartus
Instructor: Yifeng Zhu
Objectives:
1. Get familiar with Quartus II design environment;
2. Implement and verify a 1-bit adder (also called a full adder);
3. Use the full adder as a component to implement and verify the design of a 4-bit ripple-carry adder and
4-bit carry-save adder;
4. Compare the relative timing of the ripple-carry adder vs. the carry-save adder when many numbers are
to be added together.
What to hand in:
1. The report attached at the end of this handout;
2. Your implementation source files. Submit your homework through the homework submission website.
(Please do not email the source files to TA or Me.)
1. Introduction
In the term project arranged later in this semester, we will implement a MIPS-like processor from the scratch.
This homework serves as a warm-up process that makes you familiar with the software design environment and
the basic combinational logic design. Specifically, in this homework, you will implement multi-bit adders that
are fundamental logic components in the ALU design.
Firstly, you need construct a 1-bit full adder first, and then implement an n-bit ripple-carry adder from full
adders, and finally uses full adders to build a carry-save adder that is typically faster than the ripple-carry adder
when many numbers are added together. Using the time analysis tool provided in Quartus II, you are required to
compare the relative performance of these two types of adders.
2. Background
1-bit adder: A 1-bit adder, as shown in the following figure, must have three inputs: two operands, and one
CarrayIn from the neighbor adder. There must be two outputs: a single-bit output for the sum and another
single-bit output to pass on the carry, called CarryOut.
Figure 1. 1-bit adder
The truth table of a single-bit adder is given bellows.

The author (Yifeng Zhu) gratefully acknowledges borrowing parts of this homework assignment from “UNL CSE 230
Computer Organization,” ©2005 by Dr. Sharad Seth.
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
This truth table can be summarized by two logical equations
Sum  a  b  CarryIn
CarryOut  a  b  CarryIn  a  CarryIn  b
Multiple-bit ripple-carry adder. It is created by directly linking the carries of 1-bit adders, in which CarryOut
of the less significant bit is connected to the CarryIn of the more significant bit. The following figure shows an
example of a 4-bit ripple-carry adder that adds four 4-bit numbers: A, B, E, and F.
Figure 2. A 4-bit ripple-carry adder for four 4-bit numbers
Multiple-bit carry-save adder. It consists of multiple one-bit full adders, without any carry-chaining. Thus it
can prevent time-consuming carry propagation and speed up computation. The following figure presents an
example of a 4-bit carry-save adder that adds four 4-bit numbers: A, B, E, and F.
Figure 3. A 4-bit carry-save adder for four 4-bit numbers
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
3. Implementation
1. Implement a 1-bit full adder
Figure 4. Implementation of a 1-bit full adder
(a) Draw the schematic of a single bit full adder, shown above in Quartus II.
(b) Compile the design and verify the correctness with simulation.
(c) Create a default symbol for the single bit full adder. To create the default symbol, after compiling your
design, select File from the main menu then select create/update, create symbol file for current file. A
symbol will show in your current directory.
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
2. Implement a 4-bit ripple carry adder
Figure 5. A 4-bit ripple-carry adder, where fa is short for “full adder”
(a) Draw the schematic shown above of the 4-bit ripple carry adder with Quartus II. You need to use the full
adder symbol created in problem 1. (You need to create a symbol file for the full adder that you have
implemented previously (File → create/update → create symbol file for current file). Then, when you
execute add symbol, you will find, in addition to the primitive symbols we already know, there is also
the symbol you created! You could use it just like an ordinary symbol in your schematic.)
(b) Set appropriate value to a[3..0] and b[3..0] as well as cin to verify the design with simulation. (Hint:
You do not need to exhaust all possible input combinations in truth table. But please use at least 5
combinations to verify your design.)
(c) Create a default symbol for the 4-bit ripple carry adder.
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
3. Implement a ripple-carry adder for four 4-bit numbers
Figure 6. Implementation of a 4-bit ripple-carry adder for four 4-bit numbers
(a) Draw the schematic of the ripple carry addition of four 4-bit numbers with Quartus II. You need to use
the full adder symbol and the 4-bit ripple carry adder symbol created previously.
(b) Compile the design.
(c) Choose the following set of values for a, b, e, f to verify the design with simulation.





15 + 15 + 14 + 5 = 49
15 + 11+ 9 + 15 = 50
15 + 15 + 15 + 15 = 60
7 + 9 + 2 + 15 = 33
13 + 11+ 9 +7 = 40
Timing analysis
Assume the propagation delay of the AND/OR gate is 1 time unit, the propagation delay of the XOR is 2 time
units, ignore the delays in the wires and connections and answer the following questions.
(a) What is the delay in a full adder in Figure 3?
(b) What is the delay in a 4-bit ripple carry adder in Figure 4?
(c) What is the delay in the ripple carry addition of four 4-bit numbers in Figure 5?
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
4. Implement a 4-bit carry-save adder
Figure 7. Implementation of a 4-bit carry-save adder
(a) Draw the schematic of a 4-bit carry-save adder in Quartus II. You need to use the full adder symbol
created previously.
(b) Compile the design.
(c) Create a symbol for the 4-bit carry –save adder
(d) Choose the following set of values for a, b, e, f to verify the design with simulation.
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
5. Implement a 4-bit carry-save adder for four 4-bit numbers
(a) Implement a carry-save adder of four 4-bit numbers by using the 4-bit carry-save adder, 4-bit ripplecarry adder, and/or the full adder that you have implemented previously.
(b) Compile the design.
(c) Choose the following set of values for a, b, e, f to verify the design with simulation.





10 + 15 + 14 + 5 = 39
15 + 10+ 9 + 15 = 49
15 + 15 + 14 + 15 = 59
7 + 9 + 3 + 15 = 34
13 + 12+ 9 +7 = 41
Timing analysis
Assume the propagation delay of the AND/OR gate is 1 time unit, the propagation delay of the XOR is 2 time
units, ignore the delays in the wires and connections and answer the following questions.
(d) What is the delay in a 4-bit carry-save adder in Figure 6?
(e) What is the delay in the carry-save adder of four 4-bit numbers?
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
Appendix 1: Installation of Quartus II
(The following instructions are copied from the website of atlera.com.)
1. Download the free Quartus II web edition software from Altera’s website ( www.altera.com/download )
2. Be aware that the install file is large (2.7GB for Windows and 3.3GB for Linux).
Appendix 2: Tips on Simulation, Waveform Editing
1.
2.
3.
4.
5.
6.
To create a new waveform window, use “File → New → University Program VWF” to create a waveform
file
To insert a node (a waveform), RIGHT CLICK and do Insert Node. If your waveform editor file is named
the same as the graphic file, then you can use the 'List' button to list all available nodes and choose one.
To change the value of portion of the waveform, click and drag on the portion of the waveform to change then click on either the '1' or '0' button along the left hand side to change this portion to a 1 or 0.
To set the END TIME of the simulation waveform, make sure the waveform window is selected, and then
use Edit → End Time to set the ending time.
To insert a clock waveform, select the signal, RIGHT CLICK, choose value and then clock.
Output signals like DOUT do not have to be edited by you. But you must add these nodes into the
waveform window to monitor the output. Their values will be updated when you run the simulator.
Appendix 3: Tutorial of Creating a Busline in Quartus II
In this tutorial, we illustrate how to create a busline for the component 8dffe (8-bit D-Flip-flop).
Step 1: Create a new project.

Select the device EP2C35F672C6 (DE2) in the Cyclone II family.
Step 2: Create Block Diagram


Follow menu: File → New → Select “Block Diagram/Schematic File”
Insert two components: 8dffe and input
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Lab 1
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EECE473 Computer Organization & Architecture
University of Maine
Rename an Input
o Method 1: Double click on “pin_name” and rename it to “myinput[7..0]”, or
o Method 2: Right-click the input component, and then rename it in the following pop
window.
Notice, we name the bus myinput[7..0]. This means it is an 8 bit bus where the least significant bit is bit
0. Make sure you use this convention with every component. Failure to do so can cause a lot of
headaches.
 Create a Busline: Extend a Busline from the INPUT by using Orthogonal Bus Tool
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine

Connect the busline with 8dffe

Rename Each Line: Right-click to name the bus lines, select Properties to change/add the name.
The line myinput[0] is the least significant bit.
Tips:
1. We don't need wires connecting everything if they have the same name.
2. We can concatenate two bus lines to form a new one. For example, a busline named as
A[7..3],B[2..0] will form a new bus line that takes the most significant five bits of Bus A and
the least significant three bits of Bus B to four a new 8-bit bus.
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Lab 1
EECE473 Computer Organization & Architecture
University of Maine
Report of Lab 1
Combinational Logic Design and Timing
Name: ______________________________
Demo of design to TA (40 points)
Time analysis of ripple-carry adders and carry-save adders (10 points)
Assume the propagation delay of the AND/OR gate is 1 time unit, the propagation delay of the XOR is 2 time
units, ignore the delays in the wires and connections and answer the following questions.
1. What is the delay in a full adder in Figure 4?
2. What is the delay in a 4-bit ripple carry adder in Figure 5?
3. What is the delay in the ripple carry addition of four 4-bit numbers in Figure 6?
4. What is the delay in a 4-bit carry-save adder in Figure 7?
5. What is the delay in the carry-save adder of four 4-bit numbers?
You need to submit both soft copy of your design and electronic files of your lab: Create a file
named readme.txt, which includes your name. Then compress your source code into a zipped file named
Lastname-Lab1.zip and handed it through the department handin website: http://web.eece.maine.edu/hw/
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