Lab 3 :-8 bit adder Introduction In computers very wide,, 32 bit or 64 bit, adders form part of the in the Arithmetic Logic Unit (ALU) where other arithmetic and logical operations are performed. In this laboratory, we will use the ISE tools to design, simulate and synthesise an eight bit Ripple Carry Adder. In addition, we will use hierarchy, that is, we will use components already written in order to reduce the design effort. PRE-LAB READING In advance of this lab, please read RealDigital module 7. Procedure Please fill in the report as you go, answering the questions in blue. When asked to paste screenshots, please put them at the end of the report. Using ISE Project Manager generate a new project called Byte_Add in the junk directory. Target a Xilinx Spartan 3E and leave all properties at default values. In your Project Summary, make sure you have the following values. Page 1 Lab 3 :-8 bit adder Project summary Create a VHDL file called XSE.vhd which will hold a library of components for use in this, and other, designs, including a Full Adder. We will use 8 copies, known as instances, of the Full Adder as the basis for building the Byte Adder. Put the code for the XSE file at the bottom of this sheet into the XSE.vhd file. Next, create a library in the project called XSE and move the XSE.vhd to the library by right clicking on the file in the Libraries tab and moving it to the XSE library. You should see this in your ISE environment. Project library structure Now create a top level VHDL Module, ByteAdd.vhd, describing the 8 bit adder using the Fulladder module from the XSE library. Put the code for the file at the bottom of this sheet into the ByteAdd.vhd file. A few points on the ByteAdd.vhd:The USE xse.adder.all statement gives file access to all of the components of the Adder package of the XSE library. The ByteAdd module uses a FOR loop to iteratively instantiate 8 copies of the FullAdd module. The GENERATE and END GENERATE statements surround the instantiation. The loop counter, i, indexes the input and output arrays as the loop proceeds. For example, the first time through the loop the inputs to the FullAdd module are a(0), b(0) and c(0) – which is connected to the carry input on the line c(0)<=cin; The modules sum and carry outputs are connected to sum(0) and c(1) respectively. The c(1) element connects the carry output from the first adder bit to the carry input of the next adder bit on the next loop iteration. Page 2 Lab 3 :-8 bit adder Right click on ByteAdd and set it as Top Module. Synthesise the design. View the RTL schematic after choosing all the signals, primitives etc before creating the schematic. It should be similar to that shown below. Take a screenshot of your RTL schematic and paste it to the end of your report Double Click on the Fulladd block and you should get the block below it. Note the combinational logic necessary to generate the carry out signal for each Full Adder stage. SAMPLE RTL view SAMPLE RTL View Drill down Right click to highlight the box and then choose New Schematic with Selected Objects. You should get a view of the chain of 8 full adders required to build this 8 bit adder, together with the circuitry required to combine them. Have a close look at this. Note how the carry input at the top of the diagram feeds into the first full adder. The carry_ out from here is the carry_ in of the next stage. In this way, the carry ripples through the circuit. Page 3 Lab 3 :-8 bit adder SAMPLE RTL schematic of Adder chain implementing 8 bit RCA Generate the Technology View of the circuit. You should get something like the one shown below Page 4 Lab 3 :-8 bit adder SAMPLE Technology view Take a screenshot of your Technology View and paste it to the end of your report Note the area of combinational logic here to generate the carry (black oval). Note the area of combinational logic here to generate the sum. All of the combinational logic is implemented in the LUTs of the FPGA. Create a testbench called ByteAdd_tb and add it to the project. Place the (minimal) testbench code below into the file ByteAdd_tb. Associate the testbench with ByteAdd. Simulate the circuit with the testbench supplied. You should get something like this.... SAMPLE Simulation results from 8 bit adder Page 5 Lab 3 :-8 bit adder The testbench does the following arithmetic. Obviously, a real testbench would test the device a lot more exhaustively. a b cin 00000000 00000100 11111111 00000000 00001100 00000000 0 0 1 Expected Sum (a+b) 00000000 00010000 00000000 Expected Cout 0 0 1 Correct? Verify that the answers are correct from the waveforms and tick the boxes if they are. Add at least 3 other stimulus vectors to the testbench, in other words, get the device to perform 3 more calculations by modifying the testbench and insert the simulation results into your report. Look at the Synthesis report What is the synthesis goal, maximum speed or minimum area? Fill in Table 1. Name of Slices No of 4 input LUTs No of I/Os Table 1, Resources used Write one comment on the lab here. How could it be improved? Attachments for Report RTL view Technology view Modified Simulation waveforms Page 6 Lab 3 :-8 bit adder CODE LISTINGS ByteAdd.vhd file -- 8-bit Adder LIBRARY IEEE,xse; USE IEEE.std_logic_1164.all; USE xse.adder.all; library -- use the adder-bit module from the XSE -- byte-wide adder interface description ENTITY byteadd is PORT ( a: IN STD_LOGIC_VECTOR (7 DOWNTO 0); b: IN STD_LOGIC_VECTOR (7 DOWNTO 0); cin: IN STD_LOGIC; input bit sum: OUT STD_LOGIC_VECTOR (7 DOWNTO 0); cout: OUT STD_LOGIC output bit ); END byteadd; -- addend byte -- addend byte -- carry -- sum byte -- carry -- 8-bit adder architecture (generated structural) ARCHITECTURE byteadd_arch OF byteadd IS -- declare a local array of signals to transfer carry bits between adder stages SIGNAL c: STD_LOGIC_VECTOR (8 DOWNTO 0); BEGIN c(0)<=cin; -- initialize first carry signal to carry input value -- for-loop will generate 8 full-adder bits and hook them together lbl0: FOR i IN 0 TO 7 GENERATE lbl1: fulladd PORT MAP ( -- connect the I/O of the adder bit to I/O of the 8-bit adder input0=>a(i), -- addend inputs connected to i'th bit of the input1=>b(i), -a and b addend input arrays carry_input=>c(i), -- carry input connects to the i'th carry signal sum=>sum(i), -- sum bit connects to the i'th bit of the sum output array Page 7 Lab 3 :-8 bit adder carry_output=>c(i+1) -- carry output from this stage becomes the ); -input to the next stage of the adder END GENERATE; cout<=c(8); -- output carry comes from the last bit of the carry array END byteadd_arch; ByteAdd testbench file -- VHDL Test 05/09/2006 Bench Created from source file byteadd.vhd -- 10:37:42 --- Notes: -- This testbench has been automatically generated using types std_logic and -- std_logic_vector recommends for the ports of the unit under test. Xilinx -- that these types always be used for the top-level I/O of a design in order -- to guarantee implementation that the testbench will bind correctly to the post- -- simulation model. -LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY byteadd_Byte_Add_tb_vhd_tb IS END byteadd_Byte_Add_tb_vhd_tb; ARCHITECTURE behavior OF byteadd_Byte_Add_tb_vhd_tb IS COMPONENT byteadd PORT( a : IN std_logic_vector(7 downto 0); Page 8 Lab 3 :-8 bit adder b : IN std_logic_vector(7 downto 0); cin : IN std_logic; sum : OUT std_logic_vector(7 downto 0); cout : OUT std_logic ); END COMPONENT; SIGNAL a : std_logic_vector(7 downto 0); SIGNAL b : std_logic_vector(7 downto 0); SIGNAL cin : std_logic; SIGNAL sum : std_logic_vector(7 downto 0); SIGNAL cout : std_logic; BEGIN uut: byteadd PORT MAP( a => a, b => b, cin => cin, sum => sum, cout => cout ); -- *** Test Bench - User Defined Section *** tb : PROCESS BEGIN a<="00000000"; b <="00000000"; cin<= '0'; Page 9 Lab 3 :-8 bit adder wait for 10 ns; a<="00000100"; b <="00001100"; cin<= '0'; wait for 10 ns; a<="11111111"; b <="00000000"; cin<= '1'; -- check carry OK wait for 10 ns; wait; -- will wait forever END PROCESS; -- *** End Test Bench - User Defined Section *** END; XSE file for XSE library -- Xilinx Student Edition Library -- Contains some components used in design examples. -- package declaration for components used in the parity generator example LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE evpar IS -- 2-bit parity generator component declaration COMPONENT evpar2 PORT ( b0,b1: IN STD_LOGIC; par: OUT STD_LOGIC ); END COMPONENT; -- 4-bit parity generator component declaration Page 10 Lab 3 :-8 bit adder COMPONENT evpar4 PORT ( b0,b1,b2,b3: IN STD_LOGIC; par: OUT STD_LOGIC ); END COMPONENT; END evpar; -- interface and architecture definitions for the parity generator components follow LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY evpar2 IS PORT ( b0,b1: IN STD_LOGIC; par: OUT STD_LOGIC ); END evpar2; ARCHITECTURE evpar2_arch OF evpar2 IS BEGIN par <= b0 XOR b1; END evpar2_arch; LIBRARY IEEE,XSE; USE IEEE.std_logic_1164.all; USE XSE.evpar.all; ENTITY evpar4 IS PORT ( b0,b1,b2,b3: IN STD_LOGIC; par: OUT STD_LOGIC ); END evpar4; ARCHITECTURE evpar4_arch OF evpar4 IS SIGNAL tmp: STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN par0: evpar2 PORT MAP(b0=>b0,b1=>b1,par=>tmp(0)); par1: evpar2 PORT MAP(b0=>b2,b1=>b3,par=>tmp(1)); top: evpar2 PORT MAP(b0=>tmp(0),b1=>tmp(1),par=>par); END evpar4_arch; -- package declaration for 1-bit full-adder component LIBRARY IEEE; USE IEEE.std_logic_1164.all; PACKAGE adder IS COMPONENT fulladd PORT ( input0: IN STD_LOGIC; input1: IN STD_LOGIC; carry_input: IN STD_LOGIC; sum: OUT STD_LOGIC; carry_output: OUT STD_LOGIC ); Page 11 Lab 3 :-8 bit adder END COMPONENT; END adder; -- interface and architecture definitions for the 1-bit full-adder component follows LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY fulladd IS PORT ( input0: IN STD_LOGIC; input1: IN STD_LOGIC; carry_input: IN STD_LOGIC; sum: OUT STD_LOGIC; carry_output: OUT STD_LOGIC ); END fulladd; ARCHITECTURE fulladd_arch OF fulladd IS SIGNAL tmp: std_logic_vector(1 TO 4); BEGIN sum <= input0 xor input1 xor carry_input; carry_output <= (input0 and input1) or (input0 and carry_input) or (input1 and carry_input); END fulladd_arch; -- package declaration for 7-segment LED decoder component LIBRARY ieee; USE ieee.std_logic_1164.all; PACKAGE led IS COMPONENT leddcd PORT ( d : IN STD_LOGIC_VECTOR (3 DOWNTO 0); s : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) drive LED dISplay ); END COMPONENT; END led; -- 4-bit input -- 7 outputs to -- interface and architecture definitions for the LED decoder component follows LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY leddcd IS PORT( d : IN STD_LOGIC_VECTOR (3 DOWNTO 0); s : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) dISplay ); END leddcd; -- 4-bit input -- 7 outputs to drive LED ARCHITECTURE leddcd_arch OF leddcd IS BEGIN WITH d SELECT s <= "1110111" WHEN "0000", Page 12 Lab 3 :-8 bit adder "0010010" "1011101" "1011011" "0111010" "1101011" "1101111" "1010010" "1111111" "1111011" "1111110" "0101111" "1100101" "0011111" "1101101" "1101100" "0000000" END leddcd_arch; WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN WHEN "0001", "0010", "0011", "0100", "0101", "0110", "0111", "1000", "1001", "1010", "1011", "1100", "1101", "1110", "1111", others; Page 13