ISSN: 2393-994X
KARPAGAM JOURNAL OF ENGINEERING RESEARCH (KJER)
Volume No.: II, Special Issue on IEEE Sponsored International Conference on Intelligent Systems and Control (ISCO’15)
Design of Area Efficient Ripple Carry Adders using
Majority Gates in QCA
C.Udhaya Kumar1, M.Ishwarya Niranjana2
1
Assistant Professor, udhayakumar.c@gmail.com, Sri Eshwar College of Engineering, India
1
Pg Student, ishu.niranjana@gmail.com, Sri Eshwar College of Engineering, India
Abstract
As transistors decrease in size more and more of them can be accommodated in a single die, thus
increasing chip computational capabilities. However, transistors cannot get much smaller than their
current size. The Quantum-dot Cellular Automata (QCA) approach represents one of the possible
solutions in overcoming this physical limit. In the existing method, a Quantum-dot Cellular Automata
adder is designed using three input Majority Gate (MG). This Ripple Carry adder (64-bit) spans over a
complexity of 16667 (cell count) covering 18.72 μm2 of active area and shows a delay of 9 clock cycles,
that is 36 clock phases. In proposed method the same 3-input Majority logic gate method for constructing
QCA is applied. But in the modified adder (64-bit) layout design outperforms all state-of-the art
competitors and reduces area-delay efficiently than previous designs. The modified QCA Ripple Carry
adder designed spans over a complexity of 15939 (cell count) covering 15.32 μm2 of active area and
shows a delay of only 81/4 clock cycles, that is just 33 clock phases. Here the cell count is reduced by 7%
when compared to existing design.
Keywords - Adders, Quantum-dot Cellular Automata (QCA), Majority Gates (MG).
1. Introduction
Quantum-dot Cellular Automata (QCA) is an efficient technology to create computing devices. QCA is a
suitable candidate for the next generation of digital systems. A quantum-dot cellular automaton (QCA) is a new
nanotechnology that can help us to reach low-power consumption, high device density, and high clock frequency.
QCA size is smaller than CMOS it can, even be implemented in molecule or atom size. QCA power consumption is
extremely lower than CMOS because there are not any current in the circuit and output capacity. In recent years
CMOS technology demonstrated that it can be readily challenged by other technologies when it arrives at nanoregimes. Due to serious CMOS technology restrictions in nano-scales, researchers have investigated alternative
technologies [2]. As the electronic CMOS transistor technology for information processing approaches its limits,
new possibilities for the implementation of digital information processing are being explored. Among those raising
greatest interest are Quantum Cellular Automata (QCA). QCA are matrixes of cells, in which information is stored
as the position of couples of electrons bound within cell borders. Neighbour cells interact by means of electric
Columbian repulsion, and cell state can be frozen at will by controlling a potential barrier rising signal (clock).
Quantum Cellular Automata (QCA) refers to models of quantum computation, which have been devised in analogy
to conventional models of cellular automata introduced by von Neumann. It may also refer to quantum dot cellular
automata, which is a proposed physical implementation of "classical" cellular automata by exploiting quantum
mechanical phenomena. QCA has attracted a lot of attention as a result of its extremely small feature size (at the
molecular or even atomic scale) and its ultra-low power consumption, making it one candidate for
replacing CMOS technology.
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1.1 Quantum Cellular Automata (QCA)
Quantum (-dot) Cellular Automata are based on the simple interaction rules between cells placed on a grid. A
QCA cell is constructed from four quantum dots arranged in a square pattern. These quantum dots are sites electrons
can occupy by tunneling to them.
Fig.1 A simplified diagram of a four-dot QCA cell.
Fig.2 The two possible states of a four-dot QCA cell.
Fig.1 shows a simplified diagram of a quantum-dot cell. If the cell is charged with two electrons, each free to
tunnel to any site in the cell, these electrons will try to occupy the furthest possible site with respect to each other
due to mutual electrostatic repulsion. Therefore, two distinguishable cell states exist.Fig.2 shows the two possible
minimum energy states of a quantum-dot cell. The state of a cell is called its polarization, denoted as P. Although
arbitrarily chosen, using cell polarization P = -1 to represent logic “0” and P = +1 to represent logic “1” has become
standard practice [2].
Grid arrangements of quantum-dot cells behave in ways that allow for computation. The simplest practical cell
arrangement is given by placing quantum-dot cells in series, to the side of each other. Figure 4 shows such an
arrangement of four quantum-dot cells. The bounding boxes in the figure do not represent physical implementation,
but are shown as means to identify individual cells. If the polarization of any of the cells in the arrangement shown
in Fig.3 were to be changed (by a "driver cell"), the rest of the cells would immediately synchronize to the new
polarization due to Columbic interactions between them. In this way, a "wire" of quantum-dot cells can be made that
transmits polarization state. Configurations of such wires can form a complete set of logic gates for computation.
(a) QCA wire (90°)
(b) QCA wire (45°)
Fig.3 A wire of quantum-dot cells
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2. QCA Basics
2.1 Majority Gates
Fig.4 - QCA Majority Gate Perhaps the most important logic gate in QCA is the majority gate. Fig.4 shows a
majority gate with three inputs and one output. In this structure, the electrical field effect of each input on the output
is identical and additive, with the result that whichever input state ("binary 0" or "binary 1") is in the majority
becomes the state of the output cell — hence the gate's name. For example, if inputs A and B exist in a “binary 0”
state and input C exists in a “binary 1” state, the output will exist in a “binary 0” state since the combined electrical
field effect of inputs A and B together is greater than that of input C alone [3].
Fig.4 QCA Majority Gate
When one input C is fixed as logic “0” then it act as AND gate and if C is logic “1” then it act as OR gate. The
majority gate performs a three-input logic function. Assuming the inputs is A, B and C, the logic function of the
majority gate is given as in (1)
M (A, B, C) = A.B + B .C + A.C
(1)
By fixing the polarization of one input to the QCA majority gate as logic “1” or logic “0,” an AND gate or OR
gate will be obtained.
M(A,B,0) = AB
(2)
M(A,B,1) = A+B
(3)
2.2 Other Gates
Other types of gates, namely AND gates and OR gates, can be constructed using a majority gate with fixed
polarization on one of its inputs. A NOT gate, on the other hand, is fundamentally different from the majority gate,
as shown in Fig.5. The key to this design is that the input is split and both resulting inputs impinge obliquely on the
output. In contrast with an orthogonal placement, the electric field effect of this input structure forces a reversal of
polarization in the output.
Fig.5 Standard Implementation of a NOT gate.
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2.3 State Transition
There is a connection between quantum-dot cells and cellular automata. Cells can only be in one of 2 states and
the conditional change of state in a cell is dictated by the state of its adjacent neighbors. However, a method to
control data flow is necessary to define the direction in which state transition occurs in QCA cells. The clocks of a
QCA system serve two purposes: powering the automaton, and controlling data flow direction. QCA clocks are
areas of conductive material under the automaton’s lattice, modulating the electron tunneling barriers in the QCA
cells above it.
2.3 Four Stages
A QCA clock induces four stages in the tunneling barriers of the cells above it. In the first stage, the tunneling
barriers start to rise. The second stage is reached when the tunneling barriers are high enough to prevent electrons
from tunneling. The third stage occurs when the high barrier starts to lower. And finally, in the fourth stage, the
tunneling barriers allow electrons to freely tunnel again. In simple words, when the clock signal is high, electrons
are free to tunnel. When the clock signal is low, the cell becomes latched.Fig.6 shows a clock signal with its four
stages and the effects on a cell at each clock stage. A typical QCA design requires four clocks, each of which is
cyclically 90 degrees out of phase with the prior clock. If a horizontal wire consisted of say, 8 cells and each
consecutive pair, starting from the left were to be connected to each consecutive clock, data would naturally flow
from left to right. The first pair of cells will stay latched until the second pair of cells gets latched and so forth. In
this way, data flow direction is controllable through clock zones.
Fig.6 The QCA clock, its stages and its effects on a cell’s energy barriers.
2.4 WIRE CROSSING
Wire-crossing in QCA cells can be done by using two different quantum dot orientations (one at 45 degrees to
the other) and allowing a wire composed of one type to pass perpendicularly "through" a wire of the other type, as
shown schematically in Fig.7.
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Fig.7 Basic Wire-Crossing Technique.
The distances between dots in both types of cells are exactly the same, producing the same Columbic
interactions between the electrons in each cell. Wires composed of these two cell types, however, are different: one
type propagates polarization without change; the other reverses polarization from one adjacent cell to the next. The
interaction between the different wire types at the point of crossing produces no net polarization change in either
wire, thereby allowing the signals on both wires to be preserved.
2.5 Crossbar Network
A different wire-crossing technique, which makes fabrication of QCA devices more practical, was presented
by Christopher Graunke, David Wheeler, Douglas Tougaw, and Jeffrey D. Will, in their paper “Implementation of a
crossbar network using quantum-dot cellular automata”. The paper not only presents a new method of implementing
wire-crossings, but it also gives a new perspective on QCA clocking. Their wire-crossing technique introduces the
concept of implementing QCA devices capable of performing computation as a function of synchronization. This
implies the ability to modify the device’s function through the clocking system without making any physical
changes to the device.
Thus, the fabrication problem stated earlier is fully addressed by: a) using only one type of quantum-dot pattern
and, b) by the ability to make a universal QCA building block of adequate complexity, which function is determined
only by its timing mechanism (i.e., its clocks).Quasi-adiabatic switching, however, requires that the tunneling
barriers of a cell be switched relatively slowly compared to the intrinsic switching speed of a QCA. This prevents
ringing and meta-stable states observed when cells are switched abruptly. Therefore, the switching speed of a QCA
is limited not by the time it takes for a cell to change polarization, but by the appropriate quasi-adiabatic switching
time of the clocks being used.
3. Existing Method
Fig.8 Full adder schematic
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The full adder based on three inputs MG is shown in Fig.8. The n-bit adder is designed using three inputs MG. To
implement ripple adders in QCA, the novel architecture is used. In novel architecture three input MG is used.
Consider ith bit stage for given n-bit addends,
X = xn−1 ,. . .. , x0 and Y= yn−1, . . . ,y0 then propagate term pi = xi + yi and generate term gi = xi . yi are
obtained. At (i-1) th bit position the first carry is generated. The conventional CLA logic given in (4) is used to
compute carry. The last mentioned can be rewritten as reported in (5) by using Theorem 1 and 2 explained in [15].
In this way the circuit operates in RCA fashion and only one MG is needed to propagates the carry to consequent bit
position. But in conventional circuits, two cascaded MGs are required to perform the same operation. In other words
the novel QCA adder has worst case path nearly half when compared to conventional QCA design.[1]
ci+2 = gi+1 + pi+1 · gi + pi+1 · pi · ci
(4)
ci+2 = M(M (ai+1, bi+1, gi ) M (ai+1, bi+1,pi )ci )
(5)
To design novel 2-bit module shown in Fig.9 the equation (5) is used and the carry Ci+1 =M ( pi gi ci ) is obtained.
Fig.9 Novel 2-bit module
The cascading of n/2 2 bit modules gives n-bit adder. Initially carry-in of the adder is considered as 0 and initial
propagate p0 term is not considered. The module used at least significant bit position is made simpler. The carry bits
are generated first and sum is generated finally by taking carries generated as input.
Fig.10 Novel 16-bit adder.
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Fig.11 Novel 64-bit adder.
Fig.12 Simulation results obtained for the novel 64-bit adder.
4. Proposed Method
There are different approaches to digital design with QCAs. Some are based on standard synthesis procedures,
that take as input the truth table of the functionality to implement and produce as output a disposition of cells in a
matrix that implement it [8]. Such procedures are based, as for the CMOS technologies, on the definition of a
universal set of “gates”. The simplest logical operator that can be realised with QCAs is the so called majority gate.
The majority gate has three boolean inputs, and produces as output the value that is most present as input. A boolean
expression representing it is: M(x; y; z) = xy + xz + yz. The majority gate, in conjunction with the negation function
is universal. Another elementary gate with QCA is the minority gate, which is the negation of the majority: m(x; y;
z) = -M(x; y; z). It can be shown that m is universal [9]. When polarization of cells A, B and C are fixed, their state
will propagate to the nearest cells. Then, the cell at the center of the cross will be subject to the Columbian
interaction with the three polarized neighbours, and its electrons will settle according to the most present
polarization value. The state will then be propagated to the output cell. On the other hand, the implementation of the
minority gate [3] , which behaviour is similar to the one of the majority gate.
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Here the design of a compact full adder module to be implemented as a QCA is proposed. It follows a logic
simplification process similar to the one presented in [5].
The expressions obtained are:
CarryOut = m(A ; B ; CarryIn)
(6)
Sum = m (m(A ; B ; CarryIn); m(A ; B ; CarryIn) ; CarryIn)
(7)
The proposed adder module is shown in Fig.14
Fig.13 Basic Module of adder.
Fig.14 Simulation results of Basic Module.
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Fig.15 4-Bit Ripple Carry Adder.
Fig.16 Simulation results of 4-Bit Ripple Carry Adder.
Fig.17 64-Bit Ripple Carry Adder.
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Fig.18 Simulation results of 64-Bit Ripple Carry Adder.
5. Performance Analysis
Table 1. Comparison results
Adder
n
Proposed
8
16
32
Cell count Size(μm2)
650
1682
4898
Delay
Clock Phases
1.05
11/4
5
2.02
21/4
9
5.12
41/4
17
33
64
15939
15.32
81/4
8
1606
1.13
2
8
16
3587
2.66
3
12
32
7691
6.65
5
20
64
16667
18.72
9
36
Fig.19 Comparison of size
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6. Conclusions and Further Works
The optimized design of Ripple Carry adder is proposed. The proposed Adder is simulated using QCA designer
tool 2.0.2 Version and is efficient in term s of cell count and area. The proposed work has shown that it is possible to
significantly reduce the number of cells required to design basic components, such as adder circuits, by utilizing
minority gates instead of majority gates. In addition to this, the proposed design presents an increased robustness
with respect to previous approaches resulting in reduction of the number of cells from 5% to 7%. The Proposed
adder spans over a complexity of 15939 (cell count) covering 15.32 μm2 of active area and shows a delay of only
81/4 clock cycles, that is just 33 clock phases.
An interesting extension of the proposed work could be the automation of the optimizations in order to make it
possible to synthesize also more complex circuits.The cell count can further be reduced by using 5,7,9 input
Majority Gates.
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