4-bit Ripple Carry Adder of Two-Phase clocked
Adiabatic Static CMOS Logic: a comparison with
static CMOS
Nazrul Anuar
Yasuhiro Takahashi
Toshikazu Sekine
Graduate School of Engineering
Gifu University, 1-1 Yanagido,
Gifu-shi, Gifu Japan 501-1193
Email: n3814101@edu.gifu-u.ac.jp
Faculty of Engineering
Gifu University, Japan 501-1193
Email: yasut@gifu-u.ac.jp
Faculty of Engineering
Gifu University, Japan 501-1193
Email: sekine@gifu-u.ac.jp
Abstract—The paper presents a new quasi energy recovery
logic family that uses two complementary split-level sinusoidal
power supply clock for digital low power applications such as
sensors. The proposed two-phase adiabatic static CMOS logic
circuit (2PASCL) is using the principle of energy recovery and
adiabatic switching. It has switching activity that is lower than
dynamic logic and can be directly derived from static CMOS
circuits. We have designed and simulated a 4-bit ripple carry
adder (RCA) using 2PASCL logic gates implemented using 0.18
µm CMOS technology. Driving pulse with the height equal to
Vdd is supplied to the gates. From the simulation result, it shows
that 2PASCL can save an average of 71.3% of energy dissipation
compared with static CMOS logic at transition frequency of 10
to 100MHz.
I. I NTRODUCTION
With the widely spread of mobile, hand-held and wireless
electronics devices, the demands for the innovations of lowpower VLSI arise. For most of the digital circuits today,
CMOS logic scheme has been the technology of choice for
implementing low-power systems. As the clock and logic
speeds increase to meet the new performance requirements, the
energy requirement of CMOS circuits are becoming a major
concern in the design of above devices.
Power dissipation in conventional CMOS primarily occurs
during device switching. When a CMOS which consists of the
pull-up (pMOS) and pull down (nMOS) networks connected
to a load capacitance CL is set into a logical “1” logic level,
an energy of Eapplied = C L Vdd 2 is applied to the load [1].
Energy stored is half of the energy supplied, therefore the total
dissipation as heat during charging and discharging, when the
logic level is “0”, is the same as Etotal = C L Vdd 2 .
Energy(dissipation
in the channel resistance R is given as
)
2
L
Ediss = RC
C
V
L dd . For adiabatic charging, when ∆T ,
∆T
which means the time for the driving voltage to change from
0 V to Vdd is long, in theory, the energy dissipation is nearly
zero. Adiabatic logic circuits also utilize AC power supplies
to recycle the energy used to charge node capacitances in
the circuit. As it dissipates less energy than the fundamental
limit of static CMOS, adiabatic circuits are promising candidates for low-power circuits in the frequency range in which
signals are digitally processed. In recent years, studies on
adiabatic computing have been utilized for low-power systems
and several adiabatic logic families have been proposed [1]–
[15]. However, several weaknesses such as complex circuits,
multiple power-clock supplies, nonadiabatic transitions that
may compromise the energy savings and the logic gates are
not well suited for CMOS implementation are seen.
In this paper, we propose a Two-Phase Adiabatic Static
CMOS Logic (2PASCL) circuit. It can be directly converted
from static CMOS circuits without drastically increasing the
circuit complexity and transistor overheads. This circuit is
emphasized on the recycle of the charges as two diodes are
placed for the discharging. The functional of ripple carry
adder based on 2PASCL is evaluated and energy dissipation
is compared with CMOS at transition frequency of 10 to 100
MHz.
II. T WO P HASE A DIABATIC S TATIC CMOS L OGIC
Figure 1 shows a circuit diagram and waveforms illustrating
the operation of the 2PASCL inverter. It resembles the static
CMOS logic inverter but operates in a nearly adiabatic fashion.
The first difference of 2PASCL compared to static CMOS
logic gate is the two diodes, one from the output node to
the power clock supply and another one is placed next to
the nMOS logic to another power clock. The pMOS and
nMOS diodes are used to recycle the charge from the output
node. The other difference is that split-level sinusoidal power
clock supplies, ϕ and ϕ are used to replace the Vdd and the
Vss . From the simulation, we found that split-level sinusoidal
gives a lower energy dissipation compared to trapezoidal
power clock supply even if we set the Trise and Tf all of the
trapezoidal waveforms to a maximum values. By using two
split-level sinusoidal waveforms which each peak-to-peak is
0.9 V, we can reduced the voltage difference, thus reducing
the charging and discharging activities. Sinusoidal waveforms
can also be generated with higher energy efficiency than
trapezoidal waveforms [15].
The operation of 2PASCL is as follows. Let us consider
the inverter logic circuit demonstrated in Fig. 1. The circuit
φ
operation phase is divided into evaluation and hold.
In evaluation phase, when the output node Y is LOW and
pMOS tree is turned ON, as ϕ swings up and ϕ swings down,
CL is charged through pMOS transistor resulting the HIGH
state at the output. When Y is LOW and nMOS is ON, no
transition occurs. The same result gained when the output
node is HIGH and pMOS is ON. When Y node is HIGH
and nMOS is ON, discharging via nMOS and D2 resulting
the output voltage decreased to Vt value before entering hold
mode where the logical state is “0” [12]. For the evaluation
mode where ϕ swings up and ϕ swings down, the detailed
operations are summarized by Table I.
ON transistor
M1
M2
M1
M2
III. S IMULATION RESULTS AND DISCUSSION
A. Condition of simulation
The paper starts by examining the functional and energy
dissipation of a simple logic gate, an inverter of 2PASCL as
shown in Fig. 1. We use SPICE simulation with a 0.18 µm -1.8
V standard CMOS process. The W/L of nMOS and pMOS
logic gates used is 0.6 µm/0.18 µm. A capacitive load CL , of
0.01 pF is placed at output node Y. Bulks of pMOS and nMOS
are connected to ϕ and ϕ accordingly. The power supply clock
frequencies are set to be 4 times higher than the transition
frequency after considering energy dissipation results. Using
split-level sinusoidal power clock driving voltage of 0.9 V
peak-to-peak each, the result at 100 MHz transition frequency
of 2PASCL inverter is shown in Fig. 1. The input signals are
CMOS-compatible rectangular pulses. The top graph shows
the split-level sinusoidal supply clock driving voltage. The
second graph demonstrates the input signal and the third graph
shows the output waveform of a correctly functioning inverter
which was simulated with the SPICE. Its energy dissipation is
calculated by integrating the voltage and current product value
as follows:
)
∫ Ts (∑
n
E=
(Vpi × Ipi ) dt,
(1)
0
i=1
φ
Ｙ
M2
CL
φ
D2
φ
1.9V
1.4V
0.9V
0.4V
-0.1V
1.9V
1.4V
0.9V
0.4V
-0.1V
Next state of Y
HIGH
LOW (no transition)
HIGH (no transition)
LOW
At hold mode where ϕ swings down and ϕ swings up, due
to the diodes, the state of Y when preliminary state is LOW
remains unchanged. When the preliminary state of the output
node is HIGH, it will change to Vt , the threshold voltage of
the diode. At this point, discharging via D1 occurs.
From the operation of 2PASCL, less dynamic switchings
are seen as circuit nodes are not necessarily charging and
discharging every clock cycle which reduces the node switching activities significantly. The lower the switching activity
reduces energy dissipation.
φ
X
TABLE I
O PERATION SUMMARY AT EVALUATION MODE
Prelim. state Y
LOW
LOW
HIGH
HIGH
D1
M1
V(-phi)
φ
V(phi)
V(x)
V(y)
1.6V
1.1V
0.6V
0ns
Fig. 1.
10ns
20ns
30ns
40ns
50ns
2PASCL inverter circuit and its waveforms.
where Ts is the period of the primary input signal, Vp is the
power supply voltage, Ip is the power supply current and n is
the number of power supply [12]. The energy in joule is then
converted to watt by multiplying it with the input frequency.
TABLE II
C IRCUIT DATA FOR 2PASCL AND STATIC CMOS
Driving power voltage
Split level ϕ and ϕ
Frequency (input: driving voltage)
nMOS, pMOS (incl. diodes)
COMPARISON
0–1.8V
0–0.9V, 0.9–1.8V
1:4
W/L : 0.6µm/0.18µm
s
a
b
cin
cout
Fig. 2.
Full adder.
Then, the simulation of 2PASCL based 1-bit full adder (FA)
is carried out. As shown in Fig. 2, FA consists of exclusiveOR and NAND logic gates. Each exclusive-OR and NAND
of 2PASCL is as demonstrated in Fig. 3 and Fig. 4 respectively. To verify the applicabilities of the proposed structure
and 2PASCL property, a 4-bit ripple carry adder (RCA) has
been designed and simulated. To enhance the performance
evaluation, we simulate the frequency characteristics of power
consumption for RCA of 2PASCL and the result is compared
with CMOS. The transition frequencies simulated are from 10
to 100 MHz. The energy dissipation value is taken at the same
time period for both circuits.
φ
a
Ｙ
b
B. Results and discussion
From the simulations, we have confirmed the functional
of the 4-bit ripple carry adder 2PASCL logic circuits. The
results are shown in Fig. 5. From the results, 2PASCL with
split level sinusoidal clocking voltage gives a significant lower
energy dissipation compared with conventional static CMOS
for ripple carry adder. It also demonstrates a significant lower
energy dissipation when transition frequency is simulated from
10 to 100 MHz which is shown in Fig. 6.
φ
Fig. 4.
Schematic for NAND logic of 2PASCL.
Y
a
φ
φ
b
Fig. 3.
Schematic for exclusive-OR logic of 2PASCL.
2.0V
1.0V
0.0V
2.0V
1.0V
0.0V
2.0V
1.0V
0.0V
2.0V
1.0V
0.0V
2.0V
1.0V
0.0V
2.0V
1.0V
0.0V
0ns
V(-phi)
V(phi)
V(a)
V(b)
V(cin)
V(s)
V(cout)
180ns
360ns
540ns
720ns
900ns
Fig. 5.
Output waveforms for ripple carry adder of 2PASCL from the
simulation result.
IV. C ONCLUSION
R EFERENCES
This paper has described a simulation of Two-Phase clocked
Adiabatic Static CMOS Logic (2PASCL). By implementing
the adiabatic charging and energy recovery theory, 4-bit ripple
carry adder (RCA) of 2PASCL is compared to RCA of
static CMOS. Compared with static CMOS circuits, 2PASCL
consumes much less power. For instance, at input frequency
of 10 to 100 MHz, RCA of 2PASCL dissipates only 28.7%
of the energy of static CMOS logic in average. From the
results of other logic gates such as inverter chain [16], NAND,
exclusive-OR and FA of 2PASCL which have been simulated,
this logic scheme can be a viable candidate for ultra-low
energy computing.
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