COE 200 Lab
4 bit Ripple Carry Adder Implementation in Verilog
Objective: To implement and simulate 4-Bit Binary Ripple Carry Adder using Verilog
Background:
It is possible to make a module in Verilog and use it in other modules. A higher level
Verilog module can use lower level module. In higher level module, we can instantiate a
module defined in low level project.
Activity:
1. Following Verilog code is the structural description of a full adder (FA) circuit. Recall
a full adder circuit can be made by using two half adder circuits and one OR gate. Note
wire statement in Verilog represent simple wires in the circuits.
module fulladder(x, y, c_in, sum, c_out);
input x;
input y;
input c_in;
output sum;
output c_out;
wire a,b,c;
xor (a,x,y);
xor(sum,a,c_in);
and(b,x,y);
and (c,a,c_in);
or (c_out,c,b);
endmodule
Draw the logic diagram of FA adder circuit from the above Verilog structural description.
2. Create a new project called “fulladder”. Choose new source type as “HDL”. Define
inputs and outputs of the FA circuit.
3. Type fulladder code given above.
4. Create a test bench waveform and define test inputs for FA.
5. Simulate your design in ModelSim and verify the function of FA with different inputs.
Write your results in the table:
X
Y
Cin
Sum
Cout
6. Close project and create new project called “ripple-carry-adder”. Choose HDL as
source type.
7. In “Add source” wizard, click “add source”, and select “fulladder” project folder. Click
verilog file of fulladder
8. Define input and output of the 4 bit ripple carry adder. Note, there will be two input
vectors and one output vector. Also, there will be single carry in and carry out from 4-bit
ripple carry adder.
9. Type following code for 4 bit ripple carry adder:
module fourbitadder(x, y, c_in, sum, c_out);
input [3:0] x;
input [3:0] y;
input c_in;
output [3:0] sum;
output c_out;
wire c1,c2,c3;
fulladder fa0(x[0],y[0],c_in,sum[0],c1);
fulladder fa1(x[1],y[1],c1,sum[1],c2);
fulladder fa2(x[2],y[2],c2,sum[2],c3);
fulladder fa3(x[3],y[3],c3,sum[3],c_out);
endmodule
Note: This code instantiate 4 fulladder module fa0-fa1. Understand the inputs and
outputs. Draw logic diagram of a 4 bit ripple carry adder to understand the code
10. Define test bench for ripple carry adder. Note you can specify value of input vectors.
11. Simulate your design and verify the results with different values inputs and outputs.
Exercise : Extend code to design 8-bit Ripple carry adder.