Electrical Power Quality and Utilisation, Journal Vol. XII, No. 2, 2006
Multiresonant ZVS CUK Converter
El¿bieta SZYCHTA
Technical University of Radom, Poland
Summary: The article presents properties of multiresonant ZVS Cuk converter. The control
system of the converter is based on PWM technique. The operating range of the converter is
defined where ZVS operation is assured. Control characteristics are given and the converter’s
efficiency is defined. The converter’s operation is analysed on the basis of simulation testing.
1. INTRODUCTION
Demand for resonant circuits converting DC/DC electricity
switched at high operating frequencies is a result of attempts
at great efficiency, minimizing size, and the consequent cost
reduction of converters. Energy efficiency of high-frequency
converters depends mainly on switching processes of
semiconductor components. At turn-on and turn-off, power
losses occur which are a result of current multiplied by voltage
in switched semiconductor elements. At high operating
frequency, parasitic inductances of connections and parasitic
capacitances of transistors and diodes produce resonant
circuits which generate parasitic electromagnetic oscillations.
When the transistor is conducting, impact of rectifying diode’s
parasitic capacitance occurs, and when the reverse diode is
conducting, the transistor’s parasitic capacitance affects the
circuit operation. Topologies of multiresonant converters
(MRCs) enable application of switching technique at zero
voltage of both the transistor and the diode. Switching of
transistor and diode at zero voltage (ZVS) in MRCs allows
for obtaining high operating frequency of the circuit while
maintaining great energy efficiency and minimizing voltage
and current oscillations.
References present basic topologies of ZVS MRCs and
their characteristics [1, 3, 7, 11]. Properties of ZVS Buck MRC
are analysed in [1, 10, 11]. Results of simulation testing for
topologies of Boost and Buck-Boost ZVS MRCs are
presented in references [5, 6].
This article concentrates on ZVS Cuk MRC topology. An
analysis of the circuit’s operation is presented based on
results of simulation testing employing Simplorer software.
and capacitor at CD in parallel with diode D. Capacitances CS
and CD, in parallel with parasitic capacitances COS, COD,
build equivalent resonant capacitances of the circuit.
Inductance L comprises parasitic inductances of the circuit.
A very high quality factor of the reactor L is assumed, thus,
the impact of reactor’s resistance is ignored. The capacitor at
CF is a low-pass filter that limits ripples of output voltage. CT
is a large energy-transfer capacitor. The circuit in Figure 1,
when PWM control is employed, enables ZVS of transistor T
and diode D.
3. OPERATION OF THE CIRCUIT
In the Cuk MRC (Fig. 1), operating cycle is divided into
five time intervals. Current and voltage waveforms during a
cycle (relative units) based on simulation testing are shown
in Figure 2. Resonant circuits for five time intervals of
operation are presented in Figure 3.
In the first time interval (t0 £ t £ t1) (Fig. 2), at t=t0,
transistor T is turned on. Voltages: drain — source transistor
uCS and diode uCD equal zero. In the node 1 (Fig.3a), the
value of iL is greater than the supply current ILF = const. The
MOSFET’sbody diode DS conductes difference iL–ILF in the
circuit: DS, L, CT, D. At t=t1, the current iL= ILF and DS
stops conducting. The circuit in Figure 3a is described:
I LF − iS − iL = 0
iL − I LF 1 − iD = 0
L
diL
+ uCT + u D + u DS = 0
dt
2. TOPOLOGY OF ZVS CUK MRC
The structure of ZVS Cuk MRC is shown in Figure 1. Highinductance reactor LF, in series with DC voltage E, provides
constant current ILF to the converter. Reactor at inductance
LF1, equal to inductance LF, enforces constant current ILF1
to: capacitor at capacitance CF and load resistance R in
parallel connection. MOSFET T at resistance RT when
conducting and output capacitance COS is switched at
frequency f. Diode DS is an integral part of the transistor and
enables bi-directional conducting of current iS. The rectifying
diode D includes a junctin capacitance COD.
The converter’s resonant circuit includes: reactor at
inductance L, capacitor at CS in parallel with the transistor T,
El¿bieta Szychta: Multiresonant ZVS CUK Converter
Key words:
multiresonant converter,
Cuk circuit,
zero voltage switching
(ZVS),
resonant circuits
iL = CT
I LF 1 − C F
(1)
duCT
dt
dU O U O
−
=0
dt
R
Fig. 1. ZVS Cuk MRC
'#
a)
b)
c)
d)
Fig. 2. Current and voltage waveforms in ZVS Cuk MRC (relative
units)
where:
u DS — diode DS forward voltage,
u D — diode D forward voltage.
In the second time interval (t1£ t £ t3) (Fig. 2), at t = t1,
current iS = 0, the transistor starts to conduct at uCS = 0 (Fig.
3b). During this time interval, ILF occurs in the circuit: E, LF,
RT and E, LF, L, CT, D. ILF1 occurs in the circuit: D, (CF || R),
LF1. At t=t2, current iL=0, iS=ILF and iD=–ILF1. In the
interval (t2 £ t £ t3,), iL commutates with the current iD. ILF
occurs in the circuit: E, LF, RT , and ILF1 is in circuits: LF1, CT,
L, RT , (CF || R) and LF1, D ,(CF || R). At t=t3, iD=0, D stops
conducting. Voltages: uCS and uCD remain zero. The circuit
in Figure 3b is described:
e)
Fig. 3. Resonant circuit of ZVS Cuk MRC a) in the first interval, b) in
the second interval, c) in the third interval, d) in the fourth interval,
e) in the fifth interval
In the third time interval (t3 £ t £ t4) (Fig. 2) the transistor
is still on (Fig. 3c). iL becomes greater than ILF1, which initiates
charging of CD in the circuit: L, CT, (CD+COD), RT. ILF occurs
in the circuit: E, LF, RT, and ILF1 is in: LF1, CT, L, RT , (CF || R).
At t = t4 the transistor is turned off at uCS=0. The circuit in
Figure 3c is described:
I LF − iS − iL = 0
I LF − iS − iL = 0
iL − iD − I LF 1 = 0
du
iL = CT CT
dt
L
diL
+ uCT + u D − iS RT = 0
dt
I LF 1 − CF
'$
dU O U O
−
=0
dt
R
iL + iCD − I LF 1 = 0
(2)
I LF 1 − CF
L
dU O U O
−
=0
dt
R
(3)
diL
+ uCT − iS RT − uCD = 0
dt
Power Quality and Utilization, Journal • Vol. XII, No 2, 2006
iCD = CD
iL = CT
duCD
dt
duCT
dt
I LF 1 − CF
(3)
uCT + L
In the fourth time interval (t4 £ t £ t8) (Fig. 2), transistor
T and diode D do not conduct (Fig. 3d). At t = t4, transistor
turn-off causes iS to be commutated by iCS. The resonant
current iL is a component of iCS and occurs in the circuit: CT,
L, (CS+COS), (CD+COD). In the time interval (t4 £ t £ t5),
energy accumulated in the inductance L charges capacitors
CS and CD. ILF occurs in the circuit: E, LF, (CS+COS), and
ILF1 occurs in: LF1, CT, L, (CS+COS), (CF¦R). At t=t5, iCD=0
and iL=ILF1. In the time interval (t5 £ t £ t6), capacitor CD
starts to discharge. At t = t6, current iL = 0 and iCD = ILF1.
Energy stored in CS and CD forces a change in direction of
the resonant current iL. ILF occurs in the circuits: E, LF,
(CS+COS) and E, LF, L, CT, (CD+COD). ILF1 is in the circuit:
LF1, (CD+COD), (CF¦R). At t = t7, iCS = 0, iL=ILF and
capacitor CS starts to discharge. In the time interval (t7 = t =
t8), ILF occurs in the circuit: E, LF, L, CT, (CD+COD). The
resonant circuit iL occurs in the circuit: L, CT, (CD+COD),
(CS+COS), and ILF1 is in: LF1, D, (CF¦R). At t = t8, uCD = uD.
The circuit in Figure 3d is described:
diL
− uCS + u D = 0
dt
iL = CT
duCT
dt
iCS = CS
duCS
dt
When the transistor is on, at high quality factor of the circuit,
resonant frequency fD of the circuit R, L, CD, COD is:
fD =
1
2 p L (CD + COD )
fS =
1
2 p L (CS + COS )
iCS
iCD
du
= CD CD
dt
uCT + L
fN =
dU O U O
−
=0
dt
R
du
= CS CS
dt
(4)
El¿bieta Szychta: Multiresonant ZVS CUK Converter
(7)
f
fS
CD + COD
CS + COS
UO
E
(8)
RN = R
ZS
ZS =
In the fifth time interval (t8 £ t £ t10) (Fig. 2), at t = t8,
commutation of iCD and iD begins. Diode D is on. Owing to
low value of junction capacitance COD of D, oscillations of
iD are negligible. Further discharging of capacitor CS occurs
in the circuit: L, CT, D, (CS+COS). ILF occurs in the circuit: E,
LF, L, CT, D. At t = t9, where uCS = uDS, diode DS is ready to
conduct iS . Current iCS of CS is commutated by iS of DS (Fig.
3a). At t = t10 gate pulse to MOSFET initiates the next cycle
of converter operation. The circuit in Figure 3e is described:
iL − iD − I LF1 = 0
CN =
M =
diL
− uCS − uCD = 0
dt
I LF + iCS + iL = 0
(6)
When the diode D is on, at high quality factor of the circuit,
resonant frequency fS of the circuit R, L, CS, COS is:
iL + iCD − I LF 1 = 0
du
iL = CT CT
dt
(5)
ZVS MRC is characterised by:
I LF − iCS − iL = 0
I LF 1 − CF
dU O U O
−
=0
dt
R
(5)
L
+
C
( S COS )
where:
f
— operating frequency,
fN — operating frequency in relative units,
CN — ratio of capacitance,
M — ratio of voltage conversion (output voltage in relative
units),
UO — output voltage of the converter, (IO – load current),
RN — load resistance in relative units,
ZS — characteristic impedance [1].
Input power Pin of the converter is:
Pin = I LF ∗ E
(9)
where:
ILF — mean value of current supply to the converter.
'%
COS = 870pF) and HFA25TB60 fast recovery diode (junction
capacitance COD = 100pF) made by International Rectifier.
The simulation model of Cuk MRC comprises: L = 7mH, CS =
7nF, CD = 23nF, LF = 600mH, CF = 10mF, R = variable. Resonant
frequencies: fS = 678kHz, fD = 396kHz. Supply voltage E =
50V DC.
It was assumed that the converter employs ZVS technique.
ZVS of the transistor is assured when transistor turns on as
DS is conducting at uCS = 0. Transistor is always off when
voltage uCS is approximately zero. Turn-on of diode D is
related to commutation of current iCD, at uCD = 0. The diode’s
turn-off occurs when iCD = 0 and uCD = 0.
PWM technique was employed in the control system.
Variation of operating frequency f and control modulation
ratio b is then possible.
The ratio b is:
Fig. 4. Simulation model of ZVS Cuk MRC
a)
b=
b)
Fig. 5. ZVS operation area of Cuk MRC, CN = 2.9, a) RN = 0.5, b) RN = 1
Output power Pout of the converter is:
Pout = I O ∗ U O =
U O2
R
(10)
Efficiency h of the converter is:
h=
Pout
Pin
(11)
The magnitudes defined by (8 ¸ 11) are necessary to
determine control characteristics and efficiency h of the
converter. Owing to complex mathematical apparatus, the
characteristics and the efficiency h can be defined employing
results of simulation testing.
4. SIMULATION TESTING
ZVS Cuk MRC was subject to simulation testing with
Simplorer programme. The simulation circuit in Figure 4
consists of MOSFET IRFP460 transistor (output capacitance
'&
ton
T
where:
t on — time, when transistor is on,
T — period of transistor operation; T = 1
f
Results of simulation testing of the circuit served to
determine ZVS operation area of the converter: b = f (fN), at
RN = 0.5 and 1 (Fig. 5). The operation area defines permissible
limites of frequency fN and ratio b for which the criteria of
ZVS are fulfilled. Frequency fN reaches its minimum fNmin
and maximum fNmax at b constant.
The range of operating frequency fNmin £ fN £ fNmax, is
variable depending on the values of b and RN. Boundary
frequencies fNmin, fNmax tend to reduce as b rises.
Figure 6 illustrates selected current and voltage waveforms
of ZVS Cuk MRC when f = 400kHz and b = 0.65. Transistor is
turned on when diode DS is conducting, at uCS = 0.
Figure 7 presents control characteristics obtained in
simulation testing: M = f(fN), ISmax / IO = f(fN), UCSmax /
E = f(fN), UCDmax / E = f(fN) for the frequency range fNmin £
fN £ fNmax and ratio b within the ZVS area of transistor’s
operation (Fig. 5). For CN = 2.9, RN = 1, in the range 0.59 £ fN
£ 0.98 (400kHz £ f £ 667kHz), the conversion ratio M is
within: 1.93 ³ M ³ 0.38, maximum voltage of the transistor
UCSmax / E is in the range: 6.2 ³ UCSmax / E ³ 3.0, maximum
voltage of the diode UCDmax / E is in the range: 5.5 ³
UCDmax / E ³ 1.1, maximum transistor current: 5.44 ³ ISmax /
IO ³ 6.22.
Figure 7 implies that increase of relative frequency fN
causes a drop in: M, and maximum voltages of: the transistor
UCSmax / E and diode UCDmax / E.
Greater resistance RN increases: M, maximum voltage of
the diode UCDmax / E, and maximum transistor current ISmax /
IO. Values of maximum transistor voltage UCSmax / E remain
unchanged. Two inflexion points of characteristics occur in
the waveforms I Smax / IO. The values of ISmax / IO are
minimum for M = 1, and maximum for M = 0.5. The range of
boundary values of relative frequency fNmin in control
characteristics tends towards greater values as the value of
RN increases, and the range of boundary values of relative
frequency fNmax remains unchanged.
Power Quality and Utilization, Journal • Vol. XII, No 2, 2006
Fig. 6. Simulation current and voltage waveforms in ZVS Cuk MRC, CN = 2.9, R = 14.91W, UO = 50.5V, IO = 3.4A, f = 400kHz (fN = 0.59),
b = 0.65, h = 0.89, P in = 197W, P out = 175W
Figure 8 illustrates total transistor power losses PT and
total diode D power losses PD. Simulation testing results
indicate that PT are negligible (PT < 10W) in the frequency
range 0.62 £ fN £ 0.9 for RN = 0,5 and in 0.68 £ fN £ 0.95
for RN = 1. The increased resistance RN causes higher PT for
the same fN. Operation of T causes a major increase of PT at
b > 0.55. PT rise by DPT = 30W in the range of frequency
variation DfN = 0.15.
Power losses PD of diode D reduce as RN and fN. grow.
The variation is approximately uniform throughout the
El¿bieta Szychta: Multiresonant ZVS CUK Converter
frequency range. The maximum losses PD are about (5¸7)W.
In the ZVS operation of the converter, when frequencies
fN reduce, PT are several times greater than PD at the same b
and RN.
Both PT and PD significantly reduce as operating frequency
of the circuit fN grows. This results from lower transistor current
iS and diode current iD, and from decrease of conduction losses
in semiconductor elements in high frequency range. The
resulting analysis indicates that the transistor should be
characterized by the smallest possible resistance RT.
''
Fig. 7. Control characteristics for ZVS Cuk MRC in relative units, CN = 2.9, R N = 0.5, R N = 1; a) conversion ratio M; b) maximum transistor
current ISmax / IO; c) maximum diode voltage UCDmax / E; d) maximum transistor voltage UCSmax / E
Figure 9 shows the output power Pout of ZVS Cuk MRC.
Increased RN causes a power Pout increase at the same
frequency fN. For b > 0.55, Pout grows significantly in low
frequency range.
Figure 10 shows efficiency h of ZVS Cuk MRC. The
converter’s efficiency is within the range 0,86 = h = 0,92 at
RN. Greater fN does not alter h significantly at CN = const,
RN = const. For reducing fN, particularly at b > 0.55, h drops
slightly as losses PT climb dynamically. Great and constant h
can be maintained when fN is decreasing since output power
Pout increases dynamically at the time (Fig. 9).
5. CONCLUSION
On the basis of simulation testing of MRC under analysis,
it can be concluded that:
1. ZVS Cuk converter provides good conditions of zerovoltage switching for both the transistor and the diode.
The area of ZVS operation is determined by switching
frequency and ratio of modulation, and depends on load
resistance.
2. Maximum voltages of transistor and diode decrease as
the converter’s operating frequency increases or load
resistance reduces.
3. Energy efficiency of ZVS Cuk MRC is great and depends
primarily on conduction losses in semiconductor
elements.
Fig. 8. a) Total transistor power losses PT; b) total diode D power losses PD
Power Quality and Utilization, Journal • Vol. XII, No 2, 2006
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Fig. 9. Output power Pout of ZVS Cuk MRC
El¿bieta Szychta
Graduated from the Electrical Faculty of Warsaw
Polytechnic in 1981. Obtained a degree of doctor of
engineering from the Electrical Faculty of Warsaw
Polytechnic in 1988. Since 1981 she has worked for the
Transport Faculty Kazimierz Pulaski at the Technical
University of Radom. An assistant professor in the
Department of Electrical Machinery and Equipment.
Interested in industrial power electronics.
Address: Politechnika Radomska, Wydzia³ Transportu
26-600 Radom, ul. Malczewskiego 29; tel: (048) 361 77 00
e-mail: e.szychta@pr.radom.pl
El¿bieta Szychta: Multiresonant ZVS CUK Converter
Fig. 10. Efficiency h of ZVS Cuk MRC, CN = 2.9; a) RN = 0.5; b) RN = 1