An Improved Active-clamp ZVS Forward
Converter Circuit
1
Shijia Yang1, Zhaoming Qian1, Qian Ouyang1, Fang Z. Peng1,2
Zhejiang University, Hangzhou, China, 310027 2Michigan State University Department of Electrical and Computer Engineering
load of 10 A and a switching frequency of 100 kHz are
provided to support this new topology theory.
Abstract-In order to achieve Zero Voltage Switching (ZVS)
easier for both primary switch and auxiliary switch in the active
clamp forward converter, an improved active-clamp ZVS
forward converter topology is proposed in this paper. Compared
with the conventional active-clamp forward converter, the
improved one with an auxiliary network which is consisted of a
clamp capacitor and an inductor could easily achieve ZVS in
full-load range. Therefore the circuit efficiency is increased by
reducing the switching loss of the switches. The operation
principles of the proposed converter circuit are analyzed in
detail and the performance is compared with the conventional
one. The design procedure and the experimental results are
presented for a converter with a 230 V input; 14.4 V/10 A output.
The experimental results match the theoretical analysis very well.
Ⅱ. OPERATION PRINCIPLE
The proposed active-clamp ZVS forward circuit is given in
the Fig.1. The basic forward converter in the primary side is
consisted of the transformer, primary switch Q1 . The auxiliary
switch Q2 and clamp capacitor Cc are used to absorb the surge
energy from the leakage inductance so as to reduce the
voltage stress of the main switch Q1 . Theoretically, the main
switch could achieve ZVS by the resonant circuit include the
junction capacitance Coss , the leakage inductance Lr and the
magnetizing inductance Lm . However, it is difficult to meet
the demand since the magnetizing current is not large enough.
So, the ZVS active clamp forward converter with an auxiliary
network consisted of a clamp capacitance Ca and
Keywords- ZVS, active-clamp, forward.
Ⅰ.INTRODUCTION
Structure of forward converters has been used in more and
more applications (about 50 W – 500 W) because of its
simpleness, high-efficiency and good-performance. But the
duty circle could not exceed 50% and the high voltage stress
of the switch suffered from the leakage inductance reaches
more than two times of the input voltage if the reset turns
equal to the primary turns. Then, the structure of active clamp
forward converter was proposed to solve the problems above.
The magnetic core is fully used because it works in both first
and third quadrant while the reset winds are necessary in
conventional forward converter since the magnetic core
almost just works in the first quadrant. The voltage stress is
clamped by the auxiliary clamp capacitor as well as the duty
circle problem is solved in this topology. On the other hand,
the hard switching techniques in the forward converters
results in low efficiency. Theoretically, with one auxiliary
switch in the active-clamp forward converter to recycle the
energy stored in the transformer leakage, the primary switch
could turn off under zero voltage if the driver is fast enough.
However, the primary switch, in fact, is hard to achieve zero
voltage turn-on in this circuit. The result turns out that the
switching losses can not be reduced greatly and which leads
to the total efficiency is not improved greatly also.
In this paper an active clamp ZVS forward converter with
an auxiliary network is presented. With this new technique
proposed, ZVS of the primary switch can be easily achieved
in full-load range; hence the switching loss of the converter is
reduced. A detail of the design procedure and the converter
operation principles are analyzed in this paper. Finally, the
experimental results based on the input voltage of 230 V and
the output voltage of 14.4 V prototype working at rated output
978-1-4244-1874-9/08/$25.00 ©2008 IEEE
inductance La is proposed in Fig.1 below.
Lr
iLr
Ca
iD1 D1
Io
im
Va
Lm
Q2
D2
Vp
La
Vin
ia
Lo
N:1
iD2
Co
RL
Vo
Cc
Vc
ic
i Q1
Q1
Coss
v ds
Fig.1 The proposed active clamp ZVS forward converter circuit
Before analyzing the circuit, there are several assumptions
must be made.
1. The leakage inductance Lr is much smaller than the
magnetizing inductance Lm
2.
Clamp capacitor Cc is much lager than the junction
capacitance Coss
3.
4.
The clamp capacitor Cc and Ca are large enough so
that the voltage on them are constant.
The output inductance filter is large enough that the
output voltage and current are constant.
The key waveforms of the converter are shown in Fig.2.
The detailed operation principles are described as below:
318
dvds
= im − ia
dt
di
( Lr + Lm ) m = Vin − vds
dt
di
La a = vds − Vin
dt
The resonant capacitor voltage is expressed as:
I sinω1(t −t2 )
vds (t) = Vin −Vin ⋅ cosω1(t −t2 ) +[Im (t2 ) − Ia (t2 ) + o ]
N ω1Coss
Coss
on
off
off
on
Q1
Q2
Vin+Vc
Vin
vds
im
1
Where ω1 =
ia
(
1
1
+ )−1 ⋅ Coss
Lm + Lr La
(4)
(5)
State4 [t3<t<t4]: This stage begins when vds = Vin and ends
iD1
at time t4 when vds = Vin + Vc . The secondary side diodes are
iQ1
t0 t1
t3 t4
t2
t5
both conducting. The resonant tank is consisted of La ,
t6 t7 t8
Lr and Coss .
Fig.2 Key waveforms
dvds
= iLr − ia
dt
di
Lr Lr = Vin − vds
dt
dia
La
= vds − Vin
dt
The resonant capacitor voltage is expressed as:
I (t ) − I a (t3 )
vds (t ) = Vin + Lr 3
sin ω2 (t − t3 )
ω2 Coss
Coss
The clamp capacitor voltage is obtained easily because the
voltage-second products balance principle. The voltage is
given as:
DVin
Vc = Va =
(1)
1− D
State1 [t0<t<t1]: At t0, primary switch Q1 is turned on.
The secondary side diodes are both conducting so that the
input voltage is added on the leakage inductor Lr and the
Where ω 2 =
current iLr is linearly increasing. The current is given as:
iLr (t ) = I Lr (to ) +
Vin
(t − to )
Lr
(2)
1
1
1
( + ) −1 ⋅ C oss
Lr La
(6)
(7)
State5 [t4<t<t5]: Since the anti-parallel diode across
auxiliary switch is conducting current, Q2 can be ZVS turned
State2 [t1<t<t2]: At t1, the secondary diode current iD 2 =0
and D2 is off. Magnetizing current im is linearly increasing
while current ia flows through La and Ca is linearly
on in this interval when D1 and D2 are both still conducting.
decreasing. The current ia will change from a positive value to
a negative one during the interval. And the current flows
through the primary switch Q1 is consisted of ia , im and the
The voltage Va forces current ia to increase linearly while the
State6 [t5<t<t6]: At time t5 , iD1 =0 and Q2 is turned on.
magnetizing current im decreases linearly.
ia (t ) = I a (t5 ) +
primary part of the output current I o .
im (t ) = I m (t1 ) +
ia (t) = Ia (t1) −
Vin
(t − t1 )
Lm
Vin +Vc −Va
(t −t1)
La
Va
(t − t5 )
La
im (t ) = I m (t5 ) −
Vc
(t − t5 )
Lm
(8)
State7 [t6<t<t7]: The auxiliary switch Q2 is turned off at
(3)
time t6 . The junction capacitor Coss is discharged via current
ia and im at the same time. This state ends at time t7 when
the voltage vds decreases to Vin .
State3 [t2<t<t3]: Main switch Q1 is turned off at time t2 ,
The primary current charges the resonant capacitance Coss
from 0 to Vin .
319
(a) State1
(b) State2
(c) State3
(d) State4
(f) State5
(g) State6
(h) State7
(i) State8
Fig.3 The equivalent circuits of the 8 states in the proposed converter
Where ω4 = ω2
dvds
= im − ia
dt
di
(9)
( Lr + Lm ) m = Vin − vds
dt
di
La a = vds − Vin
dt
The resonant capacitor voltage is expressed as:
sin ω3 (t − t6 )
vds (t ) = Vin + Vc ⋅ cos ω3 (t − t6 ) + [I m (t6 ) − Ia (t6 )]
ω3Coss
Coss
Where ω3 = ω1
(12)
To ensure ZVS operation of Q1 , the condition of
Vin < −
I r (t7 ) − I a (t7 )
must be satisfied.
ω4 Coss
Ⅲ. DESIGN PROCESURE
1. The Key Issue to Realize The ZVS
The voltage across the junction capacitor vds should
resonate to zero via the current ia and im during the time when
(10)
the auxiliary switch Q2 is turned off until the primary
State8 [t7<t<t8]: At time t7 the voltage vds decreases to
switch Q1 is turned on.
One assumes that the period of switch is T, and the duty
circle is D. To simplify the analysis, it is assumed that:
I a (t6 ) = I a (t7 ) = ia − max
(13)
I m (t6 ) = I r (t7 ) = − im − max
Vin . Diodes D1 and D2 are both turned on. The voltage vds
decreases to zero and the anti-parallel diode across primary
switch is turned on, then the main switch could realize ZVS
operation.
dv
Coss ds = iLr − ia
dt
di
(11)
Lr Lr = Vin − vds
dt
di
La a = vds − Vin
dt
The resonant capacitor voltage is expressed as:
I (t ) − I a (t7 )
vds (t ) = Vin + r 7
sin ω4 (t − t7 )
ω4 Coss
The interval between t6 and t7 could be obtained by the
equation (10), and is given as:
Vc ⋅ Coss
(14)
t7 − t6 ≈
ia − max + im − max
The interval between t6 and t7 is a quarter period of the
resonation could be the best condition and the primary
320
switch
will
Q1
achieve
ZVS
2.3 Diodes on the secondary side
The voltage stress of the rectify diodes on the secondary
side are presented as:
V
V
(23)
VD1− max = c − max ; VD 2 − max = in − max
n
n
While the current stress of D1 and D2 are given as:
since
ia − max + im − max
sin ω4 (t8 − t7 ) ≥ Vin must be satisfied.
ω4 Coss
One can obtain the inductance La should meet the condition of
D ⋅ T ⋅ Lm
.
(15)
La ≤
Coss
2⋅
⋅ Lm − D ⋅ T
Lr
I D1− max = Dmax ⋅ I o ; I D 2 − max = (1 − Dmin ) ⋅ I o
(24)
Where the maximum and minimum duty circles are presented
as:
n ⋅ (Vo + VD )
n ⋅ (Vo + VD )
; Dmin =
(25)
Dmax =
Vin − min
Vin − max
2.4 The output filter
The output inductor should be calculated as below:
V ⋅ (1 − Dmin ) ⋅ T
Lo ≥ o
(26)
ΔI o
It is assumed that the interval when the auxiliary switch Q2
is turned off until the primary switch Q1 is turned on is tdd .On
the basis of the analyses above, the tdd is given as:
tdd = t8 − t6 ≈
2 ⋅ La ⋅ Lm ⋅ Coss 1
+ ⋅ π Lr ⋅ Coss
D ⋅ ( La + Lm ) ⋅ T 2
(16)
2. The Procedure
2.1 Transformer
Since the relation between input voltage and output voltage,
one obtained:
Vin ⋅ D = n ⋅ (Vo + VD )
(17)
According to the equation (1) and (17), the Vc could be
presented as:
n ⋅ (Vo + VD )
n ⋅ (Vo + VD )Vin
(18)
=
VC =
n ⋅ (Vo + VD ) Vin − n ⋅ (Vo + VD )
1−
Vin
The output filter capacitance Co for the aluminum
electrolytic capacitors can be expressed as:
ΔI
Co = 65 ⋅10−6 o
(27)
ΔVo
2.5 The auxiliary network
When the primary switch Q1 and the transformer are
The voltage stress of the primary switch Q1 is obviously
designated, then La is obtained by the equation (15). The
peak current value through the auxiliary net is given as:
D ⋅ T ⋅ Vin
ia − max =
(28)
2 ⋅ La
could be presented as VC + Vin . And it will meet its two
The value of the clamp capacitance Ca will be confirmed
maximum values when the input voltage Vin meets the
maximum value and the minimum one. In order to keep the
clamp voltage at a lowest level, the two maximum value of
the vds should be the same.
due to the ripple voltage across the Ca .It is expressed as:
Ca =
capacitance Cc is given as:
Cc =
4 ⋅ ΔVc
(30)
To verify the theoretical analysis of the circuit proposed, a
230 V input, 14.4 V/10 A output active clamp ZVS forward
converter has been implemented. The parameters and key
components are listed as follows:
(21)
Table1. Parameters and key components of the converter
Q2
Transformer
D1 & D2
Lo
SPA11N60C3
STP4NM60
PQ32/30,
Np: Ns =49:
7
MBR10H100CT
PQ26/25,
35 μH
La
Ca
Cc
Frequency
Dead time
EE19 635 μH
220 nF
220 nF
100 kHz
120 ns
Q1
The maximum current flow through the primary switch Q1
and auxiliary switch Q2 is given as:
1
I o + ΔI o
2
I Q1− max =
+ ia − max + im − max
n
I Q 2 − max = ia − max + im − max
( ia − max + im − max ) ⋅ T
Ⅳ. DESIGN EXAMPLE
the auxiliary switch Q2 could be calculated as:
n ⋅ (Vo + VD ) ⋅ Vin − min
+ Vin − min
Vin − min − n ⋅ (Vo + VD )
(29)
4 ⋅ ΔVa
As the same situation as the capacitance Ca , the
n ⋅ (Vo +VD ) ⋅Vin−min
n⋅ (Vo +VD ) ⋅Vin−max
+Vin−min =
+Vin−max (19)
Vin−min − n ⋅ (Vo +VD )
Vin−max − n⋅ (Vo +VD )
The turn ratio of the transformer n could be calculated from
the equation (19).It is given as:
Vin − min ⋅ Vin − max
n=
(20)
(Vo + VD )(Vin − min + Vin − max )
2.2 Switch on the primary side
Therefore, the voltage stress of the primary switch Q1 and
vds − max =
ia − max ⋅ T
(22)
Where ΔI o is the ripple current of the I o .
321
Fig.4 shows the driving signals of Q1 and Q2 . Fig.5 shows
the driving signal and drain to source voltage of Q1 .
Fig.7 gate to source and drain to source voltage waveforms of main
switch in the conventional active-clamp forward converter
Fig.4 driving waveforms of two switches
Fig.8 efficiency curve @ Vo＝12 V
Fig.5 gate to source and drain to source waveforms
of main switch
Fig.6 presents the driving signal and current waveforms
of Q1 . As can be seen from these two figures, before Q1 is
turned on, current iQ1 flows through the anti-parallel diode
across Q1 and vds is zero.
Fig.9 efficiency curve @ Io＝10 A
Ⅴ. CONCLUSION
An improved active clamp ZVS forward converter is
proposed in the paper. With the auxiliary network, the
switches of the converter could realize ZVS. A 230 V input,
14.4 V/10 A output active clamp ZVS forward converter is
built up and the experimental results match the theoretical
analysis very well.
Fig.6 gate to source voltage waveform and
current signal of the main switch
Ⅵ. REFERENCES
Fig.7 shows the driving signal and drain to source voltage
of Q1 in the conventional active clamp forward converter
without the auxiliary network. As it shows, the main switch
can not achieve ZVS. Fig.8& Fig.9 present the efficiency
curves of the active clamp ZVS forward converter compared
with the conventional one and it is clear that the efficiency of
the proposed circuit in this paper is improved greatly. The
experimental results match the theoretical analysis very well.
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322
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