PRELIMINARY DATA SHEET
4G bits DDR2 Mobile RAM™
EDB4432BABH (128M words × 32 bits)
Specifications
Features
• Density: 4G bits
• Organization: 16M words × 32 bits × 8 banks
• Package: 134-ball FBGA
— Package size: 11.5mm × 11.5mm
— Ball pitch: 0.65mm
— Lead-free (RoHS compliant) and Halogen-free
• Power supply
— VDD1 = 1.70V to 1.95V
— VDD2, VDDCA, VDDQ = 1.14V to 1.30V
• Data rate: 1066Mbps (max.)
• Interface: HSUL_12
• Burst lengths (BL): 4, 8, 16
• Burst type (BT)
— Sequential (4, 8, 16)
— Interleave (4, 8)
• Read latency (RL): 8
• Precharge: auto precharge option for each burst
access
• Programmable driver strength
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/32ms
— Average refresh period: 3.9s
• Operating case temperature range
— TC = -30°C to +85°C
• Low power consumption
• Per Bank Refresh
• Partial Array Self-Refresh (PASR)
— Bank Masking
— Segment Masking
• Auto Temperature Compensated Self-Refresh
(ATCSR) by built-in temperature sensor
• Double-data-rate architecture; two data transfers per
one clock cycle
• The high-speed data transfer is realized by the 4 bits
prefetch pipelined architecture
• Differential clock inputs (CK and /CK)
• Bi-directional differential data strobe (DQS and /DQS)
• Commands entered on both rising and falling CK edge;
data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Burst termination by burst stop command
Document No. E1890E20 (Ver. 2.0)
Date Published May 2012 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2012
EDB4432BABH
Ordering Information
Part number
Organization
(words x bits)
Clock frequency
Data rate
Read latency
Package
EDB4432BABH-1D-F
128M x 32
533MHz
1066Mbps
8
134-ball FBGA
Part Number
E D B 44 32 B A BH - 1D - F
Elpida Memory
Environment Code
F: Lead Free (RoHS compliant)
and Halogen Free
Type
D: Packaged Device
Product Family
B: DDR2 Mobile RAM
Speed
1D: 1066Mbps
Density/Chip select
44: 4Gb/1-CS
Package
BH: FBGA
Organization
32: x32
Revision
Power Supply, Interface
B: VDD1 = 1.8V, VDD2 = VDDCA = VDDQ = 1.2V,
S4B device, HSUL
Preliminary Data Sheet E1890E20 (Ver. 2.0)
2
EDB4432BABH
CONTENTS
Specifications ........................................................................................................................................ 1
Features ................................................................................................................................................ 1
Ordering Information ............................................................................................................................. 2
Part Number .......................................................................................................................................... 2
Pin Configurations ................................................................................................................................. 4
Pin Descriptions .................................................................................................................................... 5
Block Diagram ....................................................................................................................................... 6
Pin Capacitance .................................................................................................................................... 7
Package Drawing .................................................................................................................................. 8
1. Electrical Conditions ...................................................................................................................... 9
1.1 Absolute Maximum Ratings .............................................................................................. 9
1.2 Recommended DC Operating Conditions ........................................................................ 9
1.3 AC and DC Input Measurement Levels .......................................................................... 10
1.4 VREF Tolerances ........................................................................................................... 11
1.5 Input Signal ..................................................................................................................... 12
1.6 AC and DC Logic Input Levels for Differential Signals ................................................... 13
1.7 Differential Input Cross Point Voltage ............................................................................. 16
1.8 Slew Rate Definitions for Single-Ended Input Signals .................................................... 16
1.9 Slew Rate Definitions for Differential Input Signals ........................................................ 17
1.10 AC and DC Output Measurement Levels ....................................................................... 18
1.11 Differential Output Slew Rate ......................................................................................... 20
1.12 Overshoot and Undershoot Specifications ..................................................................... 21
1.13 RONPU and RONPD Resistor Definition ....................................................................... 21
2. Electrical Specifications ............................................................................................................... 24
2.1 IDD Measurement Conditions ........................................................................................ 24
2.2 DC Characteristics 1 ....................................................................................................... 26
2.3 DC Characteristics 2 ....................................................................................................... 28
2.4 Clock Specification ......................................................................................................... 29
2.5 Period Clock Jitter .......................................................................................................... 31
2.6 AC Characteristics .......................................................................................................... 34
2.7 CA and /CS Setup, Hold and Derating ........................................................................... 40
2.8 Data Setup, Hold and Slew Rate Derating ..................................................................... 47
3. Pin Function ................................................................................................................................. 54
4. Block Diagram ............................................................................................................................. 55
5. Simplified State Diagram ............................................................................................................. 56
6. Truth tables .................................................................................................................................. 57
7. Power-up, initialization and Power-Off ......................................................................................... 59
7.1 Power Ramp and Device Initialization ............................................................................ 59
8. Mode Register Definition ............................................................................................................. 63
Preliminary Data Sheet E1890E20 (Ver. 2.0)
3
EDB4432BABH
Pin Configurations
/xxx indicate active low signal.
134-ball FBGA
1
2
3
4
5
6
7
NU
NU
NU
NC
NC
VDD2
VDD1
DQ31
VDD1
VSS
NC
VSS
VSS
VSS
VDD2
ZQ
VDDQ
VSS
CA9
CA8
VDDCA* CA6
CA7
8
9
10
NU
NU
DQ29
DQ26
NU
VDDQ
DQ25
VSS
VDDQ
DQ30
DQ27
DQS3 /DQS3
VSS
DQ28
DQ24
DM3
DQ15
VDDQ
VSS
VSS
DQ11
DQ13
DQ14
DQ12
VDDQ
/DQS1 DQS1
DQ10
DQ9
DQ8
VSS
VDD2
VSS VREFDQ
A
B
C
D
E
F
G
VDD2
CA5 VREFCA
H
VDDCA* VSS
/CK
DM1
VDDQ
J
VSS
NC
CK
VSS
VDDQ
CKE
NC
NC
DM0
VDDQ
/CS
NC
NC
CA4
CA3
CA2
K
L
/DQS0 DQS0
DQ5
DQ6
DQ7
VSS
M
VSS
DQ4
DQ2
DQ1
DQ3
VDDQ
VSS VDDCA* CA1
DQ19
DQ23
DM2
DQ0
VDDQ
VSS
VSS
VDD2
CA0
VDDQ
DQ17
DQ20
DQS2 /DQS2
VSS
VDD1
VSS
NC
VSS
VSS
VDDQ
DQ22
VSS
VDDQ
NU
NC
NC
VDD2
VDD1
DQ16
DQ18
DQ21
NU
NU
NU
NU
NU
N
P
R
T
U
(Top view)
* VDDCA balls are internally connected to VDD2.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
4
EDB4432BABH
Pin Descriptions
Pin name
Function
CK, /CK
Clock
CKE
Clock enable
/CS
Chip select
CA0 to CA9
DDR command/address inputs
DM0 to DM3
Input data mask
DQ0 to DQ31
Data input/output
DQS0 to DQS3
/DQS0 to /DQS3
Data strobe
VDD1
Core power supply 1
VDD2
Core power supply 2
VDDCA
Input receiver power supply
VDDQ
I/O power supply
VREFCA
Reference voltage for CA input receiver
VREFDQ
Reference voltage for DQ input receiver
VSS
Ground
ZQ
Reference pin for output drive strength calibration
NC*1
NU
*2
No connection
Not usable
Notes: 1. Not internally connected.
2. Don’t connect.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
5
(Address configurations: Row:R0-R13,
Column:C0-C9,
Bank:BA0-BA2)
EDB4432BABH
Block Diagram
CKE /CS
VDD1
VDD2
CK, /CK
VDDCA
CA0 to CA9
4G bits
(128M x 32)
VDDQ
VREFCA
DQS0 to DQS3
/DQS0 to /DQS3
DQ0 to DQ31
DM0 to DM3
ZQ
VREFDQ
VSS
Preliminary Data Sheet E1890E20 (Ver. 2.0)
6
EDB4432BABH
Pin Capacitance
Parameter
Symbol
Pins
min.
max.
Unit
Note
Input capacitance
CI1
CK, /CK
1.0
3.5
pF
1, 2
CI2
All other DDR2 Mobile RAM
input only pins
1.0
3.5
pF
1, 2
CI/O
DQ, DM, DQS, /DQS
1.5
4.5
pF
1, 2, 3
CZQ
ZQ
1.5
3.5
pF
1, 2, 3
Data input/output capacitance
Notes: 1. This parameter is not subject to production test. It is verified by design and characterization.
2. These parameters are measured on f = 100MHz, VOUT = VDDQ/2, TA = +25°C.
3. DOUT circuits are disabled.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
7
EDB4432BABH
Package Drawing
134-ball FBGA
Solder ball: Lead free
Unit: mm
11.50 ± 0.10
0.15 S B
11.50 ± 0.10
INDEX MARK
0.15 S A
0.80 max.
0.10 S
S
0.08 S
0.22 ± 0.05
134−φ0.30 ± 0.05
φ0.08 M S A B
0.65
B
10.40
A
INDEX MARK
0.65
0.325
5.85
ECA-TS2-0462-01
Preliminary Data Sheet E1890E20 (Ver. 2.0)
8
EDB4432BABH
1. Electrical Conditions
• All voltages are referenced to VSS (GND)
• Execute power-up and Initialization sequence before proper device operation is achieved.
• Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper
operation, the DDR2 Mobile RAM Device must be powered down and then restarted through the
specialized initialization sequence before normal operation can continue.
1.1
Absolute Maximum Ratings
Table 1 Absolute Maximum Ratings
Parameter
Symbol
min.
max.
Unit
Note
VDD1 supply voltage relative to VSS
VDD1
-0.4
2.3
V
2
VDD2 supply voltage relative to VSS
VDD2
-0.4
1.6
V
2
VDDCA supply voltage relative to VSSCA
VDDCA
-0.4
1.6
V
2
VDDQ supply voltage relative to VSSQ
VDDQ
-0.4
1.6
V
2, 3
Voltage on any ball relative to VSS
VIN, VOUT
-0.4
1.6
V
Storage Temperature
TSTG
-55
125
C
Notes: 1.
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. See Power-Ramp section “Power-up, initialization and Power-Off” on page 59 for relationship between power supplies.
3. VREF 0.6 x VDDQ; however, VREF may be  VDDQ provided that VREF 300mV.
4. Storage Temperature is the case surface temperature on the center/top side of the DDR2
Mobile RAM Device. For the measurement conditions, please refer to JESD51-2 standard.
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
1.2
Recommended DC Operating Conditions
Table 2 Recommended DC Operating Conditions(TC = -30C to +85C)
Parameter
Symbol
min.
typ.
max.
Unit
Core Power1
VDD1
1.70
1.80
1.95
V
Core Power2
VDD2
1.14
1.20
1.30
V
Input Buffer Power
VDDCA
1.14
1.20
1.30
V
I/O Buffer Power
VDDQ
1.14
1.20
1.30
V
Preliminary Data Sheet E1890E20 (Ver. 2.0)
9
EDB4432BABH
1.3
1.3.1
AC and DC Input Measurement Levels
AC and DC Input Levels for Single-Ended CA and /CS Signals
Table 3 Single-Ended AC and DC Input Levels for CA and /CS Inputs
Parameter
AC input logic high
Symbol
VIHCA(AC)
min.
max.
Unit Note
VREF + 0.220
Note 2
V
1, 2
AC input logic low
VILCA(AC)
Note 2
VREF - 0.220
V
1, 2
DC input logic high
VIHCA(DC)
VREF + 0.130
VDDCA
V
1
DC input logic low
VILCA(DC)
VSS
VREF - 0.130
V
1
0.49 × VDDCA
0.51 × VDDCA
V
3, 4
Reference Voltage for CA and /CS inputs VREFCA(DC)
Notes: 1. For CA and /CS input only pins. VREF = VREFCA(DC).
2. See “Overshoot and Undershoot Specifications” on page 21.
3. The ac peak noise on VREFCA may not allow VREFCA to deviate from VREFCA(DC) by
more than ± 1% VDDCA (for reference: approx. ± 12 mV).
4. For reference: approx. VDDCA/2 ± 12 mV.
1.3.2
AC and DC Input Levels for CKE
Table 4 Single-Ended AC and DC Input Levels for CKE
Parameter
Symbol
min.
max.
Unit
Note
CKE Input High Level
VIHCKE
0.8 × VDDCA
Note 1
V
1
CKE Input Low Level
VILCKE
Note 1
0.2 × VDDCA
V
1
Note: 1.
1.3.3
See “Overshoot and Undershoot Specifications” on page 21.
AC and DC Input Levels for Single-Ended Data Signals
Table 5 Single-Ended AC and DC Input Levels for DQ and DM
Parameter
AC input logic high
Symbol
VIHDQ(AC)
min.
max.
VREF + 0.220
Note 2
Unit Note
V
1, 2
AC input logic low
VILDQ(AC)
Note 2
VREF - 0.220
V
1, 2
DC input logic high
VIHDQ(DC)
VREF + 0.130
VDDQ
V
1
DC input logic low
VILDQ(DC)
VSSQ
VREF - 0.130
V
1
Reference Voltage for DQ, DM inputs
VREFDQ(DC)
0.49 × VDDQ
0.51 × VDDQ
V
3, 4
Notes: 1. For DQ input only pins. VREF = VREFDQ(DC).
2. See “Overshoot and Undershoot Specifications” on page 21.
3. The ac peak noise on VREFDQ may not allow VREFDQ to deviate from VREFDQ(DC) by
more than ± 1% VDDQ (for reference: approx. ± 12 mV).
4. For reference: approx. VDDQ ± 12 mV.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
10
EDB4432BABH
1.4
VREF Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages VREFCA and VREFDQ are
illustrated in Figure 1. It shows a valid reference voltage VREF(t) as a function of time. (VREF stands for
VREFCA and VREFDQ likewise).
VDD stands for VDDCA for VREFCA and VDDQ for VREFDQ. VREF(DC) is the linear average of
VREF(t) over a very long period of time (e.g. 1 sec) and is specified as a fraction of the linear average of
VDDQ or VDDCA also over a very long period of time (e.g. 1 sec). This average has to meet the min/max
requirements in Table 3. Furthermore VREF(t) may temporarily deviate from VREF(DC) by no more than
± 1% VDD. VREF(t) cannot track noise on VDDQ or VDDCA if this would send VREF outside these
specification.
voltage
VDD
VREF(t)
VREF AC-noise
VREF(DC)max
VREF(DC)
VDD/2
VREF(DC)min
VSS
time
Figure 1 — Illustration of VREF(DC) tolerance and VREF AC-noise limits
The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC) and VIL(DC) are
dependent on VREF.
“VREF “ shall be understood as VREF(DC), as defined in Figure 1.
This clarifies that dc-variations of VREF affect the absolute voltage a signal has to reach to achieve a
valid high or low level and therefore the time to which setup and hold is measured. Devices will function
correctly with appropriate timing deratings with VREF outside these specified levels so long as VREF is
maintained between 0.44 × VDDQ (or VDDCA) and 0.56 × VDDQ (or VDDCA) and so long as the
controller achieves the required single-ended AC and DC input levels from instantaneous VREF (see the
“Single-Ended AC and DC Input Levels for CA and /CS Inputs” on page 10 and “Single-Ended AC and
DC Input Levels for DQ and DM” on page 10.) Therefore, system timing and voltage budgets need to
account for VREF deviations outside of this range.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and
voltage associated with VREF AC-noise. Timing and voltage effects due to AC-noise on VREF up to the
specified limit (± 1% of VDD) are included in DRAM timings and their associated deratings.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
11
EDB4432BABH
1.5
Input Signal
VIL and VIH Levels With Ringback
1.550V
VDD + 0.35V
1.200V
VDD
0.820V
VIH(AC)
0.730V
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
VREF + AC noise
0.470V
VIL(DC)
0.380V
VIL(AC)
0.000V
VSS
Minimum VIL and VIH Levels
0.820V
0.730V
VIH(AC)
VIH(DC)
0.624V
0.612V
0.600V
0.588V
0.576V
0.470V
0.380V
VIL(DC)
VIL(AC)
-0.350V
VREF + DC error
VREF - DC error
VREF - AC noise
VSS - 0.35V
Figure 2 — DDR2 Mobile RAM-533 to DDR2 Mobile RAM-1066 Input Signal
Notes: 1. Numbers reflect nominal values.
2. For CA0 – CA9, CK, /CK and /CS, VDD stands for VDDCA. For DQ, DM, DQS, and /DQS,
VDD stands for VDDQ.
3. For CA0 – CA9, CK, /CK and /CS, VSS stands for VSS. For DQ, DM, DQS, and /DQS, VSS
stands for VSSQ.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
12
EDB4432BABH
1.6
1.6.1
AC and DC Logic Input Levels for Differential Signals
Differential signal definition
differential
voltage
tDVAC
VIHdiff(AC)min.
VIHdiff(DC)min.
CK – /CK
DQS – /DQS
0.0
VILdiff(DC)max.
VILdiff(AC)max.
half cycle
tDVAC
time
Figure 3 — Definition of differential ac-swing and “time above AC-level” tDVAC
1.6.2
Differential swing requirements for clock (CK – /CK) and strobe (DQS – /DQS)
Table 6 Differential AC and DC Input Levels
Parameter
Symbol
min.
max.
Unit
Note
Differential input high
VIHdiff(DC)
2 × (VIH(DC) - VREF)
Note 3
V
1
Differential input low
VILdiff(DC)
Note 3
2 × (VIL(DC) - VREF)
V
1
Differential input high AC
VIHdiff(AC)
2 × (VIH(AC) - VREF)
Note 3
V
2
Differential input low AC
VILdiff(AC)
Note 3
2 × (VIL(AC) - VREF)
V
2
Notes: 1. Used to define a differential signal slew-rate.
2. For CK – /CK use VIH/VIL(AC) of CA and VREFCA; for DQS – /DQS, use VIH/VIL(AC) of
DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the
reduced level applies also here.
3. These values are not defined, however the single-ended signals CK, /CK, DQS, and /DQS
need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals
as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot
Specifications” on page 21.
4. For CK and /CK, VREF = VREFCA(DC). For DQS and /DQS, VREF = VREFDQ(DC).
Preliminary Data Sheet E1890E20 (Ver. 2.0)
13
EDB4432BABH
Table 7 Allowed time before ringback (tDVAC) for CK – /CK and DQS – /DQS
tDVAC [ps]
@ |VIH/Ldiff(AC)| = 440mV
tDVAC [ps]
@ |VIH/Ldiff(AC)| = 600mV
min.
min.
> 4.0
175
75
4.0
170
57
3.0
167
50
2.0
163
38
1.8
162
34
1.6
161
29
1.4
159
22
1.2
155
13
1.0
150
0
< 1.0
150
0
Slew Rate [V/ns]
Preliminary Data Sheet E1890E20 (Ver. 2.0)
14
EDB4432BABH
1.6.3
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, /CK, or /DQS) has also to comply with
certain requirements for single-ended signals.
CK and /CK shall meet VSEH(AC)min / VSEL(AC)max in every half-cycle.
DQS, /DQS shall meet VSEH(AC)min / VSEL(AC)max in every half-cycle preceeding and following a
valid transition.
Note that the applicable AC-levels for CA and DQ’s are different per speed-bin.
VDDCA or VDDQ
VSEH(AC)min.
VSEH(AC)
VDDCA/2 or VDDQ/2
CK, /CK
DQS, /DQS
VSEL(AC)max.
VSEL(AC)
VSS or VSSQ
time
Figure 4 — Single-ended requirement for differential signals.
Note that while CA and DQ signal requirements are with respect to VREF, the single-ended components
of differential signals have a requirement with respect to VDDQ/2 for DQS, /DQS and VDDCA/2 for CK,
/CK; this is nominally the same. The transition of single-ended signals through the AC-levels is used to
measure setup time. For single-ended components of differential signals the requirement to reach
VSEL(AC)max, VSEH(AC)min has no bearing on timing, but adds a restriction on the common mode
charateristics of these signals.
The signal ended requirements for CK, /CK, DQS and /DQS are found in tables 3 and 5, respectively.
Table 8 Single-ended levels for CK, DQS, /CK, /DQS
Parameter
Single-ended high-level for strobes
Single-ended high-level for CK, /CK
Single-ended low-level for strobes
Single-ended low-level for CK, /CK
Symbol
VSEH(AC)
min.
max.
(VDDQ / 2) + 0.220
Note 3
V
1, 2
(VDDCA / 2) + 0.220
Note 3
V
1, 2
Note 3
(VDDQ / 2) - 0.220
V
1, 2
Note 3
(VDDCA / 2) - 0.220
V
1, 2
VSEL(AC)
Unit Note
Notes: 1. For CK, /CK use VSEH/VSEL(AC) of CA; for strobes (DQS0, /DQS0, DQS1, /DQS1, DQS2, /DQS2,
DQS3, /DQS3) use VIH/VIL(AC) of DQs.
2. VIH(AC)/VIL(AC) for DQs is based on VREFDQ; VSEH(AC)/VSEL(AC) for CA is based on VREFCA; if
a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here
3. These values are not defined, however the single-ended signals CK, /CK, DQS0, /DQS0, DQS1, /DQS1,
DQS2, /DQS2, DQS3, /DQS3 need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and
Undershoot Specifications” on page 21.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
15
EDB4432BABH
1.7
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and
strobe, each cross point voltage of differential input signals (CK, /CK and DQS, /DQS) must meet the
requirements in Table 8. The differential input cross point voltage VIX is measured from the actual cross
point of true and complement signals to the midlevel between of VDD and VSS.
VDDCA or VDDQ
/CK, /DQS
VIX
VDDCA/2 or VDDQ/2
VIX
VIX
CK, DQS
VSS or VSSQ
Figure 5 — VIX Definition
Table 9 Cross point voltage for differential input signals (CK, DQS)
Parameter
Symbol
min.
max.
Unit
Note
Differential Input Cross Point Voltage
relative to VDDCA/2 for CK, /CK
VIXCA
-120
120
mV
1, 2
Differential Input Cross Point Voltage
relative to VDDQ/2 for DQS, /DQS
VIXDQ
-120
120
mV
1, 2
Notes: 1.
The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which
differential input signals must cross.
2. For CK and /CK, VREF = VREFCA(DC). For DQS and /DQS, VREF = VREFDQ(DC).
1.8
Slew Rate Definitions for Single-Ended Input Signals
See “CA and /CS Setup, Hold and Derating” on page 40 for single-ended slew rate definitions for
address and command signals.
See “Data Setup, Hold and Slew Rate Derating” on page 47 for single-ended slew rate definitions for
data signals.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
16
EDB4432BABH
1.9
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, /CK and DQS, /DQS) are defined and measured as shown in
Table 10 and Figure 6.
Table 10 Differential Input Slew Rate Definition
Measured
Description
Defined by
from
to
Differential input slew rate for rising edge
(CK – /CK and DQS – /DQS).
VILdiffmax
VIHdiffmin
[VIHdiffmin - VILdiffmax] / DeltaTRdiff
Differential input slew rate for falling edge
(CK – /CK and DQS – /DQS).
VIHdiffmin
VILdiffmax
[VIHdiffmin - VILdiffmax] / DeltaTFdiff
Note: 1.
The differential signal (i.e. CK – /CK and DQS – /DQS) must be linear between these
thresholds.
Differential Input Vollage (i.e. DQS - /DQS, CK - /CK)
DeltaTRdiff
VIHdiffmin
0
VILdiffmax
DeltaTFdiff
Figure 6 — Differential Input Slew Rate Definition for DQS, /DQS and CK, /CK
Preliminary Data Sheet E1890E20 (Ver. 2.0)
17
EDB4432BABH
1.10 AC and DC Output Measurement Levels
1.10.1 Single Ended AC and DC Output Levels
Table 11 shows the output levels used for measurements of single ended signals.
Table 11 Single-ended AC and DC Output Levels
Parameter
Symbol
Value
DC output high measurement level (for IV curve linearity)
VOH(DC)
0.9 × VDDQ
V
1
DC output low measurement level (for IV curve linearity)
VOL(DC)
0.1 × VDDQ
V
2
AC output high measurement level (for output slew rate)
VOH(AC)
VREFDQ + 0.12
V
AC output low measurement level (for output slew rate)
VOL(AC)
VREFDQ - 0.12
V
min.
-5
A
max.
5
A
min.
-15
%
max.
15
%
Output Leakage current (DQ, DM, DQS, /DQS)
(DQ, DQS, /DQS are disabled; 0V VOUT VDDQ)
IOZ
Delta RON between pull-up and pull-down for DQ/DM
MMPUPD
Unit
Note
Notes: 1. IOH = -0.1mA.
2. IOL = 0.1mA.
1.10.2 Differential AC and DC Output Levels
Table 12 shows the output levels used for measurements of differential signals.
Table 12 Differential AC and DC Output Levels
Parameter
Symbol
Value
Unit
AC differential output high measurement level
(for output SR)
VOHdiff(AC)
+0.2 × VDDQ
V
AC differential output low measurement level
(for output SR)
VOLdiff(AC)
-0.2 × VDDQ
V
Preliminary Data Sheet E1890E20 (Ver. 2.0)
18
Note
EDB4432BABH
1.10.3 Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table 13 and
Figure 7.
Table 13 Single-ended Output Slew Rate Definition
Measured
Description
Defined by
from
to
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)] / DeltaTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)] / DeltaTFse
Note: 1.
Output slew rate is verified by design and characterization, and may not be subject to production test.
Single Ended Output Vollage (i.e. DQ)
DeltaTRse
VOH (AC)
VREF
VOL (AC)
DeltaTFse
Figure 7 — Single Ended Output Slew Rate Definition
Table 14 Output Slew Rate (single-ended)
Parameter
Symbol
min.
max.
Unit
Single-ended Output Slew Rate (RON = 40  30%)
SRQse
1.5
3.5
V/ns
Single-ended Output Slew Rate (RON = 60  30%)
SRQse
1.0
2.5
V/ns
0.7
1.4
Output slew-rate matching Ratio (Pull-up to Pull-down)
Remark:
Notes: 1.
2.
3.
4.
SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output),
se: Single-ended Signals
Measured with output reference load.
The ratio of pull-up to pull-down slew rate is specified for the same temperature and voltage,
over the entire temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pulldown drivers due to process variation.
The output slew rate for falling and rising edges is defined and measured between VOL(AC)
and VOH(AC).
Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte
driving logic high and 1/2 of DQ signals per data byte driving logic low.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
19
EDB4432BABH
1.11 Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined
and measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table 15 and
Figure 8.
Table 15 Differential Output Slew Rate Definition
Measured
Description
from
Differential output slew rate for rising edge
Defined by
to
VOLdiff(AC)
VOHdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTRdiff
Differential output slew rate for falling edge VOHdiff(AC) VOLdiff(AC) [VOHdiff(AC) - VOLdiff(AC)] / DeltaTFdiff
Note: 1.
Output slew rate is verified by design and characterization, and may not be subject to production test.
Differential Output Vollage (i.e. DQS - /DQS)
DeltaTRdiff
VOHdiff(AC)
0
VOLdiff(AC)
DeltaTFdiff
Figure 8 — Differential Output Slew Rate Definition
Table 16 Differential Output Slew Rate
Parameter
Symbol
min.
max.
Unit
Differential Output Slew Rate (RON = 40  30%)
SRQdiff
3.0
7.0
V/ns
Differential Output Slew Rate (RON = 60  30%)
SRQdiff
2.0
5.0
V/ns
Remark:
SR: Slew Rate, Q: Query Output (like in DQ, which stands for Data-in, Query-Output),
diff: Differential Signals
Notes: 1. Measured with output reference load.
2. The output slew rate for falling and rising edges is defined and measured between VOL(AC)
and VOH(AC).
3. Slew rates are measured under normal SSO conditions, with 1/2 of DQ signals per data byte
driving logic high and 1/2 of DQ signals per data byte driving logic low.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
20
EDB4432BABH
1.12 Overshoot and Undershoot Specifications
Table 17 AC Overshoot/Undershoot Specification
Parameter
1066
Unit
Maximum peak amplitude allowed for overshoot area.
max.
0.35
V
Maximum peak amplitude allowed for undershoot area.
max.
0.35
V
Maximum overshoot area above VDD*1.
max.
0.15
V-ns
Maximum undershoot area below VSS*2
max.
0.15
V-ns
Notes: 1.
For CA0 – CA9, CK, /CK, /CS, and CKE, VDD stands for VDDCA. For DQ, DM, DQS, and
/DQS, VDD stands for VDDQ.
2. For CA0 – CA9, CK, /CK, /CS, and CKE, VSS stands for VSS. For DQ, DM, DQS, and /DQS,
VSS stands for VSSQ.
3. Values are referenced from actual VDDQ, VDDCA, VSSQ, and VSS levels.
Maximum Amplitude
Overshoot area
Volts (V)
VDD
VSS
Undershoot area
Time (ns)
Figure 9 — Overshoot and Undershoot Definition
1.13 RONPU and RONPD Resistor Definition
 VDDQ – Vout 
RONPU = -----------------------------------------ABS  Iout 
Note 1: This is under the condition that RONPD is turned off
Vout
RONPD = ----------------------------ABS  Iout 
Note 1: This is under the condition that RONPU is turned off
Chip in Drive Mode
Output Driver
VDDQ
IPU
To
other
circuitry
like
Receiver,
...
RONPU
IOut
RONPD
IPD
DQ
VOut
VSSQ
Figure 10 — Output Driver: Definition of Voltages and Currents
Preliminary Data Sheet E1890E20 (Ver. 2.0)
21
EDB4432BABH
1.13.1 RONPU and RONPD Characteristics with ZQ Calibration
Output driver impedance RON is defined by the value of the external reference resistor RZQ. Nominal
RZQ is 240.
Table 18 Output Driver DC Electrical Characteristics with ZQ Calibration
RONNOM
34.3
40.0
48.0
60.0
80.0
120.0
(optional)
Mismatch between
pull-up and pull-down
Resistor
Vout
min.
nom.
max.
Unit
Note
RON34PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/7
1, 2, 3, 4
RON34PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/7
1, 2, 3, 4
RON40PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/6
1, 2, 3, 4
RON40PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/6
1, 2, 3, 4
RON48PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/5
1, 2, 3, 4
RON48PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/5
1, 2, 3, 4
RON60PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/4
1, 2, 3, 4
RON60PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/4
1, 2, 3, 4
RON80PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/3
1, 2, 3, 4
RON80PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/3
1, 2, 3, 4
RON120PD
0.5 × VDDQ
0.85
1.00
1.15
RZQ/2
1, 2, 3, 4
RON120PU
0.5 × VDDQ
0.85
1.00
1.15
RZQ/2
1, 2, 3, 4
%
1, 2, 3,
4, 5
MMPUPD
-15.00
+15.00
Notes: 1. Across entire operating temperature range, after calibration.
2. RZQ = 240.
3. The tolerance limits are specified after calibration with fixed voltage and temperature.
For behavior of the tolerance limits if temperature or voltage changes after calibration, see
following section on voltage and temperature sensitivity.
4. Pull-down and pull-up output driver impedances are recommended to be calibrated at 0.5 ×
VDDQ.
5. Mesaurement definition for mismatch between pull-up and pull-down,
MMPUPD: Measure RONPU and RONPD, both at 0.5 × VDDQ:
RONPU – RONPD
MMPUPD = ----------------------------------------------------  100
RONNOM
For example, with MMPUPD max.= 15% and RONPD = 0.85, RONPU must be less than 1.0.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
22
EDB4432BABH
1.13.2 Output Driver Temperature and Voltage Sensitivity
If temperature and/or voltage change after calibration, the tolerance limits widen according to the Tables
shown below.
Table 19 Output Driver Sensitivity Definition
Resistor
RONPD
RONPU
Vout
0.5 × VDDQ
min.
max.
Unit
85 - (dRONdT × |T|) - (dRONdV × |V|)
115 + (dRONdT × |T|) + (dRONdV × |V|)
%
Note
1, 2
Notes: 1. T = T - T(@ calibration), V = V - V(@ calibration)
2. dRONdT and dRONdV are not subject to production test but are verified by design and
characterization
Table 20 Output Driver Temperature and Voltage Sensitivity
Parameter
Symbol
min.
max.
Unit
RON Temperature Sensitivity
dRONdT
0
0.75
%/C
RON Voltage Sensitivity
dRONdV
0
0.20
%/mV
Note
1.13.3 RONPU and RONPD Characteristics without ZQ Calibration
Output driver impedance RON is defined by design and characterization as default setting.
Table 21 Output Driver DC Electrical Characteristics without ZQ Calibration
RONNOM
34.3
40.0
48.0
60.0
80.0
120.0
(optional)
Note: 1.
Resistor
Vout
min.
nom.
max.
Unit
Note
RON34PD
0.5 × VDDQ
24
34.3
44.6

1
RON34PU
0.5 × VDDQ
24
34.3
44.6

1
RON40PD
0.5 × VDDQ
28
40
52

1
RON40PU
0.5 × VDDQ
28
40
52

1
RON48PD
0.5 × VDDQ
33.6
48
62.4

1
RON48PU
0.5 × VDDQ
33.6
48
62.4

1
RON60PD
0.5 × VDDQ
42
60
78

1
RON60PU
0.5 × VDDQ
42
60
78

1
RON80PD
0.5 × VDDQ
56
80
104

1
RON80PU
0.5 × VDDQ
56
80
104

1
RON120PD
0.5 × VDDQ
84
120
156

1
RON120PU
0.5 × VDDQ
84
120
156

1
Across entire operating temperature range, without calibration.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
23
EDB4432BABH
2. Electrical Specifications
2.1
IDD Measurement Conditions
The following definitions are used within the IDD measurement tables:
LOW: VIN  VIL(DC) max.
HIGH: VIN  VIH(DC) min.
STABLE: Inputs are stable at a HIGH or LOW level
SWITCHING: See Table 22, 23 and 24.
Table 22 Definition of Switching for CA Input Signals
Switching for CA
CK
CK
CK
CK
CK
CK
CK
CK
(RISING) / (FALLING) / (RISING) / (FALLING) / (RISING) / (FALLING) / (RISING) / (FALLING) /
/CK
/CK
/CK
/CK
/CK
/CK
/CK
/CK
(FALLING)
(RISING)
(FALLING)
(RISING)
(FALLING)
(RISING)
(FALLING)
(RISING)
Cycle
N
N+1
N+2
N+3
/CS
HIGH
HIGH
HIGH
HIGH
CA0
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CA1
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
CA2
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CA3
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
CA4
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CA5
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
CA6
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CA7
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
CA8
HIGH
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
CA9
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
Notes: 1. /CS must always be driven HIGH.
2. 50% of CA bus is changing between HIGH and LOW once per clock for the CA bus.
3. The above pattern (N, N + 1, N + 2, N + 3...) is used continuously during IDD measurement
for IDD values that require SWITCHING on the CA bus.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
24
EDB4432BABH
Table 23 Definition of Switching for IDD4R
Clock
CKE
/CS
Clock Cycle Number
Command
CA0 – CA2
CA3 – CA9
All DQ
Rising
HIGH
LOW
N
Read_Rising
HLH
LHLHLHL
L
Falling
HIGH
LOW
N
Read_Falling
LLL
LLLLLLL
L
Rising
HIGH
HIGH
N+1
NOP
LLL
LLLLLLL
H
Falling
HIGH
HIGH
N+1
NOP
HLH
HLHLLHL
L
Rising
HIGH
LOW
N+2
Read_Rising
HLH
HLHLLHL
H
Falling
HIGH
LOW
N+2
Read_Falling
LLL
HHHHHHH
H
Rising
HIGH
HIGH
N+3
NOP
LLL
HHHHHHH
H
Falling
HIGH
HIGH
N+3
NOP
HLH
LHLHLHL
L
Notes: 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
2. The above pattern (N, N + 1...) is used continuously during IDD measurement for IDD4R.
Table 24 Definition of Switching for IDD4W
Clock
CKE
/CS
Clock Cycle Number
Command
CA0 – CA2
CA3 – CA9
All DQ
Rising
HIGH
LOW
N
Write_Rising
HLL
LHLHLHL
L
Falling
HIGH
LOW
N
Write_Falling
LLL
LLLLLLL
L
Rising
HIGH
HIGH
N+1
NOP
LLL
LLLLLLL
H
Falling
HIGH
HIGH
N+1
NOP
HLH
HLHLLHL
L
Rising
HIGH
LOW
N+2
Write_Rising
HLL
HLHLLHL
H
Falling
HIGH
LOW
N+2
Write_Falling
LLL
HHHHHHH
H
Rising
HIGH
HIGH
N+3
NOP
LLL
HHHHHHH
H
Falling
HIGH
HIGH
N+3
NOP
HLH
LHLHLHL
L
Notes: 1. Data strobe (DQS) is changing between HIGH and LOW every clock cycle.
2. Data masking (DM) must always be driven LOW.
3. The above pattern (N, N + 1...) is used continuously during IDD measurement for IDD4W.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
25
EDB4432BABH
2.2
DC Characteristics 1
(TC = -30C to +85C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V)
Table 25 IDD Specification Parameters and Operating Conditions
Symbol
Power
Supply
1066
Unit
Parameter/Condition
Operating one bank active-pecharge current:
tCK = tCK(avg)min; tRC = tRCmin; CKE is HIGH;
/CS is HIGH between valid commands;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
max.
IDD0_1
VDD1
11
mA
IDD0_2
VDD2
55
mA
IDD0_IN
VDDCA
VDDQ
1.0
mA
IDD2P_1
VDD1
0.4
mA
IDD2P_2
VDD2
0.9
mA
IDD2P_IN
VDDCA
VDDQ
0.1
mA
IDD2PS_1
VDD1
0.4
mA
IDD2PS_2
VDD2
0.9
mA
IDD2PS_IN
VDDCA
VDDQ
0.1
mA
IDD2N_1
VDD1
0.6
mA
IDD2N_2
VDD2
15
mA
IDD2N_IN
VDDCA
VDDQ
1.0
mA
IDD2NS_1
VDD1
0.6
mA
IDD2NS_2
VDD2
7.0
mA
IDD2NS_IN
VDDCA
VDDQ
1.0
mA
IDD3P_1
VDD1
0.7
mA
IDD3P_2
VDD2
5.5
mA
IDD3P_IN
VDDCA
VDDQ
0.1
mA
IDD3PS_1
VDD1
0.7
mA
IDD3PS_2
VDD2
5.5
mA
IDD3PS_IN
VDDCA
VDDQ
0.1
mA
IDD3N_1
VDD1
1.0
mA
IDD3N_2
VDD2
22
mA
IDD3N_IN
VDDCA
VDDQ
1.0
mA
IDD3NS_1
VDD1
1.5
mA
IDD3NS_2
VDD2
15
mA
IDD3NS_IN
VDDCA
VDDQ
1.0
mA
Idle power-down standby current:
tCK = tCK(avg)min; CKE is LOW; /CS is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
Idle power-down standby current with clock stop:
CK = LOW, /CK = HIGH; CKE is LOW; /CS is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
Idle non power-down standby current:
tCK = tCK(avg)min; CKE is HIGH; /CS is HIGH; All banks idle;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
Idle non power-down standby current with clock stop:
CK = LOW, /CK = HIGH; CKE is HIGH; /CS is HIGH; All banks idle;
CA bus inputs are STABLE;
Data bus inputs are STABLE
Active power-down standby current:
tCK = tCK(avg)min; CKE is LOW; /CS is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
Active power-down standby current with clock stop:
CK = LOW, /CK = HIGH; CKE is LOW; /CS is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
Active non power-down standby current:
tCK = tCK(avg)min; CKE is HIGH; /CS is HIGH; One bank active;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE
Active non power-down standby current with clock stop:
CK = LOW, /CK = HIGH; CKE is HIGH; /CS is HIGH; One bank active;
CA bus inputs are STABLE;
Data bus inputs are STABLE
Preliminary Data Sheet E1890E20 (Ver. 2.0)
26
EDB4432BABH
Table 25 IDD Specification Parameters and Operating Conditions (cont’d)
Symbol
Power
Supply
1066
Unit
Parameter/Condition
IDD4R_1
VDD1
2.0
mA
VDD2
190
mA
Operating burst read current:
tCK = tCK(avg)min; /CS is HIGH between valid commands;
One bank active; BL = 4; RL = RLmin;
CA bus inputs are SWITCHING;
50% data change each burst transfer;
IDD4R_2
IDD4W_1
VDD1
2.0
mA
IDD4W_2
VDD2
220
mA
IDD4W_IN
VDDCA
VDDQ
1.0
mA
IDD5_1
VDD1
40
mA
IDD5_2
VDD2
150
mA
IDD5_IN
VDDCA
VDDQ
1.0
mA
IDD5AB_1
VDD1
2.0
mA
IDD5AB_2
VDD2
16
mA
IDD5AB_IN
VDDCA
VDDQ
1.0
mA
IDD5PB_1
VDD1
2.0
mA
IDD5PB_2
VDD2
16
mA
IDD5PB_IN
VDDCA
VDDQ
1.0
mA
max.
Operating burst write current:
tCK = tCK(avg)min; /CS is HIGH between valid commands;
One bank active; BL = 4; WL = WLmin;
CA bus inputs are SWITCHING;
50% data change each burst transfer;
All Bank Auto Refresh Burst current:
tCK = tCK(avg)min; CKE is HIGH between valid commands;
tRC = tRFCabmin; Burst refresh;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
All Bank Auto Refresh Average current:
tCK = tCK(avg)min; CKE is HIGH between valid commands; tRC = tREFI;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
Per Bank Auto Refresh Average current:
tCK = tCK(avg)min; CKE is HIGH between valid commands;
tRC = tREFI/8;
CA bus inputs are SWITCHING;
Data bus inputs are STABLE;
Notes: 1. IDD values published are the maximum of the distribution of the arithmetic mean.
2. IDD current specifications are tested after the device is properly initialized.
Table 26 IDD6 Full and Partial Array Self-Refresh Current
Parameter
Symbol
typ.
max.
Unit
Condition
Self-Refresh Current
IDD6_1
—
450
A
IDD6_2
—
1300
A
IDD6_IN
—
12
A
CK = LOW, /CK = HIGH;
CKE is LOW;
CA bus inputs are STABLE;
Data bus inputs are STABLE;
-30C TC+45C
Full Array
Self-Refresh Current
+45C <TC+85C
Full Array
IDD6_1
—
900
A
IDD6_2
—
3200
A
IDD6_IN
—
12
A
Note: 1. IDD values published are the maximum of the distribution of the arithmetic mean.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
27
EDB4432BABH
2.3
DC Characteristics 2
(TC = -30C to +85C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V)
Table 27 Electrical Characteristics and Operating Conditions
Symbol
min.
max.
Unit
Parameter/Condition
IL
-2
+2
A
Input leakage current:
For CA, CKE, /CS, CK, /CK
Any input 0V  VIN  VDD2 = VDDCA
(All other pins not under test = 0V)
IVREF
-1
+1
A
VREF supply leakage current:
VREFDQ = VDDQ/2 or VREFCA = VDD2/2 = VDDCA/2
(All other pins not under test = 0V)
Note
2
1
Notes: 1. The minimum limit requirement is for testing purposes. The leakage current on VREFCA and VREFDQ
pins should be minimal.
2. Although DM is for input only, the DM leakage shall match the DQ and DQS, /DQS output leakage
specification.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
28
EDB4432BABH
2.4
Clock Specification
The jitter specified is a random jitter meeting a Gaussian distribution. Input clocks violating the min/max
values may result in malfunction of the DDR2 Mobile RAM device.
2.4.1
Definition for tCK(avg) and nCK
tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window, where
each clock period is calculated from rising edge to rising edge.
N



tCK  avg  =
tCK j  N


j = 


N = 
where
Unit ‘tCK(avg)’ represents the actual clock average tCK(avg) of the input clock under operation. Unit
‘nCK’ represents one clock cycle of the input clock, counting the actual clock edges.
tCK(avg) may change by up to +/-1% within a 100 clock cycle window, provided that all jitter and timing
specs are met.
2.4.2
Definition for tCK(abs)
tCK(abs) is defined as the absolute clock period, as measured from one rising edge to the next
consecutive rising edge. tCK(abs) is not subject to production test.
2.4.3
Definition for tCH(avg) and tCL(avg)
tCH(avg) is defined as the average high pulse width, as calculated across any consecutive 200 high
pulses.
N



tCH  avg  =
tCH j   N  tCK  avg  


j = 


N = 
where
tCL(avg) is defined as the average low pulse width, as calculated across any consecutive 200 low
pulses.
N



tCL  avg  =
tCL j   N  tCK  avg  


j = 


N = 
where
Preliminary Data Sheet E1890E20 (Ver. 2.0)
29
EDB4432BABH
2.4.4
Definition for tJIT(per)
tJIT(per) is the single period jitter defined as the largest deviation of any signal tCK from tCK(avg).
tJIT(per) = Min/max of {tCKi - tCK(avg) where i = 1 to 200}.
tJIT(per),act is the actual clock jitter for a given system.
tJIT(per),allowed is the specified allowed clock period jitter.
tJIT(per) is not subject to production test.
2.4.5
Definition for tJIT(cc)
tJIT(cc) is defined as the absolute difference in clock period between two consecutive clock cycles.
tJIT(cc) = Max of |{tCKi +1 - tCKi}|.
tJIT(cc) defines the cycle to cycle jitter.
tJIT(cc) is not subject to production test.
2.4.6
Definition for tERR(nper)
tERR(nper) is defined as the cumulative error across n multiple consecutive cycles from tCK(avg).
tERR(nper), act is the actual clock jitter over n cycles for a given system.
tERR(nper), allowed is the specified allowed clock period jitter over n cycles.
tERR(nper) is not subject to production test.
i+n–



tERR  nper  =
tCK j – n  tCK  avg 


 j=i


tERR(nper),min can be calculated by the formula shown below:
tERR  nper  min =   + LN  n    tJIT  per  min
tERR(nper),max can be calculated by the formula shown below:
tERR  nper  max =   + LN  n    tJIT  per  max
Using these equations, tERR(nper) tables can be generated for each tJIT(per),act value.
2.4.7
Definition for duty cycle jitter tJIT(duty)
tJIT(duty) is defined with absolute and average specification of tCH / tCL.
tJIT  duty  min = MIN   tCH  abs  min – tCH  avg  min   tCL  abs  min – tCL  avg  min    tCK  avg 
tJIT  duty  max = MAX   tCH  abs  max – tCH  avg  max   tCL  abs  max – tCL  avg  max    tCK  avg 
2.4.8
Definition for tCK(abs), tCH(abs) and tCL(abs)
These parameters are specified per their average values, however it is understood that the following
relationship between the average timing and the absolute instantaneous timing holds at all times.
Table 28 Definition for tCK(abs), tCH(abs), and tCL(abs)
Parameter
Absolute Clock Period
Symbol
Min
tCK(abs)
tCK(avg),min + tJIT(per),min
Absolute Clock HIGH Pulse Width
tCH(abs)
tCH(avg),min + tJIT(duty),min / tCK(avg)min
tCK(avg)
Absolute Clock LOW Pulse Width
tCL(abs)
tCL(avg),min + tJIT(duty),min / tCK(avg)min
tCK(avg)
Notes: 1. tCK(avg),min is expressed is ps for this table.
2. tJIT(duty),min is a negative value.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
30
Unit
ps
EDB4432BABH
2.5
Period Clock Jitter
DDR2 Mobile RAM devices can tolerate some clock period jitter without core timing parameter de-rating.
This section describes device timing requirements in the presence of clock period jitter (tJIT(per)) in
excess of the values found in Table 29 on page 34 and how to determine cycle time de-rating and clock
cycle de-rating.
2.5.1 Clock period jitter effects on core timing parameters (tRCD, tRP, tRTP, tWR, tWRA, tWTR,
tRC, tRAS, tRRD, tFAW )
Core timing parameters extend across multiple clock cycles. Period clock jitter will impact these
parameters when measured in numbers of clock cycles. When the device is operated with clock jitter
within the specification limits, the DDR2 Mobile RAM device is characterized and verified to support
tnPARAM = RU{tPARAM / tCK(avg)}.
When the device is operated with clock jitter outside specification limits, the number of clocks or tCK(avg)
may need to be increased based on the values for each core timing parameter.
2.5.1.1 Cycle time de-rating for core timing parameters
For a given number of clocks (tnPARAM), for each core timing parameter, average clock period
(tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative
period error (tERR(tnPARAM),allowed), the equation below calculates the amount of cycle time de-rating
(in ns) required if the equation results in a positive value for a core timing parameter (tCORE).
 tPARAM + tERR  tnPARAM  act – tERR  tnPARAM  allowed

CycleTimeDerating = MAX   ----------------------------------------------------------------------------------------------------------------------------------------------------------------- – tCK  avg    
tnPARAM


A cycle time derating analysis should be conducted for each core timing parameter. The amount of cycle
time derating required is the maximum of the cycle time de-ratings determined for each individual core
timing parameter.
2.5.1.2 Clock Cycle de-rating for core timing parameters
For a given number of clocks (tnPARAM) for each core timing parameter, clock cycle de-rating should be
specified with amount of period jitter (tJIT(per)).
For a given number of clocks (tnPARAM), for each core timing parameter, average clock period
(tCK(avg)) and actual cumulative period error (tERR(tnPARAM),act) in excess of the allowed cumulative
period error (tERR(tnPARAM),allowed), the equation below calculates the clock cycle derating (in clocks)
required if the equation results in a positive value for a core timing parameter (tCORE).
 tPARAM + tERR  tnPARAM  act – tERR  tnPARAM  allowed 
ClockCycleDerating = RU  -----------------------------------------------------------------------------------------------------------------------------------------------------------------  – tnPARAM
tCK  avg 


A clock cycle de-rating analysis should be conducted for each core timing parameter.
2.5.2 Clock jitter effects on Command/Address timing parameters (tIS, tIH, tISCKE, tIHCKE, tISb,
tIHb, tISCKEb, tIHCKEb)
These parameters are measured from a command/address signal (CKE, CS, CA0 – CA9) transition edge
to its respective clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock
jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the
command/address. Regardless of clock jitter values, these values shall be met.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
31
EDB4432BABH
2.5.3
Clock jitter effects on Read timing parameters
2.5.3.1 tRPRE
When the device is operated with input clock jitter, tRPRE needs to be de-rated by the actual period jitter
(tJIT(per),act,max) of the input clock in excess of the period jitter (tJIT(per),allowed,max). Output deratings are relative to the input clock.
tJIT  per  act ,max – tJIT  per  ,allowed ,max
tRPRE  min derated  =  –  ------------------------------------------------------------------------------------------------------------------


tCK  avg 
For example,
if the measured jitter into a DDR2 Mobile RAM-800 device has tCK(avg) = 2500 ps, tJIT(per),act,min
= -172 ps and tJIT(per),act,max= + 193 ps, then
tRPRE,min,derated = 0.9 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 0.9 - (193 - 100)/2500=
0.8628 tCK(avg)
2.5.3.2 tLZ(DQ), tHZ(DQ), tDQSCK, tLZ(DQS), tHZ(DQS)
These parameters are measured from a specific clock edge to a data signal (DMn, DQm.: n=0,1,2,3.
m=0 –31) transition and will be met with respect to that clock edge. Therefore, they are not affected by
the amount of clock jitter applied (i.e. tJIT(per).
2.5.3.3 tQSH, tQSL
These parameters are affected by duty cycle jitter which is represented by tCH(abs)min and
tCL(abs)min. Therefore tQSH(abs)min and tQSL(abs)min can be specified with tCH(abs)min and
tCL(abs)min.
tQSH(abs)min = tCH(abs)min - 0.05
tQSL(abs)min = tCL(abs)min - 0.05
These parameters determine absolute Data-Valid window at the DDR2 Mobile RAM device pin.
Absolute min data-valid window @ DDR2 Mobile RAM device pin =
min { ( tQSH(abs)min × tCK(avg)min - tDQSQmax - tQHSmax ) , ( tQSL(abs)min × tCK(avg)min tDQSQmax - tQHSmax ) }
This minimum data-valid window shall be met at the target frequency regardless of clock jitter.
2.5.3.4 tRPST
tRPST is affected by duty cycle jitter which is represented by tCL(abs). Therefore tRPST(abs)min can be
specified by tCL(abs)min.
tRPST(abs)min = tCL(abs)min - 0.05 = tQSL(abs)min
Preliminary Data Sheet E1890E20 (Ver. 2.0)
32
EDB4432BABH
2.5.4
Clock jitter effects on Write timing parameters
2.5.4.1 tDS, tDH
These parameters are measured from a data signal (DMn, DQm.: n=0,1,2,3. m=0 –31) transition edge to
its respective data strobe signal (DQSn, /DQSn : n=0,1,2,3) crossing. The spec values are not affected
by the amount of clock jitter applied (i.e. tJIT(per), as the setup and hold are relative to the clock signal
crossing that latches the command/address. Regardless of clock jitter values, these values shall be met.
2.5.4.2 tDSS, tDSH
These parameters are measured from a data strobe signal (DQSx, /DQSx) crossing to its respective
clock signal (CK, /CK) crossing. The spec values are not affected by the amount of clock jitter applied
(i.e. tJIT(per), as the setup and hold are relative to the clock signal crossing that latches the
command/address. Regardless of clock jitter values, these values shall be met.
2.5.4.3 tDQSS
This parameter is measured from a data strobe signal (DQSx, /DQSx) crossing to the subsequent clock
signal (CK, /CK) crossing. When the device is operated with input clock jitter, this parameter needs to be
de-rated by the actual tJIT(per),act of the input clock in excess of the period jitter tJIT(per),allowed.
tJIT  per  act ,min – tJIT  per  ,allowed ,min
tDQSS  min derated  =  – ---------------------------------------------------------------------------------------------------------------tCK  avg 
tJIT  per  act ,max – tJIT  per  ,allowed ,max
tDQSS  max derated  =  – -----------------------------------------------------------------------------------------------------------------tCK  avg 
For example,
if the measured jitter into a LPDDR2-800 device has tCK(avg)= 2500 ps, tJIT(per),act,min= -172 ps and
tJIT(per),act,max= + 193 ps, then
tDQSS,(min,derated) = 0.75 -(tJIT(per),act,min - tJIT(per),allowed,min)/tCK(avg) = 0.75 - (-172 + 100)
/2500 = 0.7788 tCK(avg)
and
tDQSS,(max,derated) = 1.25 - (tJIT(per),act,max - tJIT(per),allowed,max)/tCK(avg) = 1.25 - (193 - 100)
/2500 = 1.2128 tCK(avg)
Preliminary Data Sheet E1890E20 (Ver. 2.0)
33
EDB4432BABH
2.6
AC Characteristics
(TC = -30C to +85C, VDD1 = 1.70V to 1.95V, VDD2, VDDCA, VDDQ = 1.14V to 1.30V)
Table 29 AC Characteristics Table*6
Parameter
Symbol
min. min.
max. tCK*9
Max. Frequency*4
1066
Unit
—
533
MHz
min.
—
1.875
ns
max.
—
100
ns
min.
—
0.45
max.
—
0.55
min.
—
0.45
max.
—
0.55
Clock Timing
Average Clock Period
tCK(avg)
Average high pulse width
tCH(avg)
Average low pulse width
tCL(avg)
Absolute Clock Period
tCK(abs)
min.
—
tCK(avg)(min.) + tJIT(per)(min.)
Absolute clock HIGH pulse width
(with allowed jitter)
tCH(abs),
allowed
min.
—
0.43
max.
—
0.57
Absolute clock LOW pulse width
(with allowed jitter)
tCL(abs),
allowed
min.
—
0.43
max.
—
0.57
Clock Period Jitter (with allowed jitter)
tJIT(per),
allowed
min.
—
-90
max.
—
90
Maximum Clock Jitter between two
consecutive clock cycles (with allowed jitter)
tJIT(cc),
allowed
max.
—
180
min.
—
min((tCH(abs),min tCH(avg),min), (tCL(abs),min tCL(avg),min)) × tCK(avg)
max.
—
max((tCH(abs),max tCH(avg),max), (tCL(abs),max tCL(avg),max)) × tCK(avg)
Duty cycle Jitter (with allowed jitter)
tJIT(duty),
allowed
Cumulative error across 2 cycles
tERR(2per),
allowed
min.
—
-132
max.
—
132
Cumulative error across 3 cycles
tERR(3per),
allowed
min.
—
-157
max.
—
157
Cumulative error across 4 cycles
tERR(4per),
allowed
min.
—
-175
max.
—
175
Cumulative error across 5 cycles
tERR(5per),
allowed
min.
—
-188
max.
—
188
Cumulative error across 6 cycles
tERR(6per),
allowed
min.
—
-200
max.
—
200
Cumulative error across 7 cycles
tERR(7per),
allowed
min.
—
-209
max.
—
209
Preliminary Data Sheet E1890E20 (Ver. 2.0)
34
tCK(avg)
tCK(avg)
ps
tCK(avg)
tCK(avg)
ps
ps
ps
ps
ps
ps
ps
ps
ps
EDB4432BABH
Table 29 AC Characteristics Table*6 (cont’d)
Parameter
Symbol
min. min.
max. tCK*9
1066
Cumulative error across 8 cycles
tERR(8per),
allowed
min.
—
-217
max.
—
217
Cumulative error across 9 cycles
tERR(9per),
allowed
min.
—
-224
max.
—
224
Cumulative error across 10 cycles
tERR(10per), min.
allowed
max.
—
-231
—
231
Cumulative error across 11 cycles
tERR(11per), min.
allowed
max.
—
-237
—
237
Cumulative error across 12 cycles
tERR(12per), min.
allowed
max.
—
-242
—
242
min.
—
tERR(nper),allowed,min. =
(1 + 0.68ln(n)) ×
tJIT(per),allowed,min.
max.
—
tERR(nper),allowed,max. =
(1 + 0.68ln(n)) ×
tJIT(per),allowed,max.
min.
—
2500
max.
—
5500
Cumulative error across n = 13, 14
. . . 49, 50 cycles
tERR(nper),
allowed
Unit
ps
ps
ps
ps
ps
ps
Read Parameters
DQS output access time from CK, /CK
tDQSCK
DQSCK Delta Short*15
tDQSCKDS
max.
—
330
ps
DQSCK Delta Medium*16
tDQSCKDM
max.
—
680
ps
DQSCK Delta Long*17
tDQSCKDL
max.
—
920
ps
DQS – DQ skew
tDQSQ
max.
—
200
ps
Data hold skew factor
tQHS
max.
—
230
ps
DQS Output High Pulse Width
tQSH
min.
—
tCH(abs) - 0.05
tCK(avg)
DQS Output Low Pulse Width
tQSL
min.
—
tCL(abs) - 0.05
tCK(avg)
Data Half Period
tQHP
min.
—
min(tQSH, tQSL)
tCK(avg)
DQ / DQS output hold time from DQS
tQH
min.
—
tQHP - tQHS
Read preamble*12,*13
tRPRE
min.
—
0.9
tCK(avg)
Read postamble*12,*14
tRPST
min.
—
tCL(abs) - 0.05
tCK(avg)
DQS low-Z from clock*12
tLZ(DQS)
min.
—
tDQSCK(min.) - 300
ps
DQ low-Z from clock*12
tLZ(DQ)
min.
—
tDQSCK(min.) (1.4 × tQHS(max.))
ps
DQS high-Z from clock*12
tHZ(DQS)
max.
—
tDQSCK(max.) - 100
ps
DQ high-Z from clock*12
tHZ(DQ)
max.
—
tDQSCK(max.) +
(1.4 × tDQSQ(max.))
ps
Preliminary Data Sheet E1890E20 (Ver. 2.0)
35
ps
ps
EDB4432BABH
Table 29 AC Characteristics Table*6 (cont’d)
Parameter
Symbol
min. min.
max. tCK*9
1066
Unit
Write Parameters*11
DQ and DM input hold time (VREF based)
tDH
min.
—
210
ps
DQ and DM input setup time (VREF based)
tDS
min.
—
210
ps
DQ and DM input pulse width
tDIPW
min.
—
0.35
tCK(avg)
Write command to 1st DQS latching transition
tDQSS
min.
—
0.75
max.
—
1.25
DQS input high-level width
tDQSH
min.
—
0.4
tCK(avg)
DQS input low-level width
tDQSL
min.
—
0.4
tCK(avg)
DQS falling edge to CK setup time
tDSS
min.
—
0.2
tCK(avg)
DQS falling edge hold time from CK
tDSH
min.
—
0.2
tCK(avg)
Write postamble
tWPST
min.
—
0.4
tCK(avg)
Write preamble
tWPRE
min.
—
0.35
tCK(avg)
CKE min. pulse width (high and low pulse width)
tCKE
min.
3
3
tCK(avg)
CKE input setup time
tISCKE*2
min.
—
0.25
tCK(avg)
CKE input hold time
tIHCKE*3
min.
—
0.25
tCK(avg)
Address and control input setup time
(VREF based)
tIS*1
min.
—
220
ps
Address and control input hold time
(VREF based)
tIH*1
min.
—
220
ps
Address and control input pulse width
tIPW
min.
—
0.40
tCK(avg)
max.
—
100
min.
—
18
tCK(avg)
CKE Input Parameters
Command Address Input Parameters*11
Boot Parameters (10 MHz – 55 MHz)*5,*7,*8
Clock Cycle Time
tCKb
ns
CKE Input Setup Time
tISCKEb
min.
—
2.5
ns
CKE Input Hold Time
tIHCKEb
min.
—
2.5
ns
Address & Control Input Setup Time
tISb
min.
—
1150
ps
Address & Control Input Hold Time
tIHb
min.
—
1150
ps
DQS Output Data Access Time from
CK, /CK
tDQSCKb
min.
—
2.0
max.
—
10.0
Data Strobe Edge to Ouput Data Edge
tDQSQb - 1.2
tDQSQb
max.
—
1.2
ns
Data Hold Skew Factor
tQHSb
max.
—
1.2
ns
Mode Register Write command period
tMRW
min.
5
5
tCK(avg)
Mode Register Read command period
tMRR
min.
2
2
tCK(avg)
ns
Mode Register Parameters
Preliminary Data Sheet E1890E20 (Ver. 2.0)
36
EDB4432BABH
Table 29 AC Characteristics Table*6 (cont’d)
Parameter
Symbol
min. min.
max. tCK*9
1066
Unit
DDR2 Mobile RAM Core Parameters*9
Read Latency
RL
min.
3
8
tCK(avg)
Write Latency
WL
min.
1
4
tCK(avg)
ACTIVE to ACTIVE command period
tRC
min.
—
tRAS + tRPab
(with all-bank Precharge)
tRAS + tRPpb
(with per-bank Precharge)
ns
CKE min. pulse width during Self-Refresh
(low pulse width during Self-Refresh)
tCKESR
min.
3
15
ns
Self-refresh exit to next valid command delay
tXSR
min.
2
tRFCab + 10
ns
Exit power down to next valid command delay
tXP
min.
2
7.5
ns
CAS to CAS delay
tCCD
min.
2
2
tCK(avg)
Internal Read to Precharge command delay
tRTP
min.
2
7.5
ns
RAS to CAS Delay
tRCD
min.
3
18
ns
Row Precharge Time (single bank)
tRPpb
min.
3
18
ns
Row Precharge Time (all banks)
tRPab
min.
3
21
ns
Row Active Time
tRAS
min.
3
42
ns
max.
—
70
s
Write Recovery Time
tWR
min.
3
15
ns
Internal Write to Read Command Delay
tWTR
min.
2
7.5
ns
Active bank A to Active bank B
tRRD
min.
2
10
ns
Four Bank Activate Window
tFAW
min.
8
50
ns
Refresh Window
tREFW
max.
—
32
ms
Required number of REFRESH commands
R
min.
—
8192
Average time between REFRESH commands
(for reference only)
tREFI
max.
—
3.9
s
tREFIpb
max.
—
0.4875
s
Refresh Cycle time
tRFCab
min.
—
130
ns
Per Bank Refresh Cycle time
tRFCpb
min.
—
60
ns
Burst Refresh Window
= 4 × 8 × tRFCab
tREFBW
min.
—
4.16
s
Initialization Calibration Time
tZQINIT
min.
—
1
s
Long Calibration Time
tZQCL
min.
6
360
ns
Short Calibration Time
tZQCS
min.
6
90
ns
Calibration Reset Time
tZQRESET
min.
3
50
ns
DDR2 Mobile RAM Refresh Requirement Parameters
ZQ Calibration Parameters*9
Preliminary Data Sheet E1890E20 (Ver. 2.0)
37
EDB4432BABH
Notes: 1. Input set-up/hold time for signal(CA0 – CA9, /CS).
2. CKE input setup time is measured from CKE reaching high/low voltage level to CK, /CK crossing.
3. CKE input hold time is measured from CK, /CK crossing to CKE reaching high/low voltage level.
4. Frequency values are for reference only. Clock cycle time (tCK) shall be used to determine device capabilities.
5. To guarantee device operation before the DDR2 Mobile RAM Device is configured a number of AC boot
timing parameters are defined in the Table 29 on page 34. Boot parameter symbols have the letter b
appended, e.g. tCK during boot is tCKb.
6. Frequency values are for reference only. Clock cycle time (tCK or tCKb) shall be used to determine
device capabilities.
7. The DDR2 Mobile RAM will set some Mode register default values upon receiving a RESET (MRW) command as specified in “Mode Register Definition” on page 63.
8. The output skew parameters are measured with Ron default settings into the reference load.
9. These parameters should be satisfied with both specification, analog (ns) value and min. tCK.
10. All AC timings assume an input slew rate of 1V/ns.
11. Read, Write, and Input Setup and Hold values are referenced to VREF.
12. For low-to-high and high-to-low transitions the timing reference will be at the point when the signal
crosses VTT. tHZ and tLZ transitions occur in the same access time (with respect to clock) as valid data
transitions. These parameters are not referenced to a specific voltage level but to the time when the
device output is no longer driving (for tRPST, tHZ(DQS) and tHZ(DQ) ), or begins driving (for tRPRE,
tLZ(DQS), tLZ(DQ) ). Figure 11 shows a method to calculate the point when device is no longer driving
tHZ(DQS) and tHZ(DQ), or begins driving tLZ(DQS), tLZ(DQ) by measuring the signal at two different
voltages. The actual voltage measurement points are not critical as long as the calculation is consistent.
VOH
X
VOH - X mV
2x X
VTT + 2x Y mV
VTT + Y mV
VOH - 2x X mV
tLZ(DQS), tLZ(DQ)
VTT
VTT
Y
actual waveform
2x Y
VTT - Y mV
tHZ(DQS), tHZ(DQ)
VOL + 2x X mV
VTT - 2x Y mV
VOL + X mV
T1 T2
VOL
T1 T2
stop driving point = 2 x T1 - T2
begin driving point = 2 x T1 - T2
Figure 11 — tLZ and tHZ Method for Calculating Transition and Endpoints
The parameters tLZ(DQS), tLZ(DQ), tHZ(DQS), and tHZ(DQ) are defined as single-ended. The
timing parameters tRPRE and tRPST are determined from the differential signal DQS-/DQS.
13. Measured from the start driving of DQS – /DQS to the start driving the first rising strobe edge.
14. Measured from the from start driving the last falling strobe edge to the stop driving DQS – /DQS.
15. tDQSCKDS is the absolute value of the difference between any two tDQSCK measurements (within a
byte lane) within a contiguous sequence of bursts within a 160ns rolling window. tDQSCKDS is not tested
and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock
jitter.
16. tDQSCKDM is the absolute value of the difference between any two tDQSCK measurements (within a
byte lane) within a 1.6s rolling window. tDQSCKDM is not tested and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock jitter.
17. tDQSCKDL is the absolute value of the difference between any two tDQSCK measurements (within a
byte lane) within a 32ms rolling window. tDQSCKDL is not tested and is guaranteed by design. Temperature drift in the system is < 10C/s. Values do not include clock jitter.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
38
EDB4432BABH
2.6.1
HSUL_12 Driver Output Timing Reference Load
These ‘Timing Reference Loads’ are not intended as a precise representation of any particular system
environment or a depiction of the actual load presented by a production tester. System designers should
use IBIS or other simulation tools to correlate the timing reference load to a system environment.
Manufacturers correlate to their production test conditions, generally one or more coaxial transmission
lines terminated at the tester electronics.
VREF
0.5 x VDDQ
DDR2
Mobile RAM
RTT = 50 
Output
VTT = 0.5 x VDDQ
Cload = 5pF
Figure 12 — HSUL_12 Driver Output Reference Load for Timing and Slew Rate
Note: 1. All output timing parameter values (like tDQSCK, tDQSQ, tQHS, tHZ, tRPRE etc) are
reported with respect to this reference load. This reference load is also used to report slew
rate.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
39
EDB4432BABH
2.7
CA and /CS Setup, Hold and Derating
For all input signals (CA and /CS) the total tIS (setup time) and tIH (hold time) required is calculated by
adding the data sheet tIS(base) andtIH(base) value (see Table 30) to the tIS and tIH derating value
(see Table 31) respectively. Example: tIS (total setup time) = tIS(base) + tIS
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max. If
the actual signal is always earlier than the nominal slew rate line between shaded ‘VREF(DC) to AC
region’, use nominal slew rate for derating value (see Figure 13). If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(DC) to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for derating value (see Figure 15).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). Hold (tIH) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ‘DC to VREF(DC)
region’, use nominal slew rate for derating value (see Figure 14). If the actual signal is earlier than the
nominal slew rate line anywhere between shaded ‘DC to VREF(DC) region’, the slew rate of a tangent
line to the actual signal from the DC level to VREF(DC) level is used for derating value (see Figure 16).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see
Table 32). Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will
not have reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required
to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table 30, the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 30 CA and /CS Setup and Hold Base-Values for 1V/ns
Note: 1.
Unit [ps]
1066
Reference
tIS(base)
0
VIH/L(AC)=VREF(DC) ± 220mV
tIH(base)
90
VIH/L(DC)=VREF(DC) ± 130mV
AC/DC referenced for 1V/ns CA and /CS slew rate and 2 V/ns differential CK – /CK slew rate.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
40
EDB4432BABH
Table 31 Derating values DDR2 Mobile RAM tIS/tIH - AC/DC based AC220
tIS, tIH derating in [ps] AC/DC based a
AC220 Threshold -> VIH(AC)=VREF(DC)+220mV, VIL(AC)=VREF(DC)-220mV
DC130 Threshold -> VIH(DC)=VREF(DC)+130mV, VIL(DC)=VREF(DC)-130mV
CK,/CK Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH
CA,
/CS
Slew
rate
V/ns
2.0
110
65
110
65
110
65
1.5
74
43
74
43
74
43
89
59
1.0
0
0
0
0
0
0
16
16
32
32
-3
-5
-3
-5
13
11
29
27
-8
-13
8
3
24
19
40
35
56
55
2
-6
18
10
34
26
50
46
66
78
10
-3
26
13
42
33
58
65
4
-4
20
16
36
48
-7
2
17
34
0.9
0.8
0.7
0.6
0.5
0.4
a. Cell contents blanked are defined as ‘not supported’.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
41
45
43
EDB4432BABH
Table 32 Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition
tVAC @ 220mV [ps]
Slew Rate [V/ns]
min.
max.
> 2.0
175
—
2.0
170
—
1.5
167
—
1.0
163
—
0.9
162
—
0.8
161
—
0.7
159
—
0.6
155
—
0.5
150
—
< 0.5
150
—
Preliminary Data Sheet E1890E20 (Ver. 2.0)
42
EDB4432BABH
/CK
CK
tIS
tIS
tIH
tIH
VDD2
VDDCA
tVAC
VIH(AC) min
VREF to AC
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal
slew rate
VIL(DC) max
VREF to AC
region
VIL(AC) max
tVAC
VSS
TR
TF
VREF(DC) - VIL(AC)max
Setup Slew Rate
=
Falling Signal
TF
VIH(AC)min - VREF(DC)
Setup Slew Rate
=
Rising Signal
TR
Figure 13 — Illustration of nominal slew rate and tVAC for setup time tIS
for CA and /CS with respect to clock.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
43
EDB4432BABH
/CK
CK
tIS
tIS
tIH
tIH
VDD2
VDDCA
VIH(AC) min
VIH(DC) min
DC to VREF
region
nominal
slew rate
VREF(DC)
nominal
slew rate
DC to VREF
region
VIL(DC) max
VIL(AC) max
VSS
TF
TR
VREF(DC) - VIL(DC)max
Hold Slew Rate
=
Rising Signal
TR
Hold Slew Rate
=
Falling Signal
VIH(DC)min- VREF(DC)
Figure 14 — Illustration of nominal slew rate for hold time tIH
for CA and /CS with respect to clock
Preliminary Data Sheet E1890E20 (Ver. 2.0)
44
TF
EDB4432BABH
/CK
CK
tIS
tIS
tIH
VDD2
VDDCA
nominal
line
tIH
tVAC
VIH(AC) min
VREF to AC
region
VIH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VREF to AC
region
VIL(AC) max
nominal
line
TR
tVAC
VSS
tangent line [ VIH(AC)min - VREF(DC) ]
Setup Slew Rate
=
Rising Signal
TR
TF
Setup Slew Rate
tangent line [ VREF(DC) - VIL(AC)max ]
Falling Signal =
TF
Figure 15 — Illustration of tangent line for setup time tIS
for CA and /CS with respect to clock
Preliminary Data Sheet E1890E20 (Ver. 2.0)
45
EDB4432BABH
/CK
CK
tIS
tIS
tIH
tIH
VDD2
VDDCA
VIH(AC) min
nominal
line
VIH(DC) min
DC to VREF
region
tangent
line
VREF(DC)
DC to VREF
region
tangent
line
nominal
line
VIL(DC) max
VIL(AC) max
VSS
TR
TF
tangent line [ VREF(DC) - VIL(DC)max ]
Hold Slew Rate
Rising Signal =
TR
Hold Slew Rate
tangent line [ VIH(DC)min - VREF(DC) ]
Falling Signal =
TF
Figure 16 — Illustration of tangent line for hold time tIH
for CA and /CS with respect to clock
Preliminary Data Sheet E1890E20 (Ver. 2.0)
46
EDB4432BABH
2.8
Data Setup, Hold and Slew Rate Derating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the
data sheet tDS(base) and tDH(base) value (see Table 33) to the tDS and tDH (see Table 34) derating
value respectively. Example: tDS (total setup time) = tDS(base) + tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIH(AC)min. Setup (tDS) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VREF(DC) and the first crossing of VIL(AC)max
(see Figure 17). If the actual signal is always earlier than the nominal slew rate line between shaded
‘VREF(DC) to ac region’, use nominal slew rate for derating value. If the actual signal is later than the
nominal slew rate line anywhere between shaded ‘VREF(DC) to AC region’, the slew rate of a tangent
line to the actual signal from the AC level to DC level is used for derating value (see Figure 19).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(DC)max and the first crossing of VREF(DC). Hold (tDH) nominal slew rate for a falling signal is
defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC)
(see Figure 18). If the actual signal is always later than the nominal slew rate line between shaded ‘DC
level to VREF(DC) region’, use nominal slew rate for derating value. If the actual signal is earlier than the
nominal slew rate line anywhere between shaded ‘DC to VREF(DC) region’, the slew rate of a tangent
line to the actual signal from the DC level to VREF(DC) level is used for derating value (see Figure 20).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see
Table 35).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have
reached VIH/IL(AC) at the time of the rising clock transition) a valid input signal is still required to
complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in the tables the derating values may obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and
characterization.
Table 33 Data Setup and Hold Base-Values
Note: 1.
Unit [ps]
1066
Reference
tDS(base)
-10
VIH/L(AC)=VREF(DC) ± 220mV
tDH(base)
80
VIH/L(DC)=VREF(DC) ± 130mV
AC/DC referenced for 1V/ns DQ slew rate and 2 V/ns differential DQS – /DQS slew rate.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
47
EDB4432BABH
Table 34 Derating values DDR2 Mobile RAM tDS/tDH - AC/DC based AC220
tDS, DH derating in [ps] AC/DC based a
AC220 Threshold -> VIH(AC)=VREF(DC)+220mV, VIL(AC)=VREF(DC)-220mV
DC130 Threshold -> VIH(DC)=VREF(DC)+130mV, VIL(DC)=VREF(DC)-130mV
DQS, /DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH tDS tDH
DQ
Slew
rate
V/ns
2.0
110
65
110
65
110
65
1.5
74
43
73
43
73
43
89
59
1.0
0
0
0
0
0
0
16
16
32
32
-3
-5
-3
-5
13
11
29
27
45
43
-8
-13
8
3
24
19
40
35
56
55
2
-6
18
10
34
26
50
46
66
78
10
-3
26
13
42
33
58
65
4
-4
20
16
36
48
-7
2
17
34
0.9
0.8
0.7
0.6
0.5
0.4
a. Cell contents blanked are defined as ‘not supported’.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
48
EDB4432BABH
Table 35 Required time tVAC above VIH(AC) {below VIL(AC)} for valid transition
tVAC @ 220mV [ps]
Slew Rate [V/ns]
min.
max.
> 2.0
175
—
2.0
170
—
1.5
167
—
1.0
163
—
0.9
162
—
0.8
161
—
0.7
159
—
0.6
155
—
0.5
150
—
< 0.5
150
—
Preliminary Data Sheet E1890E20 (Ver. 2.0)
49
EDB4432BABH
/DQS
DQS
tDS
tDS
tDH
tDH
VDDQ
tVAC
VIH(AC) min
VREF to AC
region
VIH(DC) min
nominal
slew rate
VREF(DC)
nominal
slew rate
VIL(DC) max
VREF to AC
region
VIL(AC) max
tVAC
VSSQ
TF
TR
Setup Slew Rate
VREF(DC) - VIL(AC)max
=
Falling Signal
TF
Setup Slew Rate
Rising Signal =
VIH(AC)min - VREF(DC)
TR
Figure 17 — Illustration of nominal slew rate and tVAC for setup time tDS
for DQ with respect to strobe
Preliminary Data Sheet E1890E20 (Ver. 2.0)
50
EDB4432BABH
/DQS
DQS
tDS
tDS
tDH
tDH
VDDQ
VIH(AC) min
VIH(DC) min
DC to VREF
region
nominal
slew rate
VREF(DC)
nominal
slew rate
DC to VREF
region
VIL(DC) max
VIL(AC) max
VSSQ
TF
TR
Hold Slew Rate
VREF(DC) - VIL(DC)max
=
Rising Signal
TR
Hold Slew Rate
=
Falling Signal
VIH(DC)min - VREF(DC)
Figure 18 — Illustration of nominal slew rate for hold time tDH
for DQ with respect to strobe
Preliminary Data Sheet E1890E20 (Ver. 2.0)
51
TF
EDB4432BABH
/DQS
DQS
tDS
tDH
tDS
VDDQ
nominal
line
VIH(AC) min
tDH
tVAC
VREF to AC
region
VIH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VREF to AC
region
VIL(AC) max
nominal
line
tVAC
TR
VSSQ
Setup Slew Rate tangent line [ VIH(AC)min - VREF(DC) ]
=
Rising Signal
TR
TF
Setup Slew Rate tangent line [ VREF(DC) - VIL(AC)max ]
Falling Signal =
TF
Figure 19 — Illustration of tangent line for setup time tDS
for DQ with respect to strobe
Preliminary Data Sheet E1890E20 (Ver. 2.0)
52
EDB4432BABH
/DQS
DQS
tDS
tDS
tDH
tDH
VDDQ
VIH(AC) min
nominal
line
VIH(DC) min
DC to VREF
region
tangent
line
VREF(DC)
DC to VREF
region
tangent
line
nominal
line
VIL(DC) max
VIL(AC) max
VSSQ
TR
Hold Slew Rate
Rising Signal =
Hold Slew Rate
=
Falling Signal
tangent line [ VREF(DC) - VIL(DC)max ]
TR
tangent line [ VIH(DC)min - VREF(DC) ]
TF
Figure 20 — Illustration of tangent line for hold time tDH
for DQ with respect to strobe
Preliminary Data Sheet E1890E20 (Ver. 2.0)
53
TF
EDB4432BABH
3. Pin Function
Table 36 Pad Definition and Description
Name
Type
Description
Input
Clock:
CK and /CK are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both
positive and negative edge of CK. Single Data Rate (SDR) inputs, /CS and CKE, are sampled at the
positive Clock edge.
Clock is defined as the differential pair, CK and /CK. The positive Clock edge is defined by the crosspoint
of a rising CK and a falling /CK. The negative Clock edge is defined by the crosspoint of a falling CK and
a rising /CK.
CKE
Input
Clock Enable:
CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers
and output drivers. Power savings modes are entered and exited through CKE transitions.
CKE is considered part of the command code. See Command Truth Table on page 57 for command code
descriptions. CKE is sampled at the positive Clock edge.
/CS
Input
Chip Select:
/CS is considered part of the command code. See Command Truth Table on page 57 for command code
descriptions. /CS is sampled at the positive Clock edge.
CA0 – CA9
Input
DDR Command/Address Inputs:
Uni-directional command/address bus inputs.
CA is considered part of the command code. See Command Truth Table on page 57 for command code
descriptions.
DQ0 – DQ31
I/O
Data Inputs/Output: Bi-directional data bus
x32 : DQ0 – DQ31 , x16 : DQ0 – DQ15
CK, /CK
Data Strobe (Bi-directional, Differential):
The data strobe is bi-directional (used for read and write data) and differential (DQS and /DQS). It is output
with read data and input with write data. DQS is edge-aligned to read data and centered with write data.
DQS0 – DQS3,
/DQS0 – /DQS3 I/O
The following is corresponding table between DQ and DQS, /DQS
DQ
32
DQS, /DQS
DQ
16
DQS, /DQS
DQ0-7
DQS0, /DQS0
DQ0-7
DQS0, /DQS0
DQ8-15
DQS1, /DQS1
DQ8-15
DQS1, /DQS1
DQ16-23
DQS2, /DQS2


DQ24-31
DQS3, /DQS3


Input Data Mask:
DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincident
with that input data during a Write access. DM is sampled on both edges of DQS. Although DM is for input
only, the DM loading shall match the DQ and DQS (or /DQS).
DM0 – DM3
Input
The following is corresponding table between DQ and DM
16
32
DQ
DM
DM0
DQ0-7
DM0
DQ
DM
DQ0-7
DQ8-15
DM1
DQ8-15
DM1
DQ16-23
DM2


DQ24-31
DM3


VDD1
Supply Core Power Supply 1
VDD2
Supply Core Power Supply 2
VDDCA
Supply Input Receiver Power Supply
VDDQ
Supply I/O Power Supply
VREFCA
Supply Reference Voltage for CA Input Receiver
VREFDQ
Supply Reference Voltage for DQ Input Receiver
VSS
Supply Ground
VSSQ
Supply I/O Ground
ZQ
I/O
Reference Pin for Output Drive Strength Calibration
Preliminary Data Sheet E1890E20 (Ver. 2.0)
54
EDB4432BABH
CK
/CK
CKE
Clock
generator
4. Block Diagram
CA0 to CA9
Row
address
buffer
and
refresh
counter
Row decoder
Mode
register
Memory cell array
Bank 0
Sense amp.
Control logic
/CS
Address/command decoder
Bank 7
Bank 6
Bank 5
Bank 4
Bank 3
Bank 2
Bank 1
Column decoder
Column
address
buffer
and
burst
counter
Data control circuit
Latch circuit
Input & Output buffer
DQ
Preliminary Data Sheet E1890E20 (Ver. 2.0)
55
DQS, /DQS
DM
EDB4432BABH
5. Simplified State Diagram
Power
Applied
Automatic Sequence
Power
On
Resetting
MR
Reading
Command Sequence
Reset
MRR
Self
Refreshing
Resetting
PD
SREF
PDX
Resetting
Power
Down
SREFX
Reset
MRR
Idle
MR
Reading
REF
Idle
MRW
PDX
MR
Writing
ACT
Active
Power
Down
PD
Idle
Power
Down
MRR
PDX
Refreshing
Active
MR
Reading
PD
Active*1
BST
WR
BST
RD
WR
Writing
Reading
WRA
PR(A) = Precharge (All)
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
BST = Burst Terminate
Reset = Reset is achieved through MRW command
MRW = Mode Register Write
MRR = Mode Register Read
PD = Enter Power Down
PDX = Exit Power Down
SREF = Enter Self Refresh
SREFX = Exit Self Refresh
REF = Refresh
PR, PRA
RDA
WRA
Writing
with
Autoprecharge
RD
RDA
PR, PRA
Reading
with
Autoprecharge
Precharging
Figure 21 — Simplified Bus Interface State Diagram
Notes: 1. For DDR2 Mobile RAM in the Idle state, all banks are precharged.
2. RESET command can be issued from any state if CKE is kept high and NOP commands are
issued for at least tINIT3 = 200 μs before the RESET command.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
56
EDB4432BABH
6. Truth tables
Operation or timing that is not specified is illegal, and after such an event, in order to guarantee proper
operation, the DDR2 Mobile RAM Device must be powered down and then restarted through the
specified initialization sequence before normal operation can continue.
Table 37 provides the command truth table.
Table 37 Command Truth Table
SDR Command Pins
Command
CKE
/CS
MRW
MRR
DDR CA pins (10)
CK(n-1)
CK(n)
H
H
H
Refresh
(per bank)
H
Refresh
(all bank)
H
Enter
Self-Refresh
H
Activate
(bank)
H
Write
(bank)
H
Read
(bank)
H
Precharge
(bank)
H
BST
H
H
H
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
L
L
L
L
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
L
L
L
H
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
L
L
L
L
X
H
L
X
L
X
L
H
L
H
H
X
L
X
L
L
L
H
X
L
X
H
H
H
H
H
L
H
R8
R9
R10
R11
R12
BA0
BA1
BA2
R0
R1
R2
R3
R4
R5
R6
R7
R13
RFU
H
L
L
RFU
RFU
C1
C2
BA0
BA1
BA2
AP*3
C3
C4
C5
C6
C7
C8
C9
RFU
RFU
H
L
H
RFU
RFU
C1
C2
BA0
BA1
BA2
AP*3
C3
C4
C5
C6
C7
C8
C9
RFU
RFU
H
H
L
H
AB
X
X
BA0
BA1
BA2
X
X
X
X
X
X
X
X
X
X
H
H
L
L
L
L
L
L
X
L
X
H
NOP
H
H
H
H
X
L
X
Maintain
PD, SREF
(NOP)
H
L
L
H
H
X
L
X
Preliminary Data Sheet E1890E20 (Ver. 2.0)
57
CK
EDGE
EDB4432BABH
Table 37 Command Truth Table
SDR Command Pins
Command
DDR CA pins (10)
CKE
/CS
CK(n-1)
CK(n)
H
H
CA0
CA1
CA2
CA3
CA4
CA5
CA6
CA7
CA8
CA9
CK
EDGE
X
NOP
H
X
X
Maintain
PD, SREF
(NOP)
L
Enter
Power Down
H
Exit
PD, SREF
L
Notes: 1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
L
H
X
X
L
H
X
X
H
H
X
All commands are defined by states of /CS, CA0, CA1, CA2, CA3, and CKE at the rising edge
of the clock.
Bank addresses determine which bank is to be operated upon.
AP “high” during a READ or WRITE command indicates that an auto-precharge will occur to
the bank associated with the READ or WRITE command.
“X” means “H or L (but a defined logic level)”
Self-refresh exit is asynchronous.
VREF must be between 0 and VDDQ during Self-Refresh operation.
CAxr refers to command/address bit “x” on the rising edge of clock.
CAxf refers to command/address bit “x” on the falling edge of clock.
/CS and CKE are sampled at the rising edge of clock.
The least-significant column address C0 is not transmitted on the CA bus, and is implied to be
zero.
RFU needs to input “H” or “L“ (but a defined logic level).
Preliminary Data Sheet E1890E20 (Ver. 2.0)
58
EDB4432BABH
7. Power-up, initialization and Power-Off
DDR2 Mobile RAM Devices must be powered up and initialized in a predefined manner. Operational
procedures other than those specified may result in undefined operation.
7.1
Power Ramp and Device Initialization
The following sequence shall be used to power-up an DDR2 Mobile RAM Device. Unless specified
otherwise, these steps are mandatory.
1. Power Ramp
While applying power (after Ta), CKE shall be held at a logic low level ( 0.2 × VDD2 (VDDCA)), all
other inputs shall be between VILmin and VIHmax. The DDR2 Mobile RAM Device will only guarantee
that outputs are in a high impedance state while CKE is held low.
On or before the completion of the power ramp (Tb) CKE must be held low.
DQ, DM, DQS and /DQS voltage levels must be between VSSQ and VDDQ during voltage ramp time
to avoid latch-up. CK, /CK, /CS and CA inputs levels must be between VSS and VDD2 (VDDCA)
during voltage ramp up to avoid latch-up.
The following conditions apply:
Ta is the point where any power supply first reaches 300mV.
After Ta is reached, VDD1 must be greater than VDD2 (VDDCA) - 200mV.
After Ta is reached, VDD1 and VDD2 must be greater than VDDQ - 200mV.
After Ta is reached, VREF must always be less than all other supply voltages.
The voltage difference between any of VSS and VSSQ pins may not exceed 100mV.
The above conditions apply between Ta and power-off (controlled or uncontrolled).
Tb is the point when all supply and reference voltages are within their respective min/max operating
conditions.
For supply and reference voltage operating conditions, See Table 2 on page 9.
Power ramp duration tINIT0 (Tb - Ta) must be no greater than 20ms.
Note: VDD2 is not present in some systems. Rules related to VDD2 in those cases do not apply.
2. CKE and clock
Beginning at Tb, CKE must remain low for at least tINIT1 = 100 ns, after which it may be asserted
high. Clock must be stable at least tINIT2 = 5 x tCK prior to the first low to high transition of CKE (Tc).
CKE, /CS and CA inputs must observe setup and hold time (tIS, tIH) requirements with respect to the
first rising clock edge (as well as to the subsequent falling and rising edges).
The clock period shall be within the range defined for tCKb (18 ns to 100 ns), if any Mode Register
Reads are performed. Mode Register Writes can be sent at normal clock operating frequencies so
long as all AC Timings are met.. Furthermore, some AC parameters (e.g. tDQSCK) may have relaxed
timings (e.g. tDQSCKb) before the system is appropriately configured.
While keeping CKE high, issue NOP commands for at least tINIT3 = 200 s. (Td).
3. Reset command
After tINIT3 is satisfied, a MRW(Reset) command shall be issued (Td). The memory controller may
optionally issue a Precharge-All command prior to the MRW Reset command. Wait for at least
tINIT4 = 1 s while keeping CKE asserted and issuing NOP commands.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
59
EDB4432BABH
4. Mode Registers Reads and Device Auto-Initialization (DAI) polling:
After tINIT4 is satisfied (Te) only MRR commands and power-down entry/exit commands are allowed.
Therefore, after Te, CKE may go low in accordance to Power-Down entry and exit specification.
The MRR command may be used to poll the DAI-bit to acknowledge when Device Auto-Initialization is
complete or the memory controller shall wait a minimum of tINIT5 before proceeding.
As the memory output buffers are not properly configured yet, some AC parameters may have relaxed
timings before the system is appropriately configured.
After the DAI-bit (MR#0, “DAI”) is set to zero “DAI complete“ by the memory device, the device is in
idle state (Tf). The state of the DAI status bit can be determined by an MRR command to MR#0.
The DDR2 Mobile RAM will set the DAI-bit no later than tINIT5 (10 s) after the Reset command.
The memory controller shall wait a minimum of tINIT5 or until the DAI-bit is set before proceeding.
After the DAI-Bit is set, it is recommended to determine the device type and other device characteristics by issuing MRR commands (MR0 “Device Information” etc.).
5. ZQ Calibration:
After tINIT5 (Tf), an MRW ZQ Initialization Calibration command may be issued to the memory (see
MR#10). This command is used to calibrate output drivers (RON) over process, voltage, and
temperature. In system in which more than one DDR2 Mobile RAM Device exists on the same bus,
the controller must not overlap ZQ Calibration commands. The device is ready for normal operation
after tZQINIT.
6. Normal Operation:
After tZQINIT (Tg), MRW commands may be used to properly configure the memory, for example the
output buffer driver strength, latencies etc. Specifically, MR1, MR2, and MR3 shall be set to configure
the memory for the target frequency and memory configuration.
The DDR2 Mobile RAM Device will now be in IDLE state and ready for any valid command.
After Tg, the clock frequency may be changed according to the clock frequency change procedure
described in section “Input clock stop and frequency change during CKE low events” of “DDR2 Mobile
RAM General Functionality and Electrical Condition” datasheet (E1354E).
Table 38 Timing Parameters for initialization
Symbol
min.
max.
Unit
Comment
tINIT0
—
20
ms
Maximum Power Ramp Time
tINIT1
100
—
ns
Minimum CKE low time after completion of power ramp
tINIT2
5
—
tCK
Minimum stable clock before first CKE high
tINIT3
200
—
s
Minimum Idle time after first CKE assertion
tINIT4
1
—
s
Minimum Idle time after Reset command
tINIT5
—
10
s
Maximum duration of Device Auto-Initialization
tZQINIT
1
—
s
ZQ Initial Calibration
tCKb
18
100
ns
Clock cycle time during boot
Preliminary Data Sheet E1890E20 (Ver. 2.0)
60
EDB4432BABH
Ta
Tb
Tc
Td
Tf
Te
Tg
tINIT2 = 5 tCK (min)
CK, /CK
tINIT0 = 20 ms (max)
Supplies
tINIT3 = 200 s (min)
tINIT1 = 100 ns (min)
CKE
PD
tISCKE
tINIT5
tINIT4 = 1 s (min)
CA*
RESET
MRR
tZQINIT
ZQC
Valid
DQ
TD_ResetPowerRamp_4 (modified)
* Midlevel on CA bus means: valid NOP
Figure 22 — Power Ramp and Initialization Sequence
7.1.1
Initialization after Reset (without Power Ramp):
If the RESET command is issued outside the power-up initialization sequence, the reinitialization
procedure shall begin with step 3 (Td).
7.1.2
Power-Off Sequence
The following sequence shall be used to power-off the DDR2 Mobile RAM Device. Unless specified
otherwise, these steps are mandatory.
While removing power, CKE shall be held at a logic low level ( 0.2 × VDD2 (VDDCA)), all other inputs
shall be between VILmin and VIHmax. The DDR2 Mobile RAM Device will only guarantee that outputs
are in a high impedance state while CKE is held low.
DQ, DM, DQS and /DQS voltage levels must be between VSSQ and VDDQ during power-off sequence
to avoid latch-up.
CK, /CK, /CS and CA input levels must be between VSS and VDD2 (VDDCA) during power-off sequence
to avoid latch-up.
Tx is the point where any power supply decreases under its minimum value specified in the DC operating
condition table.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
61
EDB4432BABH
Tz is the point where all power supplies are below 300mV. After Tz, the device is powered off.
The time between Tx and Tz (tPOFF) shall be less than 2s.
The following conditions apply:
Between Tx and Tz, VDD1 must be greater than VDD2 (VDDCA) - 200mV.
Between Tx and Tz, VDD1 and VDD2 must be greater than VDDQ - 200mV.
Between Tx and Tz, VREF must always be less than all other supply voltages.
The voltage difference between any of VSS and VSSQ pins may not exceed 100mV.
For supply and reference voltage operating conditions, See Table 2 on page 9.
Table 39 Timing Parameters for Power-Off
Symbol
tPOFF
7.1.3
min.
max.
—
2
Unit
s
Comment
Maximum Power-Off ramp time
Uncontrolled Power-Off Sequence
The following sequence shall be used to power-off the DDR2 Mobile RAM Device under uncontrolled
condition. Unless specified otherwise, these steps are mandatory.
Tx is the point where any power supply decreases under its minimum value specified in the DC operating
condition table. After turning off all power supplies, any power supply current capacity must be zero.
Tz is the point where all power supply first reaches 300mV. After Tz, the device is powered off.
The time between Tx and Tz (tPOFF) shall be less than 2s. The relative level between supply voltages
are uncontrolled during this period.
VDD1 and VDD2 shall decrease with a slope lower than 0.5V/usec between Tx and Tz.
Uncontrolled power-off sequence can be applied only up to 400 times in the life of the device.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
62
EDB4432BABH
8. Mode Register Definition
Table 40 shows the mode registers for DDR2 Mobile RAM.
Each register is denoted as “R” if it can be read but not written and “W” if it can be written but not read.
Mode Register Read command shall be used to read a register. Mode Register Write command shall be
used to write a register.
Table 40 Mode Register Assignment
MR#
MA
<7:0>
Function
Access
OP7
OP6
OP5
OP4
OP3
OP2
0
00H
Device Info.
R
(RFU)
1
01H
Device Feature 1
W
nWR (for AP)
2
02H
Device Feature 2
W
(RFU)
RL & WL
MR#2
3
03H
I/O Config-1
W
(RFU)
DS
MR#3
4
04H
Refresh Rate
R
5
05H
Basic Config-1
R
Manufacturer ID
MR#5
6
06H
Basic Config-2
R
Revision ID1 (Die Revision)
MR#6
7
07H
Basic Config-3
R
Revision ID2 (RFU)
MR#7
8
08H
Basic Config-4
R
9
09H
Test Mode
W
Vendor-Specific Test Mode
10
0AH
IO Calibration
W
Calibration Code
11:15
0BH~0FH
(Reserved)
RZQI
WC
(RFU)
BT
I/O width
OP0
DI
DAI
BL
(RFU)
TUF
OP1
MR#0
MR#1
Refresh Rate
Density
Link
Type
MR#4
MR#8
MR#10
(RFU)
16
10H
PASR_Bank
W
Bank Mask
MR#16
17
11H
PASR_Seg
W
Segment Mask
MR#17
18:19
12H~13H
(Reserved)
32
20H
DQ Calibration
Pattern A
33:39
21H~27H
(Do Not Use)
40
28H
DQ Calibration
Pattern B
41:47
29H~2FH
(Do Not Use)
48:62
30H~3EH
(Reserved)
63
3FH
Reset
64:126
40H~7EH
(Reserved)
127
7FH
(Do Not Use)
(RFU)
R
See “DQ Calibration” of “DDR2 Mobile RAM General Functionality
and Electrical Condition” datasheet (E1354E).
MR#32
R
See “DQ Calibration” of “DDR2 Mobile RAM General Functionality
and Electrical Condition” datasheet (E1354E).
MR#40
(RFU)
W
X
(RFU)
128:190 80H~BEH (Reserved)
191
BFH
(RFU)
(Do Not Use)
192:254 C0H~FEH (Reserved)
255
FFH
MR#63
(RFU)
(Do Not Use)
Notes 1: RFU bits shall be set to ‘0’ during Mode Register writes.
2: RFU bits shall be read as ‘0’ during Mode Register reads.
3: All Mode Registers that are specified as RFU or write-only shall return undefined data when
read and DQS, /DQS shall be toggled.
4: All Mode Registers that are specified as RFU shall not be written.
5: Writes to read-only registers shall have no impact on the functionality of the device.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
63
EDB4432BABH
MR#0_Device Information (MA<7:0> = 00H): Read-only
OP7
OP6
OP5
OP4
(RFU)
OP3
RZQI
OP2
OP1
OP0
(RFU)
DI
DAI
OP<0>
DAI (Device Auto-Initialization Status)
0B: DAI complete
1B: DAI still in progress
OP<1>
DI (Device Information)
0B: DDR2 Mobile RAM
OP<4:3>
RZQI (Built in Self Test for RZQ Information)
01B: ZQ-pin may connect to VDD2 or VDDCA or float
10B: ZQ-pin may short to GND
11B: ZQ-pin self test completed, no error condition detected
(ZQ-pin may not connect to VDD or float nor short to GND)
Notes: 1. DDR2 Mobile RAM will not implement DNV functionality.
2. RZQI will be set upon completion of the MRW ZQ Initialization Calibration command.
3. If ZQ is connected to VDD2 or VDDCA to set default calibration, OP[4:3] shall be set to 01.
If ZQ is not connected to VDD2 or VDDCA, either OP[4:3]=01 or OP[4:3]=10 might indicate
a ZQ-pin assembly error. It is recommended that the assembly error is corrected.
4. In the case of possible assembly error (either OP[4:3]=01 or OP[4:3]=10 per Note 3), the
LPDDR2 device will default to factory trim settings for RON, and will ignore ZQ calibration
commands. In either case, the system may not function as intended.
5. In the case of the ZQ self-test returning a value of 11b, this result indicates that the device
has detected a resistor connection to the ZQ pin. However, this result cannot be used to
validate the ZQ resistor value or that the ZQ resistor tolerance meets the specified limits
(i.e. 240 1%).
Preliminary Data Sheet E1890E20 (Ver. 2.0)
64
EDB4432BABH
MR#1_Device Feature 1 (MA<7:0> = 01H): Write-only
OP7
OP6
nWR (for AP)
OP5
OP4
OP3
WC
BT
OP<2:0>
BL
010B: BL4 (default)
011B: BL8
100B: BL16
All others: Reserved
OP<3>
BT
0B: Sequential (default)
1B: Interleaved
OP<4>
WC
0B: Wrap (default)
1B: No wrap (allowed for BL4 only)
OP<7:5>
nWR
001B: nWR=3 (default)
010B: nWR=4
011B: nWR=5
100B: nWR=6
101B: nWR=7
110B: nWR=8
All others: Reserved
OP2
OP1
OP0
BL
Notes: 1. BL 16, interleaved is not an official combination to be supported.
2. Programmed value in nWR register is the number of clock cycles which determines when to
start internal precharge operation for a write burst with AP enabled. It is determined by
RU(tWR/tCK).
Preliminary Data Sheet E1890E20 (Ver. 2.0)
65
EDB4432BABH
Table 41 Burst Sequence by BL, BT, and WC
C3
C2
C1
C0
WC
wrap
BT
any
BL
4
Burst Cycle Number and Burst Address Sequence
1
2
3
4
0
1
2
3
2
3
0
1
y
y+1
y+2
y+3
5
6
7
8
X
X
0B
0B
X
X
1B
0B
X
X
X
0B
nw
any
X
0B
0B
0B
wrap
seq
0
1
2
3
4
5
6
7
X
0B
1B
0B
2
3
4
5
6
7
0
1
X
1B
0B
0B
4
5
6
7
0
1
2
3
X
1B
1B
0B
6
7
0
1
2
3
4
5
X
0B
0B
0B
0
1
2
3
4
5
6
7
X
0B
1B
0B
2
3
0
1
6
7
4
5
X
1B
0B
0B
4
5
6
7
0
1
2
3
X
1B
1B
0B
6
7
4
5
2
3
0
1
X
X
X
0B
nw
any
0B
0B
0B
0B
wrap
seq
0B
0B
1B
0B
1B
0B
0B
1B
1B
1B
8
int
9
10
11
12
13
14
15
16
A
B
C
D
E
F
illegal (not allowed)
0
1
2
3
4
5
6
7
8
9
0B
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
0B
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
1B
0B
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
0B
0B
0B
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
0B
1B
0B
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
1B
1B
0B
0B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
1B
1B
1B
0B
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
X
X
X
0B
X
X
X
0B
Notes: 1.
nw
16
int
illegal (not allowed)
any
illegal (not allowed)
C0 input is not present on CA bus. It is implied zero.
2.
For BL=4, the burst address represents C1 - C0.
3.
For BL=8, the burst address represents C2 - C0.
4.
For BL=16, the burst address represents C3 - C0.
5.
For no-wrap (nw), BL4, the burst shall not cross the page boundary and shall not cross subpage boundary. The variable y may start at any address with C0 equal to 0 and may not start
at any address in Table 42 below for the respective density and bus width combinations.
Table 42 Non Wrap Restrictions
Not across full page boundary
Not across sub page boundary
Note: 1.
x16
7FE, 7FF, 000, 001
x32
3FE, 3FF, 000, 001
x16
3FE, 3FF, 400, 401
x32
None
Non-wrap BL=4 data-orders shown above are prohibited.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
66
EDB4432BABH
MR#2_Device Feature 2 (MA<7:0> = 02H): Write-only
OP7
OP6
OP5
OP4
OP3
(RFU)
OP<3:0>
OP2
OP1
OP0
RL & WL
RL & WL
0001B: RL3 / WL1(default)
0010B: RL4 / WL2
0011B: RL5 / WL2
0100B: RL6 / WL3
0101B: RL7 / WL4
0110B: RL8 / WL4
All others: Reserved
MR#3_I/O Configuration 1 (MA<7:0> = 03H): Write-only
OP7
OP6
OP5
OP4
OP3
(RFU)
OP<3:0>
OP2
OP1
DS
DS
0000B: Reserved
0001B: 34.3 typ.
0010B: 40  typ. (default)
0011B: 48  typ.
0100B: 60  typ.
0101B: Reserved
0110B: 80  typ.
0111B: 120  typ.
All others: Reserved
Preliminary Data Sheet E1890E20 (Ver. 2.0)
67
OP0
EDB4432BABH
MR#4_Device Temperature (MA<7:0> = 04H): Read-only
OP7
OP6
TUF
OP5
OP4
OP3
OP2
(RFU)
OP1
OP0
Refresh Rate
OP<2:0>
Refresh Rate
000B: Low temperature operating limit exceeded
001B: 4× tREFI, 4× tREFIpb, 4× tREFW
010B: 2× tREFI, 2× tREFIpb, 2× tREFW
011B: 1× tREFI, 1× tREFIpb, 1× tREFW(+85C)
100B: RFU
101B: 0.25× tREFI, 0.25× tREFIpb, 0.25× tREFW, do not de-rate AC timing
110B: 0.25× tREFI, 0.25× tREFIpb, 0.25× tREFW, de-rate AC timing
111B: High temperature operating limit exceeded
OP<7>
TUF(Temperature Update Flag)
0B: OP<2:0> value has not changed since last read of MR4.
1B: OP<2:0> value has changed since last read of MR4.
Notes: 1.
2.
3.
4.
5.
6.
A Mode Register Read from MR4 will reset OP7 to ‘0’.
OP7 is reset to ‘0’ at power-up. OP<2:0> bits are undefined after power-up.
If OP2 equals ‘1’, the device temperature is greater than 85C.
OP7 is set to “1” if OP2:OP0 has changed at any time since the last read of MR4.
DDR2 Mobile RAM will drive OP<6:5> to ‘0’.
Specified operating temperature range and maximum operating temperature are refer to
“Electrical Conditions” on page 9. If maximum temperature is 85C, functionality for over 85C
is not guaranteed.
MR#5_Basic Configuration 1 (MA<7:0> = 05H): Read-only
OP7
OP6
OP5
OP4
OP3
Manufacturer ID
OP<7:0>
Manufacturer ID
00000011B (Elpida)
Preliminary Data Sheet E1890E20 (Ver. 2.0)
68
OP2
OP1
OP0
EDB4432BABH
MR#6_Basic Configuration 2 (MA<7:0> = 06H): Read-only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
OP2
OP1
OP0
OP2
OP1
OP0
Revision ID1(Die Revision)
OP<7:0>
Revision ID1 (Die Revision)
00000000B: A-version
MR#7_Basic Configuration 3 (MA<7:0> = 07H): Read-only
OP7
OP6
OP5
OP4
OP3
Revision ID2 (RFU)
OP<7:0>
Revision ID2 (RFU)
00000000B: Default Value
MR#8_Basic Configuration 4 (MA<7:0> = 08BH): Read-only
OP7
OP6
I/O width
OP<1:0>
Type
00B: S4 Device
OP<5:2>
Density
0110B: 4Gb
OP<7:6>
I/O width
00B: ×32
OP5
OP4
OP3
Density
Preliminary Data Sheet E1890E20 (Ver. 2.0)
69
Type
EDB4432BABH
MR#10_Calibration (MA<7:0> = 0AH): Write-only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Calibration Code
OP<7:0>
Calibration Code
0xFF: Calibration command after initialization
0xAB: Long calibration
0x56: Short calibration
0xC3: ZQ Reset
others: Reserved
Notes: 1. Host processor shall not write MR10 with “Reserved” values.
2. DDR2 Mobile RAM Devices shall ignore calibration command when a “Reserved” value is
written into MR10.
3. See AC timing table for the calibration latency.
4. If ZQ is connected to VSS through RZQ, either the ZQ calibration function (see “Mode Register Write ZQ Calibration Command” of “DDR2 Mobile RAM General Functionality and Electrical Condition” datasheet (E1354E).) or default calibration (through the ZQreset command) is
supported. If ZQ is connected to VDD2 or VDDCA, the device operates with default calibration, and ZQ calibration commands are ignored. In both cases, the ZQ connection shall not
change after power is applied to the device.
MR#16_PASR_Bank Mask (MA<7:0> = 010H): Write-only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Bank Mask
OP<7:0>
Bank Mask
0B: refresh enable to the bank (=unmasked, default)
1B: refresh blocked (=masked)
Bank and OP corresponding table
OP<7:0>
Note: 1.
Bank
Bank #
Bank Address
OP0
Bank 0
000B
OP1
Bank 1
001B
OP2
Bank 2
010B
OP3
Bank 3
011B
OP4
Bank 4
100B
OP5
Bank 5
101B
OP6
Bank 6
110B
OP7
Bank 7
111B
Each bank can be masked independently by setting each OP value.
Preliminary Data Sheet E1890E20 (Ver. 2.0)
70
EDB4432BABH
MR#17_PASR_Segment Mask (MA<7:0> = 0H): Write-only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
Segment Mask
OP<7:0>
Segment
0B: refresh enable to the segment (=unmasked, default)
1B: refresh blocked (=masked)
Segment and OP corresponding table
OP<7:0>
Note: 1.
Segment
Segment #
Row Address (R13:11)
OP0
Segment 0
000B
OP1
Segment 1
001B
OP2
Segment 2
010B
OP3
Segment 3
011B
OP4
Segment 4
100B
OP5
Segment 5
101B
OP6
Segment 6
110B
OP7
Segment 7
111B
Each segment can be masked independently by setting each OP value.
MR#32_DQ Calibration Pattern A (MA<7:0> = 20H):
Reads to MR32 return DQ Calibration Pattern “A”. See “DDR2 Mobile RAM General Functionality and
Electrical Condition” datasheet (E1354E).
MR#40_DQ Calibration Pattern B (MA<7:0> = 28H):
Reads to MR40 return DQ Calibration Pattern “B”. See “DDR2 Mobile RAM General Functionality and
Electrical Condition” datasheet (E1354E).
MR#63_Reset (MA<7:0> = 3FH): MRW only
OP7
OP6
OP5
OP4
OP3
OP2
OP1
OP0
X
Note: 1.
For additonal information on MRW RESET see “DDR2 Mobile RAM General Functionality and
Electrical Condition” datasheet (E1354E).
Preliminary Data Sheet E1890E20 (Ver. 2.0)
71
EDB4432BABH
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Preliminary Data Sheet E1890E20 (Ver. 2.0)
72
EDB4432BABH
Mobile RAM is a trademark of Elpida Memory, Inc.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Be aware that this product is for use in typical electronic equipment for general-purpose applications.
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, this product is not intended for use in the product in aerospace, aeronautics, nuclear power,
combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other
such application in which especially high quality and reliability is demanded or where its failure or
malfunction may directly threaten human life or cause risk of bodily injury. Customers are instructed to
contact Elpida Memory's sales office before using this product for such applications.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
Usage in environments with special characteristics as listed below was not considered in the design.
Accordingly, our company assumes no responsibility for loss of a customer or a third party when used in
environments with the special characteristics listed below.
Example:
1) Usage in liquids, including water, oils, chemicals and organic solvents.
2) Usage in exposure to direct sunlight or the outdoors, or in dusty places.
3) Usage involving exposure to significant amounts of corrosive gas, including sea air, CL 2 , H 2 S, NH 3 ,
SO 2 , and NO x .
4) Usage in environments with static electricity, or strong electromagnetic waves or radiation.
5) Usage in places where dew forms.
6) Usage in environments with mechanical vibration, impact, or stress.
7) Usage near heating elements, igniters, or flammable items.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E1007
Preliminary Data Sheet E1890E20 (Ver. 2.0)
73