IndianJournalof Engineering
& MaterialsSciences
Vol. 4, August1997,pp. 129-133
A novel dual PFD charge-pump phase locked loop
B C Sarkar, M Nandi, R Hati & A Hati
Physics Department, Burdwan University, Burdwan 713 104, India
Received
14October1996;accepted
27February
1997
A novel charge-pumpphaselocked loop (CP-PLL)comprisingof a modified dual edge sensitive
phasefrequencydetector (PFD)has beenproposed.The new structurehas an increasedloop gainand a
faster transient response,althoughits filter time constant,loop VCO sensitivityand pump current magnitude aresameasthoseof the conventionalCP-PLL.
I,
Charge pump phase-lock loops (CP-PLLs) based
on tristate sequential logic phase/frequency detectors (PFDs) are extensively used in present day
communication receivers because of its number of
merits over conventional phase-locked 100psl-4.
These include large tracking range, almost zero
steady state phase error, easy implementation facility and low cost. Moreover, the loop structure
parameters, viz., loop damping factor (p), loop
natural frequency (wJ, and loop gain or bandwidth (K) can be easily controlled to satisfy several application-specific requirements. The present
paper describes a simple modification in the structure of the loop PFD which can be used to change
the loop parameters (K, p and wJ without changing the pump current magnitude (Ip), VCO sensitivity (Ko (rad/s)/V) and loop filter tiIne constant
(1").Considering a large input signal frequency (wJ
to loop bandwidth (K) ratio, the transfer fuDction
analysisl of the modified CP-PLL shows that the
value of p and Wn are increased by a factor of J2
while the value of K is doubled compared to those
of a conventional CP-PLL. The effective increase
of K can improve the acquisition behaviour of the
modified loop. The changed response of the new
CP-PLL would fmd application in high speed frequency synthesizers with better spectral purity.
VCO signal. The phase error is obtained as a time
interval once in each period of the phase leading
waveform and the pump current flows during that
interval of time once in that cycle. Assuming 50%
duty cycle of the square wave input one can employ a second PFD to detect the phase error for
the second time in the same cycle at the negative
going edges of the signal under consideration.
Thus the average pump current over a cycle can
be made two times of the average pump current of
a single PFD CP-PLL. This increases the loop
bandwidth and therefore reduces the acquisition
time.
The schematic diagram of the modified CP-PLL
is shown in Fig. 1. The PFD-1 is activated by the
positive going edge transitions of the two input
signals I and V while PFD-2 responds to those of
the negative going edge transitions. Remembering
the basic operation principle of the sequential~.
tristate PFD, one can note that the UP output
terminals (Ui or U2) of the two PFDs will be active (logic state 1) when I waveform leads the V
waveform and will remain active for a duration
proportional to the phase difference between I
and V. The DOWN terminals (Di or D2) will reINPUT
~
/
"i
Structure Modification Algorithm
Conventional CP-PLLs use one PFD which detects the lead or lag in phase of the local reference
VCO signal (of frequency wo) with respect to the
incoming input signal of frequency Wi' For this
purpose sequential logic circuit based PFDs are
employed which are activated by the transition
edges (say positive going edge) of the input or
Fig. I-Functional blockdiagramof the proposeddual-PFD
CP-PLL
130
INDIAN J. ENG. MATER. SCI., AUGUST 1997
main passive (logic state 0) during this period. The
roles of UP and DOWN terminals are reversed
when V leads I. If V an~ I are in s~me ph~se, both
UP and DOWN termInals remam passive. The
control signals required to act~vate the pump cir-
8j (t) = 8i (0) + Wi t
K i r
8 (t)= 80(0)+ wo(t)+ Ko[i R+ Vx(O)]t+ 6.0.p.
0
p
2C
cuit are derived using a simple logic circuit whic4
has two outputs U and D. U and D are. obtained
according to the following rule:
for 0 < t< tp
= 8
U=(UIANDU2),andD=(l5IANDl52)
The pump current flows into (from) the loop filter
when U=O, D= 1 (U= 1, D=O) respectively. No
current will flow when U= D= 1.
...(3)
0
o()
+
w
o()
t +
,
...(4a)
K
[
0
ir
ilt
i Rl
_.:£:P.+.:P.:£:+
p
p
2C
C
for tp< t< T
i t
Vx(T)= Vx(tp)= Vx(O)+~
Vx(O) ]
...(4b)
~
...(5)
Analytical Studies
.
It is evident from the modified PFD structure Here ip (= ::t:Ip) is the filter pump current whose
that if there is a phase error of amount 8e between sign depends on the sign of phase error, tp is the
the input signal and the reference signal on.e gets pump "ON" interval, T is the time interval betwo pump ON intervals of approximate duration tween two consecutive active transitions of the
18el/Wi in a period of (2JrIWj)' Thus, if Ip be the PFD and Vx(T) is the voltage stored in the filter
pump current magnitude, the average pump cur- capacitor C at t= 1: The value of tp can be obrent I PAover a full cycle can be obtained as,
tained by solving the equations
IpA=Ip(18eI/Jr)
...(1)
80(tp+)=0 for positive error
and
/~
which is twice the average current of the conventional CP-PLL. The average VCO control voltage
is obtained by pas~ing the average .pump cu~ent
throu~ the filter Impe~ance func~lon compnsed
of resistor R ~d capacitor c: of time cons~ant 'f
(= Rq. Followmg the analysIs of Ga:dner one
gets different system parameters as given below.
With suffix m, for modified loop they are related
.
8j(tp_)=Ofornegatlveerror.
The quantity 8j (T) or 80 (T) which becomes Jr
earlier gives the solution of T indicating the start
of a new cycle. Having obtained the exact value of
7; the value of phase error 8e (T) can be calculateQfrom the following relation
'
to conventional loop parameters as,
8e (T) = 8j (T) -80 (T)
K
= (K I R/Jr) = 2K
mop
(Wn)m
=/""K:h= [2 Wn
...(2a)
...(2b)
Pm=(wJm'f/2=.j2P
...(2c)
...(6)
The cal~ulation is repeate.d, ~einitializing all the
state vanables at each startmg mstant of pump cycle, until a previously specified small phase error
is achieved. Taking (WiI K)= 10, p=0.5, (~w/K)
=(wj-wo)IK=::t:2
and ~(}e=::t:6 radians, the
Here Ko ISthe loop VCO sensitiVIty.
time evolution of 8e has been numerically computed and results are shown in Figs 2a and 2b. It is
This modification of the system parameters can be
verified by simulating the real time development
of the loop phase error numerically in accordance
with the proposed hardware. The same has been
done as follows. Assuming input signal phase and
VCO phase -at time t as 8i(t) and 80(t) respectively and choosing the time origin at the active
transition instant of U or D terminals, 8i(t) and
80(t) can be written in the first pump current cycle
(until the next pump current starts) as,
observed that the modified system with new PFD
has quicker time responses. However, the response of the modified CP-PLL in this case is
same as that of the conventional CP-PLL with
damping constant P = 0.707 which indicates that
the modified CP-PLL has a damping constant [2
times of the value taken for computation (0.5).
The stability requirement is critical for a sampledsignal control system like a change pump PLL.
Stability problem of nth order digital PLL has
been addressed by Osbome5. Here the increase in
-1
~
SARKAR et al.: CHARGE-PUMPPHASELOCKED LOOP
131
2
H
~
6
I.
-,
~ o.
~
-:
i~
i...r
'---
:::
~
%-0.
~
~-
x
~
..
_1.
RHS 01(9)
.
Unstable
Region
nO)
I
-,
-H
'GJ
-6
'0)
Fig. 2-The computed time evolution of loop phase error of a
second order CP-PLL, wj/K= 10, Kr= 1; (a) Frequency step
input ~w/K=:t2,
(b) Phase step input ~(Je=:t6 radians;
T I = input signal period ' (~
) conventional ' (
) modi-
0
0'571'
I'ig. 3-Variation
71'
W. T
1,
\'571'
271'
of r.h.s of Eq. (9) and Eli. (10) with normalized input frequency (Wi r)
effective gain requires critical analysis of the stability problem of the new system. Following the
analysis of Gardner, one can examine the locations of the poles of the Z-domain expression of
loop phase error obtained in Appendix as
lJe(Z)
=
1l (i\w/
Wj)Z
(Z-IY+(Z-I)Czrz+Cz(rz-l)
where
C =(21lK/w.)andr
2
1
...()~
7
=1+(1l/w.-r).
2
""_DUG' D-F,..-Flo..
1
"121 -"ono.ho'
The stability condition of the systemis,
Fig. 4-Block
Cz~4/(r2+1)
(K-r)m~[(1l/Wj-r)(1 +(1l/2Wj -r))]-1
)0
..lues
f
e same
diagram of the experimental set-up
...(8)
which can be written in terms of the loop parameters for the modified CP-PLL as,
Th
,h;.
.I
or a conventlona
K-r~[(1l/w.-rXl+(1l/w.-r))]-1
I
I
CP PLL'
-IS
.:. (9)
1
matic diagram of the experimental circuit is shown
in Fig. 4. The transient responses of the modified
as well as conventional CP-PLL have been verified
in the face of frequency shift keyed (FSK) input
signal
circuit
(10)
The equalit1 sign in the above equations indicates
stability limits. The variation of the right hand side
expressions of (9) and (10) with (Wj(t) is shown in
Fig. 3 which gives information regarding the range
of (K -r) for stable system operation. It is evident
that the modified ~tructure remain stable for a
large range of values of K-r. Since Ip, Ko and R varemain unchanged, the modified system will
have the same VCO overload limit as that of the
conventional CP-PLL.
for identical
pump current
and loop filter
constants. The parameters
taken in the de-
sign are Ko=9 kHz/V, Ip=0.309 mA, R=6.8
kg, C= 0.022 .uF, input si~al frequency /; = 37
kHz, frequency step i\f=:I: 1.2 kHz, modulating
frequency fm = 750 Hz. For the design parameters
taken here (K-r)mis 5.658 and the right hand side
expression of (9) is 10.592, which means the stability condition is satisfied. Incidentally the minimum input signal frequency which can be taken
for the experimental circuit is about 20.5 kHz.
Upper limit of input signal frequency is restricted
by the technology used to realise different functional blocks of. the circuit. Figs 5a and 5b show
the performances of the modified and conventionExperimental Details
al CP-PLL based FSK demodulator where the upThe modified CP-PLL is designed in the labora- per trace is the modulating wave and the lower
tory using common IC functional blocks. A sche- trace is the demodulated output. It has been ob.
132
INDIAN 1. ENG. MATER.
sci., AUGUST
1997
0·28
O· 2~
00·2
0·16
~
'0
>
0·12
0
>
0·08
O·O~
O'~
0·6
0'8
1·0
f
1·2
m,
KHz
Fig. 6-Variation of the amplitude of loop control voltage (Vo)
in the face of an FM input signal with the modulating frequency (fm). K; = 9 kHz/V, Ip = 7.35 X 10-5 . A, R= 2.2 kQ,
C=0.022 .uF; (a) modified CP-PLL, (b) conventional CP-PLL.
Fig. 5-Photographs
of experimental responses of a CP-PLL
based FSK demodulator. Upper trace-modulating waveform,
lower trace-demodulated output; (a) modified system, (b) conventional system. X-axis = 50 ms/ em, Y-axis = 0.5 V/ em
served that the modified system has better transient response than that of a conventional one.
The effective increase of loop bandwidth in the
modified CP-PLL with respect to the conventional
CP-PLL has been verified in the laboratory by studying the frequency response of the two loops in
the face of continuous wave frequency modulated
(CWFM) signals. It has been observed that the
demodulated output (Vo) of the modified CP-PLL
becomes maximum at a higher modulating frequency t; compared to that obtained in the case
of conventional CP-PLL. This indicates that the
modified system has a larger value of the loop natural frequency indicating larger loop bandwidth.
The signal and circuit r~,rameters were taken in
the
experiment
as
Ko = 9
kHz/V,
Ip=7.35xlO-sA,
R=2.2 kQ, C=0.022,uF. Using these design parameters (K r)m becomes
0.1408; which means that the system will remain
stable if the input signal frequency be more than
3.568 kHz. In the experiment carrier frequency of
the input CWFM signal was taken 40 kHz. The
experimental variation of Vo with f m for conventional and modified CP-PLL are shown in Fig. 6.
The experimental results give that I; = 0.87 kHz,
([n)m = 1.26 kHz =J2 In' It should be noted that
since the bandwidth of the modified system has
increased, its loop phase error variance? will also
increase.
Discussion
The modified CP-PLL using two PFDs, proposed in this paper, has a larger loop bandwidth
and faster transient response. The FSK response
for modified loop is nearly 35% faster than that of
conventional loop for identical signal and circuit
parameters. Moreover, since the actual pump current magnitude I p and loop filter resistance R have
not been altered in the modified system, the inherent granularity problems of a second order CPPLL, due to voltage step at the vca control
terminal during the pump current off instant, will
not change. This will happen if the average pump
current be increased by increasing the pump current magnitude. The proposed structure can be
used in high speed frequency synthesizers if it be
in a switched mode. The switching should be automatically done from a two-PFD structure (during acquisition mode) to a one-PFD structure
(during tracking mode). This will ensure faster
transition from one frequency to another as well
as purer spectral characteristics of the synthesized
frequency.
SARKAR et al.: CHARGE-PUMP
References
For small phase errors one can approximate
I Gardner F M, IEEE Trans COM, 28 (1980) 1849 .
2 Wolaver D, Phase locked loop circuit design, (Prentice Hall,
Englewood Cliffs, NJ), 1991.
3 Young I A, Greason J K & Wong K L, IEEE
5 Osborne H C, IEEE Trans COM, 28 (19~O) 1343.
6 Sarkar B C & Nandi M, Indian J Pure Appl Phys, 32
(1994)817.
1\n)=n/w;
0, (n)=
OJ
(n) - 00 (n)
+ K"
... (AI)
V, (n-
+- Aw:n
= Oe(n -
1)
Wj
Wi
The discrete difference equations expressing 0e and V, at
the nth pump current ON instant in terms of those at the previous instants and loop parameters can be obtained as follows.
For small Oe, tp and T can be considered same for positive
and negative phase errors. Then Eqs (3), (4) and (5) reduce to
)+[w"
...
(AS)
Using (A4) and (AS) and utilizing only linear terms of
can write 0, (n) at the nth pump ON instant as,
_!!.. K V(n-
1\n)
(AA)
and
Appendix
O;(n)=O;(n-I)+wj
...
J Solid State
Circuits, 27 (1992) 1599 .
4 Jeong D K, et al., IEEE J Solid-State Circuits, 22(2) (1987)
585.
O,,(n)= O,,(n-I
133
PHASE LOCKED LOOP
(I
1)
.\
Oe,
one
,
C1r10. (n -
1)
...
(A6)
...
(A7)
and
V,(n)=
V,(n-l)+
II,O,(n-
1)
wjC
where
I)] 7(n)
2:nK
(:. =-Wi
and r:= I +(:n/Wj r)
... (Al)
Taking the initial frequency error Aw as a frequency step and
utilizing Z transformed equations of (A6) and (A7), onc gcts
aft~r a bit of algchra
and
:n(Aw/
V,(n)=
V,(n-l)+~
C
... (A3)
O,(Z)=
(Z-
I): +(Z-l
w,)Z
)C:r:
+ C!(r:
-
I)
...
(AS)