19-output DB1900Z Low-Power Derivative
w/85ohm Terminations
9ZXL1950
DATASHEET
General Description
Features/Benefits
The 9ZXL1950 is a DB1900Z derivative buffer utilizing
Low-Power HCSL (LP-HCSL) outputs to increase edge rates
on long traces, reduce board space, and reduce power
consumption more than 50% from the original 9ZX21901.It is
pin-compatible to the 9ZXL1930 and fully integrates the
output terminations. It is suitable for PCI-Express Gen1/2/3 or
QPI/UPI applications, and uses a fixed external feedback to
maintain low drift for demanding QPI/UPI applications.
• LP-HCSL outputs; up to 90% IO power reduction, better
•
•
•
•
•
Recommended Application
Buffer for Romley, Grantley and Purley Servers
•
Output Features
•
•
•
19 LP-HCSL output pairs w/integrated terminations (Zo =
85
Key Specifications
•
•
•
•
•
Cycle-to-cycle jitter: <50ps
Output-to-output skew: <50ps
Input-to-output delay variation: <50ps
Phase jitter: PCIe Gen3 <1ps rms
Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
•
•
signal integrity over long traces
Direct connect to 85Ω transmission lines; eliminates 76
termination resistors, saves 130mm2 area
Pin compatible to the 9ZXL1930; easy upgrade to reduced
board space
72-pin VFQFPN package; smallest 19-output Z-buffer
Fixed feedback path; ~0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can share
same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
100MHz & 133.33MHz PLL mode; legacy QPI support
Selectable PLL BW; minimizes jitter peaking in downstream
PLL's
Spread spectrum compatible; tracks spreading input clock
for EMI reduction
SMBus Interface; unused outputs can be disabled
Block Diagram
FBOUT_NC
Z-PLL
(SS Compatible)
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
9ZXL1950 REVISION E 11/20/15
DIF(18:0)
Logic
1
©2015 Integrated Device Technology, Inc.
9ZXL1950 DATASHEET
DIF13
DIF13#
VDDIO
GND
DIF14
DIF14#
DIF15
DIF15#
GND
VDD
DIF16
DIF16#
DIF17
DIF17#
VDDIO
GND
DIF18
DIF18#
Pin Configuration
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
54 DIF12#
53 DIF12
VDDA 1
GNDA 2
52 VDDIO
51 GND
50 DIF11#
^100M_133M# 3
^vHIBW_BYPM_LOBW# 4
CKPWRGD_PD# 5
49 DIF11
48 DIF10#
GND 6
VDDR 7
DIF_IN 8
47 DIF10
46 GND
9ZXL1950
(epad should be connected to GND and is
pin 73)
DIF_IN# 9
^SADR0_tri 10
SMBDAT 11
45 VDD
44 DIF9#
43 DIF9
SMBCLK 12
42 DIF8#
41 DIF8
^SADR1_tri 13
FBOUT_NC# 14
40 VDDIO
39 GND
FBOUT_NC 15
GND 16
38 DIF7#
37 DIF7
DIF0 17
N/A 1530
DIF0# 18
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DIF6#
DIF6
GND
VDDIO
DIF5#
DIF5
DIF4#
DIF4
VDD
GND
DIF3#
DIF3
DIF2#
DIF2
GND
VDDIO
DIF1#
DIF1
Note: Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Pins with ^v prefix have internal 120K pullup/pulldown (biased to VDD/2)
Power Management Table
Inputs
CKPWRGD_PD#
0
DIF_IN/
DIF_IN#
X
1
Running
Control Bits
Outputs
SMBus
EN bit
X
0
DIFx/
FBOUT_NC/
DIFx# FB_OUT_NC#
Low/Low
Low/Low
Low/Low
Running
1
Running
Running
Power Connections
28, 45, 64
21, 33, 40,
52, 57, 69
GND
2
6
16, 22, 27, 34,
39, 46, 51, 58,
63, 70, 73
Description
Analog PLL
Analog Input
1
0
ON
DIF_IN
(MHz)
100.00
133.33
HiBW_BypM_LoBW# Byte0, bit (7:6)
Low ( PLL Low BW)
00
Mid (Bypass)
01
High (PLL High BW)
11
NOTE: PLL is off in Bypass mode
DIF clocks
Functionality at Power-up (PLL mode)
100M_133M#
OFF
ON
PLL Operating Mode
Pin Number
VDDIO
VDD
1
7
PLL State
DIFx
(MHz)
DIF_IN
DIF_IN
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 2
Tri-level Input Thresholds
Level
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
REVISION E 11/20/15
9ZXL1950 DATASHEET
Pin Descriptions
PIN #
1
2
PIN NAME
VDDA
GNDA
PIN TYPE
PWR
GND
3
^100M_133M#
4
^vHIBW_BYPM_LOBW#
5
CKPWRGD_PD#
6
GND
GND
7
VDDR
PWR
8
9
DIF_IN
DIF_IN#
IN
IN
10
^SADR0_tri
IN
11
12
SMBDAT
SMBCLK
I/O
IN
13
^SADR1_tri
IN
14
FBOUT_NC#
OUT
15
FBOUT_NC
OUT
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
DIF0
DIF0#
DIF1
DIF1#
VDDIO
GND
DIF2
DIF2#
DIF3
DIF3#
GND
VDD
DIF4
DIF4#
DIF5
DIF5#
VDDIO
GND
DIF6
DIF6#
GND
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
REVISION E 11/20/15
IN
LATCHE
D IN
IN
DESCRIPTION
Power for the PLL core.
Ground pin for the PLL core.
3.3V Input to select operating frequency. This pin has an internal pull-up resistor.
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as
an analog power rail and filtered appropriately.
HCSL True input
HCSL Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the
SADR1 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up
resistor.
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the
SADR0 to decode 1 of 9 SMBus Addresses. It has an internal 120Kohm pull up
resistor.
Complementary half of differential feedback output. This pin should NOT be
connected to anything outside the chip. It exists to provide delay path matching to
get 0 propagation delay.
True half of differential feedback output. This pin should NOT be connected to
anything outside the chip. It exists to provide delay path matching to get 0
propagation delay.
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
3
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Pin Descriptions (cont.)
PIN #
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
PIN NAME
DIF7
DIF7#
GND
VDDIO
DIF8
DIF8#
DIF9
DIF9#
VDD
GND
DIF10
DIF10#
DIF11
DIF11#
GND
VDDIO
DIF12
DIF12#
DIF13
DIF13#
VDDIO
GND
DIF14
DIF14#
DIF15
DIF15#
GND
VDD
DIF16
DIF16#
DIF17
DIF17#
VDDIO
GND
DIF18
DIF18#
epad
PIN TYPE
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
GND
DESCRIPTION
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Differential true clock output
Differential Complementary clock output
Power supply for differential outputs
Ground pin.
Differential true clock output
Differential Complementary clock output
Connect EPAD to ground.
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 4
REVISION E 11/20/15
9ZXL1950 DATASHEET
Electrical Characteristics–Absolute Maximum Ratings
PARAMETER
SYMBOL
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
I/O Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
VDDA, R
VDD
VDDIO
VIL
VIH
VIHSMB
Storage Temperature
Junction Temperature
Input ESD protection
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
UNITS NOTES
MAX
4.6
4.6
4.6
V
V
V
V
V
V
GND-0.5
Except for SMBus interface
SMBus clock and data pins
VDD+0.5V
5.5V
-65
Human Body Model
°
150
125
C
°C
V
2000
1,2
1,2
1,2
1
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics–DIF_IN Clock Input Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
Input Crossover Voltage DIF_IN
Input Swing - DIF_IN
SYMBOL
CONDITIONS
MIN
VCROSS
Cross Over Voltage
150
TYP
MAX
UNITS NOTES
900
mV
1
V SWING
Differential value
300
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
IIN
V IN = VDD , V IN = GND
-5
5
uA
Input Duty Cycle
dtin
Measurement from differential wavefrom
45
55
%
1
Input Jitter - Cycle to Cycle
J DIFIn
Differential Measurement
0
125
ps
1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured through +/-75mV window centered around differential zero
Electrical Characteristics–Current Consumption
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
Powerdown Current
REVISION E 11/20/15
SYMBOL
CONDITIONS
IDDVDD
IDDVDDA/R
IDDVDDIO
IDDVDDPD
All outputs 100MHz, CL = 2pF; Zo = 85Ω
All outputs 100MHz, CL = 2pF; Zo = 85Ω
All outputs 100MHz, CL = 2pF; Zo = 85Ω
All differential pairs low-low
All differential pairs low-low
All differential pairs low-low
IDDVDDA/RPD
IDDVDDIOPD
5
MIN
TYP
MAX
UNITS
20
15
142
2.2
4.5
0.1
35
20
185
6
9
1
mA
mA
mA
NOTES
mA
mA
mA
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
Ambient Operating
Temperature
TCOM
Commmercial range
0
35
70
°C
Input High Voltage
VIH
2
VDD + 0.3
V
Input Low Voltage
VIL
GND - 0.3
0.8
V
IIN
Input Current
Input Frequency
Pin Inductance
Capacitance
IINP
Fibyp
Fipll
Fipll
Lpin
CIN
CINDIF_IN
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, VIN = GND, V IN = VDD
UNITS NOTES
-5
5
uA
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
-200
200
uA
V DD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
VDD = 3.3 V, 133.33MHz PLL mode
33
90
120
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
1.5
1.5
150
110
147
7
5
2.7
MHz
MHz
MHz
nH
pF
pF
2
2
2
1
1
1,4
6
pF
1
0.65
1
ms
2
31.5
33
kHz
25
300
us
1,3
5
ns
1,2
5
0.8
ns
V
V
V
mA
V
ns
ns
1,2
kHz
5
COUT
Output pin capacitance
Clk Stabilization
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
Tdrive_PD#
tDRVPD
Tfall
tF
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tR
VILSMB
VIHSMB
V OLSMB
IPULLUP
V DDSMB
tRSMB
tFSMB
@ IPULLUP
@ VOL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
fSMB
SMBus operating frequency
30
DIF output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
2.1
4
2.7
100
100.00
133.33
VDDSMB
0.4
5.5
1000
300
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
2
5
The differential input clock must be running for the SMBus to be active
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 6
REVISION E 11/20/15
9ZXL1950 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Slew rate
Slew rate matching
Trf
∆Trf
Scope averaging on
Slew rate matching.
1.5
2.7
8.8
MAX UNITS NOTES
4
20
Voltage High
VHigh
660
787
850
Voltage Low
VLow
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
-150
33
150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Vmax
Vmin
Vcross_abs
∆-Vcross
Single ended signal using absolute value.
Includes 300mV of over/undershoot. (Scope
Scope averaging off
Scope averaging off
845
9
471
14
1150
-300
250
V/ns
%
1, 2, 3
1, 2, 4
mV
550
140
mV
mV
mV
1, 5
1, 6
Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with Zo = 85Ω differential trace impedance.
1
2
Measured from differential waveform
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting ∆-Vcross to be smaller than Vcross absolute.
Clock Periods–Differential Outputs with Spread Spectrum Disabled
SSC OFF
Center
Freq.
MHz
DIF
100.00
133.33
1 Clock
1us
0.1s
-SSC
- ppm
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94900
9.99900
7.44925
7.49925
Measurement Window
0.1s
0.1s
+ ppm
0 ppm
Long-Term
Period
Average
Nominal
Max
10.00000
10.00100
7.50000
7.50075
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter
AbsPer
Max
10.05100
7.55075
Units Notes
ns
ns
1,2,3
1,2,4
Clock Periods–Differential Outputs with Spread Spectrum Enabled
SSC ON
Center
Freq.
MHz
DIF
99.75
133.00
1 Clock
1us
0.1s
- ppm
-SSC
-c2c jitter
Short-Term Long-Term
AbsPer
Average
Average
Min
Min
Min
9.94906
9.99906
10.02406
7.44930
7.49930
7.51805
Measurement Window
0.1s
0.1s
+ ppm
0 ppm
Long-Term
Period
Average
Nominal
Max
10.02506
10.02607
7.51880
7.51955
1us
+SSC
Short-Term
Average
Max
10.05107
7.53830
1 Clock
+c2c jitter
AbsPer
Max
10.10107
7.58830
Units Notes
ns
ns
1,2,3
1,2,4
Notes:
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+
accuracy requirements (+/-100ppm). The 9ZXL1950 itself does not contribute to ppm error.
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
REVISION E 11/20/15
7
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Electrical Characteristics–Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
Input-to-Output Skew in PLL mode
nominal value @ 35°C, 3.3V, 100MHz
Input-to-Output Skew in Bypass mode
nominal value @ 35°C, 3.3V
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
MIN
TYP
MAX
UNITS
NOTES
CLK_IN, DIF[x:0]
tSPO_PLL
-150
-117
-50
ps
1,2,4,5,8
CLK_IN, DIF[x:0]
tPD_BYP
2.5
3.6
4.5
ns
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_PLL
-50
0
50
ps
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across temperature for a given voltage
-250
0
250
ps
1,2,3,5,8
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
1
5
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
5
75
ps
1,2,3,5,8
DIF[x:0]
tSKEW_ALL
37
50
ps
1,2,3,8
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
jpeak-hibw
jpeak-lobw
pllHIBW
pllLOBW
tDC
0
0
2
0.7
45
1.8
0.7
3.3
1.2
50
2.5
2
4
1.4
55
dB
dB
MHz
MHz
%
7,8
7,8
8,9
8,9
1
Duty Cycle Distortion
tDCD
0
0.7
1.5
%
1,10
Jitter, Cycle to cycle
tjcyc-cyc
12
0
50
10
ps
ps
1,11
1,11
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode). 100MHz
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
PLL mode
Additive Jitter in Bypass Mode
Notes for preceding table:
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3
4
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
This parameter is deterministic for a given device
5
Measured with scope averaging on to find mean value.
6.
t is the period of the input clock
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11
Measured from differential waveform
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 8
REVISION E 11/20/15
9ZXL1950 DATASHEET
Electrical Characteristics–Phase Jitter Parameters
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
tjphPCIeG1
tjphPCIeG2
Phase Jitter, PLL Mode
tjphPCIeG3
tjphQPI_SMI
tjphPCIeG1
tjphPCIeG2
Additive Phase Jitter,
Bypass mode
tjphPCIeG3
tjphQPI_SMI
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
MIN
TYP
34
MAX
86
1.2
3
2.1
3.1
0.5
1
0.2
0.5
0.1
0.3
0.1
0.2
0.1
10
0.1
0.3
0.1
0.7
0.0
0.3
0.0
0.3
0.0
0.1
0.0
0.1
UNITS
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
ps
(rms)
1
Applies to all outputs.
2
See http://www.pcisig.com for complete specs
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4
Subject to final ratification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.4
6
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
Notes
1,2,3
1,2
1,2
1,2,4
1,5
1,5
1,5
1,2,3
1,2,6
1,2,6
1,2,4,6
1,5,6
1,5,6
1,5,6
Test Loads
Differential Output Terminations
DIF Zo (Ω)
Rs (Ω)
85
Internal
7.5
100
(External)
9ZXL Differential Test Loads
Rs
Zo = 85 Dif.,
10 inches
2pF
2pF
Rs
LP-HCSL
Differential
Output
REVISION E 11/20/15
9
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
General SMBus Serial Interface Information
How to Write
•
•
•
•
•
•
•
•
•
•
How to Read
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T
•
•
•
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
IDT (Slave/Receiver)
Controller (Host)
starT bit
T
Slave Address
WR
•
•
•
•
•
•
•
•
•
•
•
IDT (Slave/Receiver)
starT bit
Slave Address
WRite
ACK
WR
WRite
ACK
Beginning Byte = N
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
RT
Beginning Byte N
ACK
X Byte
O
O
O
Repeat starT
Slave Address
RD
ReaD
ACK
O
Data Byte Count=X
O
O
ACK
ACK
ACK
Beginning Byte N
Byte N + X - 1
stoP bit
X Byte
P
O
O
O
O
O
O
Byte N + X - 1
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 10
N
Not acknowledge
P
stoP bit
REVISION E 11/20/15
9ZXL1950 DATASHEET
9ZXL1950 SMBus Addressing
SMBus Address (Rd/Wrt bit = 0)
SADR(1:0)_tri
00
D8
0M
DA
01
DE
M0
C2
MM
C4
M1
C6
10
CA
1M
CC
11
CE
SMBusTable: PLL Mode, and Frequency Select Register
Byte 0
Pin #
Name
Control Function
PLL Mode 1
PLL Operating Mode Rd back 1
4
Bit 7
PLL Mode 0
PLL Operating Mode Rd back 0
4
Bit 6
72/71
DIF_18_En
Output Control
Bit 5
68/67
DIF_17_En
Output Control
Bit 4
66/65
DIF_16_En
Output Control
Bit 3
Reserved
Bit 2
Reserved
Bit 1
3
100M_133M#
Frequency Select Readback
Bit 0
Type
R
R
RW
RW
RW
0
1
See PLL Operating Mode
Readback Table
Low/Low
Enable
Low/Low
Enable
Low/Low
Enable
R
133MHz
100MHz
0
1
Low/Low
Enable
0
1
Low/Low
Enable
SMBusTable: Output Control Register
Byte 1
Pin #
Name
DIF_7_En
38/37
Bit 7
35/36
DIF_6_En
Bit 6
31/32
DIF_5_En
Bit 5
29/30
DIF_4_En
Bit 4
25/26
DIF_3_En
Bit 3
23/24
DIF_2_En
Bit 2
19/20
DIF_1_En
Bit 1
DIF_0_En
17/18
Bit 0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
SMBusTable: Output Control Register
Byte 2
Pin #
Name
DIF_15_En
62/61
Bit 7
DIF_14_En
60/59
Bit 6
56/55
DIF_13_En
Bit 5
DIF_12_En
54/53
Bit 4
DIF_11_En
50/49
Bit 3
48/47
DIF_10_En
Bit 2
DIF_9_En
44/43
Bit 1
42/41
DIF_8_En
Bit 0
Control Function
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Output Control
Type
RW
RW
RW
RW
RW
RW
RW
RW
Default
Latch
Latch
1
1
1
0
0
Latch
Default
1
1
1
1
1
1
1
1
Default
1
1
1
1
1
1
1
1
SMBusTable: PLL SW Override Control Register
Byte 3
Pin #
Name
Control Function
Type
0
1
Default
0
Reserved
Bit 7
0
Reserved
Bit 6
0
Reserved
Bit 5
0
Reserved
Bit 4
PLL_SW_EN
Enable S/W control of PLL BW
RW
HW Latch
SMBus Control
0
Bit 3
PLL Mode 1
PLL Operating Mode 1
RW
See PLL Operating Mode
1
Bit 2
PLL Mode 0
PLL Operating Mode 1
RW
1
Bit 1
Readback Table
Reserved
0
Bit 0
Note: Setting bit 3 to '1' allows the user to overide the Latch value from pin 4 via use of bits 2 and 1. Use the values from the PLL Operating
Mode Readback Table. Note that Byte 0, Bits 7:6 will keep the value originally latched on pin 4. A warm reset of the system will have to
accomplished if the user changes these bits.
REVISION E 11/20/15
11
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
SMBusTable: Reserved Register
Byte 4
Pin #
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SMBusTable: Vendor & Revision ID Register
Pin #
Name
Byte 5
RID3
Bit 7
RID2
Bit 6
RID1
Bit 5
RID0
Bit 4
VID3
Bit 3
VID2
Bit 2
VID1
Bit 1
VID0
Bit 0
SMBusTable: DEVICE ID
Pin #
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
SMBusTable: Byte Count Register
Pin #
Name
Byte 7
Bit 7
Bit 6
Bit 5
BC4
Bit 4
BC3
Bit 3
BC2
Bit 2
BC1
Bit 1
BC0
Bit 0
SMBusTable: Reserved Register
Pin #
Name
Byte 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Type
0
1
Default
0
0
0
0
0
0
0
0
Control Function
Type
R
R
R
R
R
R
R
R
0
1
-
-
Default
X
X
X
X
0
0
0
1
Type
R
R
R
R
R
R
R
R
0
1
REVISION ID
VENDOR ID
Control Function
Device ID 7 (MSB)
Device ID 6
Device ID 5
Device ID 4
Device ID 3
Device ID 2
Device ID 1
Device ID 0
Control Function
Reserved
Reserved
Reserved
Writing to this register configures how
many bytes will be read back.
Control Function
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 12
Type
RW
RW
RW
RW
RW
Type
A rev = 0000
B rev = 0001
etc.
Default
1
1
0
0
0
0
1
1
1950 is 195 Decimal
or C3 Hex
1550 is 155 Decimal
or 9B Hex
0
1
Default value is 8 hex, so 9
bytes (0 to 8) will be read back
by default.
0
1
Default
0
0
0
0
1
0
0
0
Default
0
0
0
0
0
0
0
0
REVISION E 11/20/15
9ZXL1950 DATASHEET
Alternate Terminations
The 9ZXL1950 can be terminated to other logic families. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's
"Universal" Low-Power HCSL Outputs” for details.
Marking Diagram
ICS
9ZXL1950BKLF
LOT
YYWW
Notes:
1. “LOT” denotes the lot number.
2. “YYWW” is the last two digits of the year and week that the part was assembled.
3. “LF” denotes RoHS compliant package.
4. Bottom marking: country of origin if not USA.
REVISION E 11/20/15
13
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Package Outline and Package Dimensions (NLG72)
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 14
REVISION E 11/20/15
9ZXL1950 DATASHEET
Package Outline and Package Dimensions (NLG72), cont. Use EPAD Option P1.
REVISION E 11/20/15
15
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
9ZXL1950 DATASHEET
Package Outline and Package Dimensions (NLG72), cont. Use P1 EPAD 5.9mm SAWN pattern.
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS 16
REVISION E 11/20/15
9ZXL1950 DATASHEET
Ordering Information
Part / Order Number
9ZXL1950BKLF
9ZXL1950BKLFT
Shipping Package
Trays
Tape and Reel
Package
72-pin VFQFPN
72-pin VFQFPN
Temperature
0 to +70°C
0 to +70°C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“B” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev.
A
B
C
D
E
Issuer Issue Date Description
RDW
3/11/2014 Moved to final.
1. Cleaned up output pin names to be DIFxx instead of DIF_xx
2. Updated electrical tables to new format
RDW
3/7/2015 3. Updated ordering info to B rev along with Rev ID.
4. Updated termination schemes for driving LVDS.
5. Minor cleanup/reformatting of DS, including front page text.
RDW
6/16/2015 Added landing pattern from POD
1. Tightened O2O spec from 75 to 50ps
2. Added epad (pin 73) to power connections table
3. Updated pin 73 pin name from "GND" to "epad"
4. Clarified SMBus operating frequency by removing the word "Maximum"
RDW
7/30/2015
and updated the symbol from fMINSMB to fSMB
5. Tightened duty cycle distortion and additive cycle to cycle jitter specs
6. Updated Rs from 7 to 7.5 ohms in Test Loads Table
7. Replaced LVDS termination info with reference to AN891.
RDW
11/20/2015
REVISION E 11/20/15
1. Updated QPI references to QPI/UPI
2. Updated DIF_IN table to match PCI SIG specification, no silicon change
17
Page #
Various
17
1,8
2
4
6
8
9
13
1,5
19-OUTPUT DB1900Z LOW-POWER DERIVATIVE W/85OHM TERMINATIONS
Corporate Headquarters
Sales
Support
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com
www.idt.com/go/support
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in
this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined
in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether
express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This
document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT’s products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Product specification subject to change without notice. Other trademarks and service marks used herein, including protected
names, logos and designs, are the property of IDT or their respective third party owners.
Copyright ©2015 Integrated Device Technology, Inc.. All rights reserved.