High-Frequency Characterization and Circuit
Modeling of Via in Multi-Layered IC Package
Research Area: Transmission Lines
Hyewon Kim and Yungseon Eo
Dept. Electrical and Computer Engineering
Hanyang University
Ansan, Korea
hwkim@giga.hanyang.ac.kr, eo@giga.hanyang.ac.kr
Abstract—A via is experimentally characterized by using highfrequency s-parameter measurements. Test patterns are designed
and fabricated by using a package process. They are measured
by using VNA (vector network analyzer) up to 25GHz. The
parasitic effects due to access lines for on-wafer probing are deembedded. Then modeling the via as two equivalent circuits (Ttype and Pi-type), the circuit model parameters are determined.
It is shown that the T-type circuit model has excellent agreement
with the measured s-parameters.
Keywords-via; s-parameter; de-embedding; circuit model
I.
INTRODUCTION
Both the level of integration and the operating frequency of
today’s integrated circuits are now plunged into the Giga-scale
( × 109 ) [1]. As the scale-down of the semiconductor process
technology approaches a physical limitation, recently, 3dimensional integration technologies such as “through silicon
via (TSV)” and “package on package (POP)” become one of
the technical issues [2]-[7]. In such gigantic high-frequencyoperating integrated electronic systems, the signal integrity
degradation of interconnect lines between the circuit subblocks substantially limits the circuit performance [8]-[10].
In order to integrate more transistors in a small silicon die,
many metal layers are required. Even in today’s high-density
integrated circuits, metal layers exceed more than 8 [1].
However, in the future 3-dimensional integrated systems, much
more metal layers are definitely required. In such multi-layered
integrated systems, lots of vias are inevitable. It is well known
that the distribution of vias is strongly related with geometrical
structures and routing algorithms [11]. In geometrically far
more complicated future 3-dimensional chips or packages, the
vias may have a much more significant effect on the circuit
performance. Thus, for the sake of a reliable circuit design, the
via effects have to be taken into account in the early phase of
the circuit design.
To date, there have been many techniques to characterize
and model vias [12]-[21]. However, most of them are based on
numerical calculation [12]-[14], commercial field solvers
[15][16], or simple models [17][18]. Relatively, there are only
a few experimental characterization techniques [19]-[21].
In practice, it is inherently difficult to accurately
characterize a small via because of parasitics. Further, an air
calibration using SMA connectors may not be suitable for deembedding the parasitic effects. In this paper, a novel waferlevel high-frequency characterization technique for the via is
presented.
II.
EXPERIMENTS FOR TEST PATTERNS
Since a via is too tiny in its size to be accurately
characterized in high-frequencies by using SMA connectors, a
wafer level characterization technique should be employed.
However, the wafer-level probing for 2-port network
measurements requires a pair of contact pads on the same plane.
Otherwise, the two port measurements may not be possible.
Thus, two vias should be considered a pair for the wafer-level
via characterizations. That is, one is a top to bottom via and the
other is a bottom to top via. Furthermore, access lines between
the contact pad and the via are required. Test patterns for a
wafer level characterization are designed and fabricated by
using a package process as shown in Fig. 1. The test pattern
layout and its cross-sectional dimensions are described in Fig.
2 and Fig. 3, respectively.
Figure 1. Picture of a test module
Figure 2. Top view of the test structure
CIRCUIT MODEL AND PARAMETER DETERMINATION
300um
III.
In order to de-embed the parasitic access line effects, the
measured s-parameter data of the test structure are represented
by using ABCD parameters
⎡A B⎤
⎡A B⎤ ⎡A B⎤ ⎡A B⎤ .
⎢C D ⎥ = ⎢C D ⎥ ⎢C D ⎥ ⎢ C D ⎥
⎣
⎦ total ⎣
⎦ line ⎣
⎦ via ⎣
⎦ line
(1)
Thus, the de-embedded s-parameters for DUT (device under
test) can be readily determined as follows.
Figure 3. The cross-sectional view of the test structure
Zo
Zo
a1
b1
⎡T11p T12p ⎤
⎢ p
p⎥
⎣T21 T22 ⎦
⎡T11via T12via ⎤ ⎡T11p T12p ⎤
⎢ via via ⎥ ⎢T p T p ⎥
⎣T21 T22 ⎦ ⎣ 21 22 ⎦
a2
b2
-1
Zo
Zo
Figure 4. Network representation of a test pattern. Note, T-parameters are
used for the cascaded network.
A VNA (Vector Network Analyzer) for the test pattern
measurements is calibrated by SOLT (short, open, load, and
thru) calibration method up to probe tips. Then, s-parameters
for the test patterns including access lines as shown in Fig. 4
are measured from 50MHz to 25GHz by using on-wafer probe
tips (Cascade Microtech GSG probe tips). Note, although the
access lines are inevitable for the wafer level measurements,
the effects have to be de-embedded for an accurate
characterization. Thus, a 0.5 mm-long line is designed on the
same test module for the purpose of the parasitic effect deembedding.
In order to investigate how much the vias have an effect on
signal integrity, the s-parameters of the line including vias are
compared with the straight lines in Fig. 5. Note that the line
including vias has much more significant signal integrity
degradation than the straight lines. Although the total length of
the line including vias is 1.1mm long, its S21 characteristic is
worse than that of the 5mm long straight line.
(2)
Note, there is large discrepancy between the de-embedded sparameter data and those without de-embedding as shown in
Fig. 6.
Considering the electromagnetic field distribution of a signal
line through two vias as schematically described in Fig. 7, a via
may be represented with one of the possible two circuit
models: T-type model as shown in Fig. 8 and Pi-type model as
shown in Fig. 9. In the T-type model of Fig. 8, the measured sparameter data can be equated by using ABCD network
parameters as follows
⎡ Z1
⎢1+ Z
⎡A B⎤
3
=⎢
⎢C D ⎥
⎣
⎦ measured ⎢ 1
⎢ Z
⎣ 3
Z1 Z 2 + Z 2 Z 3 + Z 3 Z1 ⎤
⎥
, (3)
⎥
⎥
⎥
⎦ T-Type
Z3
1+
Z2
Z3
where the measurement reference impedance is Z 0 = 50 [Ω] .
Thus, the circuit model parameters for the T-type can be
determined as follows
Im (1 Z 3 )
ω
Im ( Z 2 )
ω
0.0
=
=
Im ( C )
2πf
T
= Cvia ,
Im ( ( D − 1) C )
2πf
=
(4)
LTvia .
S21
0
(5)
0
S11
straight line : 1mm
-1.0
straight line : 2mm
-1.5
-20
-1
-40
-2
straight line : 5mm
non-de-embedded
de-embedded
de-embedded Via
-60
-2.0
0
5
10
15
20
25
Frequency [GHz]
Figure 5. Comparison of the line including vias with straight lines
0
5
10
15
20
-3
25
Frequency [GHz]
Figure 6. Via test structure characteristics after de-embedding
S21 [dB]
S11 [dB]
-0.5
S21 [dB]
-1
⎡A B⎤
⎡A B⎤ ⎡A B⎤
⎡A B⎤ .
=⎢
⎢C D ⎥
⎥
⎢
⎥
⎢
⎥
⎣
⎦ via
⎣C D ⎦ line ⎣C D ⎦ total ⎣C D ⎦ line
The total inductances and total capacitances of the test structure
are compared in Fig. 10 and Fig. 11, respectively. Note,
regardless of the circuit models (i.e., T-type model and Pi-type
model) of the test structure, the circuit model parameters show
perfect agreement each other up to 5GHz. On the contrary, as
the frequency increases, they show large discrepancy. The
deviation of the circuit model parameters in the high-frequency
is considered due to the simple lumped circuit models. Thus,
the values of the 100MHz to 5GHz are averaged for the circuit
model parameters. The total inductance and total capacitance
are 0.26nH and 0.27pF, respectively. Both T-type model and
Pi-type model are represented in Fig. 12 by using the extracted
circuit model parameters.
Figure 7. Conceptual description of electro-magnetic field distribution
for the circuit model of the test structure
T
Z1 Lvia
Zo
In order to verify the accuracy of the experimental
characterization, the s-parameters are determined by
performing HSPICE simulations. As shown in Fig. 13, the
LTvia Z
2
T
Cvia
Z3
Zo
0.5
2 LTvia
0.4
Inductance [nH]
Figure 8. T-type circuit model of the vias
0.3
0.2
Lπvia
0.1
Figure 9. Pi-type circuit model of the vias
0.0
Y
⎡
1+ 2
⎢
Y3
⎡A B⎤
=⎢
⎢C D ⎥
⎣
⎦ measured ⎢ Y1Y2 +Y2Y3 +Y3Y1
⎢
Y3
⎣
1 ⎤
Y3 ⎥
, (6)
⎥
Y ⎥
1+ 1 ⎥
Y3 ⎦ Pi-Type
the circuit model parameters can be determined as follows
Im (1 Y3 )
ω
Im ( Y1 )
ω
=
=
Im ( B )
2πf
=
Lπvia ,
Im ( ( D − 1) B )
2πf
π
= Cvia .
(7)
5
15
20
25
Figure 10. Extracted total inductances for the test structure
0.5
T
Cvia
0.4
0.3
0.2
π
2Cvia
0.1
(8)
10
Frequency [GHz]
Capacitance [pF]
Similarly, since ABCD parameters for the Pi-type circuit
model are
0
0.0
0
5
10
15
20
25
Frequency [GHz]
Figure 11. Extracted total capacitances for the test structure
IV.
VERIFICATION OF THE CIRCUIT MODEL
The circuit model parameters corresponding to the T-type
model or Pi-type model can be determined by using (4), (5), (7),
and (8), respectively. Total inductances and total capacitances
for each circuit model are defined as follows
π
π
LTtotal ≡ 2 LTvia , Ltotal ≡ Lvia ,
π
π
T
T
, Ctotal
.
≡ 2Cvia
Ctotal
≡ Cvia
(9)
(10)
Figure 12. T-type circuit model and Pi-type circuit model with
experimentally extracted circuit model parameters
simulated s-parameters using the T-type circuit model has
excellent agreement with the measured s-parameters up to
20GHz. In contrast, the Pi-type circuit model shows
discrepancy with the measured data from 10GHz. It is
understandable since the vertical via structure may be
inductive-prominent at the beginning and then capacitive due
to the line in the bottom signal line. Thus, it is considered that
the T-type circuit model for the via test structure is better than
the Pi-type circuit model.
V.
REFERENCES
[1]
[2]
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CONCLUSION
A via has a significant effect on the signal integrity of
high-speed integrated circuits and packages. In this work, vias
were experimentally characterized up to 25GHz. Then,
representing the via with the T- and Pi-network, the circuit
model parameters were directly determined by using the
measured s-parameters. It was shown that the simulated sparameters using the T-type circuit model have excellent
agreement with the measured s-parameters.
[5]
[6]
[7]
[8]
[9]
T-model
0
S11 [dB]
[10]
-20
[11]
Pi-model
[12]
-40
Measurement
[13]
-60
0
5
10
15
20
25
[14]
Frequency [GHz]
Figure 13. S11 comparison between T-type circuit model and Pi-type
circuit model
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S21 [dB]
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[18]
-1
T-model
[19]
-2
[20]
Measurement
-3
0
5
10
15
20
25
Frequency [GHz]
Figure 14. S21 comparison between T-type circuit model and Pi-type
circuit model
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