LT6402-20
300MHz Low Distortion, Low
Noise Differential Amplifier/
ADC Driver (AV = 20dB)
DESCRIPTIO
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FEATURES
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The LT®6402-20 is a low distortion, low noise differential
amplifier/ADC driver for use in applications from DC to
300MHz. The LT6402-20 has been designed for ease of
use, with minimal support circuitry required. Exceptionally
low input-referred noise and low distortion (with either
single-ended or differential inputs) make the LT6402-20
an excellent solution for driving high speed 12-bit and
14-bit ADCs. In addition to the normal unfiltered outputs
(+OUT and –OUT), the LT6402-20 has a built-in 75MHz
differential low pass filter and an additional pair of filtered
outputs (+OUTFILTERED, –OUTFILTERED) to reduce
external filtering components when driving high speed
ADCs. The output common mode voltage is easily set via
the VOCM pin, eliminating an output transformer or ACcoupling capacitors in many applications.
300 MHz –3dB Bandwidth
Fixed Gain of 20dB
Low Distortion:
51dBm OIP3, –81dBc HD3 (20MHz, 2VP-P)
Low Noise:
12.4dB NF, en = 1.9nV/√Hz (20MHz)
Differential Inputs and Outputs
Additional Filtered Outputs
Adjustable Output Common Mode Voltage
DC- or AC-Coupled Operation
Minimal Support Circuitry Required
Small 0.75mm Profile 16-Lead 3mm × 3mm QFN
Package
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APPLICATIO S
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The LT6402-20 is designed to meet the demanding requirements of communications transceiver applications. It can
be used as a differential ADC driver, a general-purpose
differential gain block, or in other applications requiring
differential drive. The LT6402-20 can be used in data
acquisition systems required to function at frequencies
down to DC.
Differential ADC Driver for:
Imaging
Communications
Differential Driver/Receiver
Single Ended to Differential Conversion
Differential to Single Ended Conversion
Level Shifting
IF Sampling Receivers
SAW Filter Interfacing/Buffering
The LT6402-20 operates on a 5V supply and consumes
30mA. It comes in a compact 16-lead 3mm × 3mm QFN package and operates over a –40°C to 85°C temperature range.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
U
TYPICAL APPLICATIO
Distortion vs Frequency, Differential
Input, No RLOAD
–40
5V
FILTERED OUTPUTS
VOUT = 2VP-P
–50
0.1µF
0.1µF
–INB
–INA
VCC
VOCM
+OUT
0.1µF
LT6402-20
–OUT
0.1µF
IF IN
+INB
+INA
10Ω
10Ω
VCM
AIN+
LTC®2249
DISTORTION (dBc)
■
–60
–70
HD3
–80
AIN–
–90
VEE
HD2
–100
6402 TA01a
1
10
FREQUENCY (MHz)
100
64022 G08
640220fa
1
LT6402-20
U
W W
W
ABSOLUTE
AXI U RATI GS
U
W
U
PACKAGE/ORDER I FOR ATIO
(Note 1)
–INB
–INA
+INA
+INB
TOP VIEW
Total Supply Voltage (VCCA/VCCB/VCCC to
VEEA/VEEB/VEEC) ...................................................5.5V
Input Current (+INA, –INA, +INB, –INB,
VOCM, ENABLE)................................................±10mA
Output Current (Continuous)
+OUT, –OUT ...................................................±100mA
+OUTFILTERED, –OUTFILTERED......................±30mA
Output Short Circuit Duration (Note 2) ............ Indefinite
Operating Temperature Range (Note 3) ... –40°C to 85°C
Specified Temperature Range (Note 4) .... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
Junction Temperature ........................................... 125°C
Lead Temperature Range (Soldering 10 sec) ........ 300°C
16 15 14 13
12 VEEC
VCCC 1
VOCM 2
11 ENABLE
17
VCCA 3
10 VCCB
VEEA 4
6
7
8
+OUT
+OUTFILTERED
–OUTFILTERED
–OUT
9
5
VEEB
UD PACKAGE
16-LEAD (3mm × 3mm) PLASTIC QFN
TJMAX = 125°C, θJA = 68°C/W, θJC = 4.2°C/W
EXPOSED PAD IS VEE (PIN 17)
MUST BE SOLDERED TO THE PCB
ORDER PART NUMBER
UD PART MARKING*
LT6402CUD-20
LT6402IUD-20
LCBC
LCBC
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA
shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
18.9
20
20.9
dB
0.25
0.35
0.5
V
V
Input/Output Characteristics (+INA, +INB, –INA, –INB, +OUT, –OUT, +OUTFILTERED, –OUTFILTERED)
GDIFF
Gain
VSWINGMIN
VSWINGMAX
VSWINGDIFF
Output Voltage Swing
IOUT
Output Current Drive
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Drift
Differential (+OUT, –OUT), VIN = ±160mV
Differential
●
Single-Ended +OUT, –OUT, +OUTFILTERED,
–OUTFILTERED, VIN = ±600mV Differential
●
Single-Ended +OUT, –OUT, +OUTFILTERED,
–OUTFILTERED, VIN = ±600mV Differential
3.4
3.3
3.6
●
Differential (+OUT, –OUT), VIN = ±600mV
Differential
6.1
5.6
7
●
VP-P
VP-P
●
±30
±35
mA
–6.5
–10
1
●
TMIN to TMAX
●
2.5
V
V
6.5
10
mV
mV
µV/°C
640220fa
2
LT6402-20
DC ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V, ⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA
shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
IVRMIN
Input Voltage Range, MIN
Single-Ended
●
IVRMAX
Input Voltage Range, MAX
Single-Ended
●
3.9
●
77
RINDIFF
Input Resistance
CINDIFF
Input Capacitance
CMRR
Common Mode Rejection Ratio
ROUTDIFF
COUTDIFF
MIN
TYP
MAX
0.9
UNITS
V
V
100
122
Ω
1
pF
70
dB
Output Resistance
0.3
Ω
Output Capacitance
0.8
pF
Input Common Mode 0.9V to 3.9V
●
45
Common Mode Voltage Control (VOCM Pin)
GCM
VOCMMIN
VOCMMAX
Common Mode Gain
Differential (+OUT, –OUT), VOCM = 1.2V to 3.6V
Differential (+OUT, –OUT), VOCM = 1.4V to 3.4V
Output Common Mode Voltage
Adjustment Range, MIN
●
0.9
0.9
1
●
Output Common Mode Voltage
Adjustment Range, MAX
Single-Ended
VOSCM
Output Common Mode Offset
Voltage
Measured from VOCM to Average of +OUT and –OUT
IBIASCM
VOCM Input Bias Current
●
RINCM
VOCM Input Resistance
●
CINCM
VOCM Input Capacitance
●
1.1
1.1
V/V
V/V
1.2
1.4
V
V
3.6
3.4
–30
0.8
V
V
4
30
mV
5
15
µA
3
MΩ
1
pF
⎯E⎯N⎯A⎯B⎯L⎯E Pin
VIL
⎯E⎯N⎯A⎯B⎯L⎯E Input Low Voltage
●
VIH
⎯E⎯N⎯A⎯B⎯L⎯E Input High Voltage
●
IIL
⎯E⎯N⎯A⎯B⎯L⎯E Input Low Current
⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V
●
IIH
⎯E⎯N⎯A⎯B⎯L⎯E Input High Current
⎯E⎯N⎯A⎯B⎯L⎯E = 2V
●
0.8
2
V
V
0.5
µA
1
3
µA
Power Supply
VS
Operating Range
●
4
5
5.5
V
IS
Supply Current
⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V
●
24
30
37
mA
ISDISABLED
Supply Current (Disabled)
⎯E⎯N⎯A⎯B⎯L⎯E = 2V
●
250
500
µA
PSRR
Power Supply Rejection Ratio
4V to 5.5V
●
55
90
dB
640220fa
3
LT6402-20
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCCA = VCCB = VCCC = 5V, VEEA = VEEB = VEEC = 0V,
⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
200
300
MHz
30
MHz
Input/Output Characteristics
–3dBBW
–3dB Bandwidth
20mVP-P Differential (+OUT, –OUT)
0.1dBBW
Bandwidth for 0.1dB Flatness
20mVP-P Differential (+OUT, –OUT)
0.5dBBW
Bandwidth for 0.5dB Flatness
20mVP-P Differential (+OUT, –OUT)
80
MHz
SR
Slew Rate
3.2VP-P Differential (+OUT, –OUT)
400
V/µs
ts1%
1% Settling
1% Settling for a 1VP-P Differential Step
(+OUT, –OUT)
tON
tOFF
8
ns
Turn-On Time
100
ns
Turn-Off Time
1
µs
Common Mode Voltage Control (VOCM Pin)
–3dBBWCM
Common Mode Small-Signal –3dB
Bandwidth
0.1VP-P at VOCM, Measured Single-Ended at +OUT
and –OUT
200
MHz
SRCM
Common Mode Slew Rate
1.3V to 3.4V Step at VOCM
250
V/µs
2VP-P Differential (+OUTFILTERED, –OUTFILTERED)
–85
dBc
2VP-P Differential (+OUT, –OUT)
–85
dBc
Third-Order IMD
2VP-P Differential Composite (+OUTFILTERED,
–OUTFILTERED), f1 = 9.5MHz, f2 = 10.5MHz
–93
dBc
OIP310M
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 9.5MHz, f2 = 10.5MHz (Note 5)
49.5
dBm
NF
Noise Figure
Measured Using DC954A Demo Board
12.3
dB
en10M
Input Referred Noise Voltage Density
1.85
nV/√Hz
Noise/Harmonic Performance Input/Output Characteristics
10MHz Signal
Second/Third Harmonic Distortion
1dB Compression Point
RL = 100Ω (Note 5)
19.5
dBm
Second/Third Harmonic Distortion
2VP-P Differential (+OUTFILTERED, –OUTFILTERED)
–81
dBc
2VP-P Differential (+OUT, –OUT)
–81
dBc
2VP-P Differential Composite (+OUTFILTERED,
–OUTFILTERED), f1 = 19.5MHz, f2 = 20.5MHz
–96
dBc
2VP-P Differential Composite (+OUT, –OUT),
RL = 400Ω, f1 = 19.5MHz, f2 = 20.5MHz
–91
dBc
51
dBm
20MHz Signal
Third-Order IMD
OIP320M
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 19.5MHz, f2 = 20.5MHz (Note 5)
NF
Noise Figure
Measured Using DC954A Demo Board
en20M
Input Referred Noise Voltage Density
1dB Compression Point
RL = 100Ω (Note 5)
12.4
dB
1.9
nV/√Hz
18
dBm
640220fa
4
LT6402-20
AC ELECTRICAL CHARACTERISTICS
TA = 25°C, VCCA = VCCB = VCCC = 5V,VEEA = VEEB = VEEC = 0V,
⎯E⎯N⎯A⎯B⎯L⎯E = 0.8V, +INA shorted to +INB (+IN), –INA shorted to –INB (–IN), VOCM = 2.2V, Input common mode voltage = 2.2V, no RLOAD
unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Second/Third Harmonic Distortion
2VP-P Differential (+OUTFILTERED, –OUTFILTERED)
–80
dBc
2VP-P Differential (+OUT, –OUT)
–80
dBc
2VP-P Differential Composite (+OUTFILTERED,
–OUTFILTERED), f1 = 24.5MHz, f2 = 25.5MHz
–86
dBc
2VP-P Differential Composite (+OUT, –OUT),
RL = 400Ω, f1 = 24.5MHz, f2 = 25.5MHz
–84
dBc
46
dBm
25MHz Signal
Third-Order IMD
OIP325M
Output Third-Order Intercept
Differential (+OUTFILTERED, –OUTFILTERED),
f1 = 24.5MHz, f2 = 25.5MHz (Note 5)
NF
Noise Figure
Measured Using DC954A Demo Board
en25M
Input Referred Noise Voltage Density
RL = 100Ω (Note 5)
1dB Compression Point
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: As long as output current and junction temperature are kept below
the Absolute Maximum Ratings, no damage to the part will occur.
Note 3: The LT6402 is guaranteed functional over the operating
temperature range of –40°C to 85°C.
12.5
dB
1.9
nV/√Hz
16.6
dBm
Note 4: The LT6402C is guaranteed to meet specified performance from
0°C to 70°C. It is designed, characterized and expected to meet specified
performance from –40°C and 85°C but is not tested or QA sampled
at these temperatures. The LT6402I is guaranteed to meet specified
performance from –40°C to 85°C.
Note 5: Since the LT6402-20 is a feedback amplifier with low output
impedance, a resistive load is not required when driving an ADC.
Therefore, typical output power is very small. In order to compare the
LT6402-20 with typical gm amplifiers that require 50Ω output loading, the
LT6402-20 output voltage swing driving an ADC is converted to OIP3 and
P1dB as if it were driving a 50Ω load.
TYPICAL PERFORMANCE CHARACTERISTICS
Frequency Response
RLOAD = 400Ω
30
35
25
30
25
FILTERED
10
5
20
15
10
0
VIN = 20mVP-P
UNFILTERED: RLOAD = 400Ω
–5
FILTERED: RLOAD = 300Ω (EXTERNAL)
+ 100Ω (INTERNAL, FILTERED OUTPUTS)
–10
10
100
1000
1
FREQUENCY (MHz)
64022 G01
UNFILTERED
20
25
GAIN (dB)
15
30
VIN = 20mVP-P
UNFILTERED OUTPUTS
UNFILTERED
GAIN (dB)
GAIN (dB)
20
Frequency Response
RLOAD = 100Ω
Frequency Response vs
CLOAD, RLOAD = 400Ω
0
1
10
100
FREQUENCY (MHz)
FILTERED
10
5
0
0pF
1.6pF
5pF
10pF
5
15
VIN = 20mVP-P
UNFILTERED: RLOAD = 100Ω
FILTERED: RLOAD = 100Ω
(INTERNAL, FILTERED OUTPUTS)
–5
–10
1000
34022 G02
1
10
100
FREQUENCY (MHz)
1000
64022 G03
640220fa
5
LT6402-20
U W
TYPICAL PERFOR A CE CHARACTERISTICS
–60
–60
–70
–70
UNFILTERED OUTPUTS
–85
–90
FILTERED OUTPUTS
–80
–85
–90
–95
–100
–105
–105
–110
55
–75
–100
FILTERED OUTPUTS
35
30
20
25
15
FREQUENCY (MHz)
–40
2 TONES, 2VP-P COMPOSITE
1MHz TONE SPACING
55
DISTORTION (dBc)
UNFILTERED OUTPUTS
35
30
–40
FILTERED OUTPUTS
VOUT = 2VP-P
–60
–70
HD3
–80
15
20
25
FREQUENCY (MHz)
30
10
FREQUENCY (MHz)
Distortion vs Output Amplitude
20MHz Differential Input,
No RLOAD (Filtered)
–70
DISTORTION (dBc)
DISTORTION (dBc)
–85
HD3
–76
–78
HD2
–80
HD3
–82
–90
–84
–95
0
1
2 3 4 5 6 7 8
OUTPUT AMPLITUDE (dBm)
9
10
64022 G12
10
FREQUENCY (MHz)
– 86
64022 G10
25
20
15
1
2 3 4 5 6 7 8
OUTPUT AMPLITUDE (dBm)
9
10
64022 G13
400Ω LOAD
10
100Ω LOAD
5
0
–5
–10
0
100
Output 1dB Compression
vs Frequency
UNFILTERED OUTPUTS
20MHz DIFFERENTIAL INPUT
NO RLOAD
–72
HD2
HD2
1
100
–74
–80
HD3
–80
Distortion vs Output Amplitude
20MHz Differential Input,
No RLOAD (Unfiltered)
FILTERED OUTPUTS
20MHz DIFFERENTIAL INPUT
NO RLOAD
–75
–70
64022 G08
64022 G07
–70
–60
–100
1
35
35
UNFILTERED OUTPUTS
VOUT = 2VP-P
–90
HD2
–100
10
30
–50
–90
5
15
20
25
FREQUENCY (MHz)
64022 G06
OUTPUT 1dB COMPRESSION (dBm)
OUTPUT IP3 (dBm)
40
10
Distortion vs Frequency,
Differential Input, No RLOAD
(Unfiltered)
–50
FILTERED OUTPUTS
45
5
64022 G05
Distortion vs Frequency,
Differential Input, No RLOAD
(Filtered)
50
UNFILTERED OUTPUTS
40
35
30
64022 G04
Output Third Order Intercept vs
Frequency, Differential Input,
RLOAD = 400Ω
60
45
30
10
5
DISTORTION (dBc)
20
25
15
FREQUENCY (MHz)
FILTERED OUTPUTS
50
35
–110
10
5
2 TONES, 2VP-P COMPOSITE
1MHz TONE SPACING
UNFILTERED OUTPUTS
OUTPUT IP3 (dBm)
–75
–95
60
2 TONES, 2VP-P COMPOSITE
–65 1MHz TONE SPACING
THIRD ORDER IMD (dBc)
THIRD ORDER IMD (dBc)
2 TONES, 2VP-P COMPOSITE
–65 1MHz TONE SPACING
–80
Output Third Order Intercept vs
Frequency, Differential Input,
No RLOAD
Third Order Intermodulation
Distortion vs Frequency
Differential Input, RLOAD = 400Ω
Third Order Intermodulation
Distortion vs Frequency
Differential Input, No RLOAD
UNFILTERED OUTPUTS
1
10
100
FREQUENCY (Hz)
1000
64022 G14
640220fa
6
LT6402-20
U W
TYPICAL PERFOR A CE CHARACTERISTICS
Input Referred Noise Voltage
vs Frequency
Noise Figure vs Frequency
NOISE FIGURE (dB)
25
20
15
10
MEASURED USING DC954A DEMO BOARD
5
10
100
FREQUENCY (MHz)
–30
7
–40
6
–50
5
4
3
–100
0
–110
10
100
FREQUENCY (MHz)
1
1000
0
UNFILTERED OUTPUTS
INPUT REFLECTION COEFFICIENT (S11)
250
200
150
IMPEDANCE MAGNITUDE
50
0
100
10
1
IMPEDANCE PHASE
–100
10
1000
100
FREQUENCY (MHz)
Output Reflection Coefficient
vs Frequency
–20
–25
–30
1
110
PSRR, CMRR (dB)
–20
–25
–30
RLOAD = 100Ω PER OUTPUT
PSRR
90
80
70
CMRR
60
50
2.25
2.20
2.15
40
30
TIME (5ns/DIV)
20
–35
1000
Small-Signal Transient Response
UNFILTERED OUTPUTS
100
–10
–15
10
100
FREQUENCY (MHz)
34022 G20
PSRR, CMRR vs Frequency
120
MEASURED USING
DC954A DEMO BOARD
–5
–15
64022 G19
64022 G18
0
–10
1000
OUTPUT VOLTAGE (V)
10
100
FREQUENCY (MHz)
MEASURED USING
DC954A DEMO BOARD
–5
–35
0
1
1000
Input Reflection Coefficient
vs Frequency
350
300
10
100
FREQUENCY (MHz)
64022 G17
Differential Output Impedance
vs Frequency
OUTPUT IMPEDANCE (Ω)
INPUT IMPEDANCE (MAGNITUDE Ω, PHASE°)
1000
64022 G16
400
–50
–80
1
Differential Input Impedance
vs Frequency
100
–70
–90
1000
UNFILTERED OUTPUTS
–60
2
64022 G15
OUTPUT REFLECTION COEFFICIENT (S22)
Isolation vs Frequency
8
ISOLATION (dB)
INPUT REFERRED NOISE VOLTAGE (nV/√Hz)
30
64022 G23
10
–40
0
1
10
100
FREQUENCY (MHz)
1000
64022 G21
1
10
100
FREQUENCY (MHz)
1000
64022 G22
640220fa
7
LT6402-20
TYPICAL PERFORMANCE CHARACTERISTICS
Large-Signal Transient Response
3.4
Overdrive Recovery Time
4.0
RLOAD = 100Ω PER OUTPUT
3.2
3.5
+OUT
2.4
2.2
2.0
1.8
DISTORTION (dBc)
2.6
FILTERED OUTPUTS, NO RLOAD
VOUT = 20MHz 2VP-P
–82
3.0
OUTPUT VOLTAGE (V)
2.8
–80
RLOAD = 100Ω PER OUTPUT
3.0
OUTPUT VOLTAGE (V)
Distortion vs Output Common
Mode Voltage LT6402-20 Driving
LTC2249 14-Bit ADC
2.5
2.0
1.5
HD3
–84
–86
HD2
1.0
–88
1.6
0.5
1.4
–OUT
0
1.2
–90
TIME (25ns/DIV)
TIME (10ns/DIV)
1
64022 G25
64022 G24
1.2 1.4 1.6 1.8
2.0 2.2 2.4
OUTPUT COMMON MODE VOLTAGE (V)
64022 G26
Turn-On Time
Turn-Off Time
RLOAD = 1009
PER OUTPUT
3.5
3.5
+OUT
2.5
2.0
–OUT
1.5
ENABLE
1.0
–20
–30
+OUT
2.5
2.0
–OUT
1.5
ENABLE
1.0
5V
0V
0
–50
–60
–70
–80
–100
–110
0V
0
TIME (125ns/DIV)
–40
–90
5V
0.5
0.5
8192 POINT FFT
fIN = 10MHz, –1dBFS
FILTERED OUTPUTS
–10
3.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.0
0
RLOAD = 1009
PER OUTPUT
4.0
AMPLITUDE (dBFS)
4.0
10MHz 8192 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
–120
0
TIME (250ns/DIV)
64022 G27
5
10
64022 G28
15 20 25 30
FREQUENCY (MHz)
35
40
64022 G29
20MHz 8192 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
0
25MHz 8192 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
0
8192 POINT FFT
–10 fIN = 25MHz, –1dBFS
–20 FILTERED OUTPUTS
8192 POINT FFT
fIN = 20MHz, –1dBFS
FILTERED OUTPUTS
–10
–20
–40
–50
–60
–70
–80
–40
–50
–60
–70
–80
–90
–90
–100
–100
–110
–110
–120
0
5
10
15 20 25 30
FREQUENCY (MHz)
AMPLITUDE (dBFS)
–30
AMPLITUDE (dBFS)
–30
AMPLITUDE (dBFS)
20MHz 2-Tone 32768 Point FFT,
LT6402-20 Driving
LTC2249 14-Bit ADC
–120
35
40
64022 G30
0
5
10
15 20 25 30
FREQUENCY (MHz)
35
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
–130
–140
32768 POINT FFT
TONE 1 AT 19.5MHz, –7dBFS
TONE 2 AT 20.5MHz, –7dBFS
FILTERED OUTPUTS
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5
FREQUENCY (MHz)
64022 G31
64022 G32
640220fa
8
LT6402-20
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VOCM (Pin 2): This pin sets the output common mode
voltage. Without additional biasing, both inputs bias to
this voltage as well. This input is high impedance.
+OUTFILTERED, –OUTFILTERED (Pins 6, 7): Filtered
Outputs. These pins add a series 50Ω resistor from the
unfiltered outputs and three 14pF capacitors. Each output
has 14pF to VEE, plus an additional 14pF between each pin
(See the Block Diagram). This filter has a –3dB bandwidth
of 75MHz.
VCCA, VCCB, VCCC (Pins 3, 10, 1): Positive Power Supply
(Normally Tied to 5V). All three pins must be tied to the
same voltage. Bypass each pin with 1000pF and 0.1µF
capacitors as close to the package as possible. Split
supplies are possible as long as the voltage between VCC
and VEE is 5V.
E⎯ ⎯N⎯A⎯B⎯L⎯E (Pin 11): This pin is a TTL logic input referenced
to the VEEC pin. If low, the LT6402 is enabled and draws
typically 30mA of supply current. If high, the LT6402 is
disabled and draws typically 250µA.
VEEA, VEEB, VEEC (Pins 4, 9, 12): Negative Power Supply
(Normally Tied to Ground). All three pins must be tied to
the same voltage. Split supplies are possible as long as
the voltage between VCC and VEE is 5V. If these pins are
not tied to ground, bypass each pin with 1000pF and 0.1µF
capacitors as close to the package as possible.
+INA, +INB (Pins 15, 16): Positive Inputs. These pins are
normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the VOCM pin.
–INA, –INB (Pins 14, 13): Negative Inputs. These pins are
normally tied together. These inputs may be DC- or ACcoupled. If the inputs are AC-coupled, they will self-bias
to the voltage applied to the VOCM pin.
+OUT, –OUT (Pins 5, 8): Outputs (Unfiltered). These
pins are high bandwidth, low-impedance outputs. The DC
output voltage at these pins is set to the voltage applied
at VOCM.
Exposed Pad (Pin 17): Tie the pad to VEEC (Pin 12). If split
supplies are used, DO NOT tie the pad to ground.
W
BLOCK DIAGRA
500Ω
–INA
100Ω
14pF
–
14
–INB
VEEA
VCCA
+OUT
5
A
100Ω
+OUTFILTERED
+
13
6
50Ω
VEEA
VCCC
500Ω
VOCM
+
2
C
14pF
–
VEEC
500Ω
50Ω
+INA
7
+
16
+INB
–OUTFILTERED
VCCB
100Ω
–OUT
8
B
100Ω
–
15
14pF
VEEB
VEEB
500Ω
BIAS
3
10
VCCA
1
VCCB
11
VCCC
4
ENABLE
9
VEEA
6402 BD
12
VEEB
VEEC
640220fa
9
LT6402-20
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APPLICATIO S I FOR ATIO
Circuit Description
The LT6402-20 is a low noise, low distortion differential
amplifier/ADC driver with:
• –3dB bandwidth
DC to 300MHz
• Fixed gain independent of RLOAD
10V/V (20dB)
• Differential input impedance
100Ω
• Low output impedance
• Built-in, user adjustable output filtering
• Requires minimal support circuitry
Referring to the block diagram, the LT6402-20 uses a
closed-loop topology which incorporates 3 internal amplifiers. Two of the amplifiers (A and B) are identical and
drive the differential outputs. The third amplifier is used
to set the output common mode voltage. Gain and input
impedance are set by the 500Ω and 100Ω resistors in
the internal feedback network. Output impedance is low,
determined by the inherent output impedance of amplifiers
A and B, and further reduced by internal feedback.
The LT6402-20 also includes built-in single-pole output
filtering. The user has the choice of using the unfiltered
outputs, the filtered outputs (75MHz –3dB lowpass), or
modifying the filtered outputs to alter frequency response
by adding additional components. Many lowpass and
bandpass filters are easily implemented with just one or
two additional components.
The LT6402-20 has been designed to minimize the need
for external support components such as transformers or
AC-coupling capacitors. As an ADC driver, the LT6402-20
requires no external components except for power-supply
bypass capacitors. This allows DC-coupled operation for
applications that have frequency ranges including DC. At
the outputs, the common mode voltage is set via the VOCM
pin, allowing the LT6402-20 to drive ADCs directly. No
output AC-coupling capacitors or transformers are needed.
At the inputs, signals can be differential or single-ended
with virtually no difference in performance. Furthermore,
DC levels at the inputs can be set independently of the
output common mode voltage. These input characteristics
often eliminate the need for an input transformer and/or
AC-coupling capacitors.
Input Impedance and Matching Networks
Calculation of the input impedance of the LT6402-20 is
not straightforward from examination of the block diagram
because of the internal feedback network. In addition, the
input impedance when driven differentially is different than
when driven single-ended.
LT6402-20
Differential
Single-Ended
100Ω
85.9Ω
For single-ended 50Ω applications, a 121Ω shunt matching
resistor to ground will result in the proper input termination (Figure 1). For differential inputs there are several
termination options. If the input source is 50Ω differential,
then the input matching can be accomplished by either
a 100Ω shunt resistor across the inputs (Figure 3), or
equivalent 49.9Ω shunt resistors on each of the inputs
to ground (Figure 2). If additional AC gain is desired, an
impedance ratio transformer can also be used to better
match impedances.
13
14
–INB
–INA
–OUT
8
0.1µF
LT6402-20
15
IF IN
16
121Ω
ZIN = 50Ω
SINGLE-ENDED
+INB
+INA
+OUT
5
6402 F01
Figure 1. Input Termination for Single-Ended 50Ω
Input Impedance
640220fa
10
LT6402-20
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APPLICATIO S I FOR ATIO
Single-Ended to Differential Operation
The LT6402-20’s performance with single-ended inputs
is comparable to its performance with differential inputs.
This excellent single-ended performance is largely due
to the internal topology of the LT6402-20. Referring to
the block diagram, if the +INA and +INB pins are driven
with a single-ended signal (while –INA and –INB are tied
to AC ground), then the +OUT and –OUT pins are driven
differentially without any voltage swing needed from
amplifier C. Single-ended to differential conversion using
more conventional topologies suffers from performance
limitations due to the common mode amplifier.
Driving ADCs
The LT6402-20 has been specifically designed to interface
directly with high speed Analog to Digital Converters
(ADCs). In general, these ADCs have differential inputs, with
an input impedance of 1kΩ or higher. In addition, there is
generally some form of lowpass or bandpass filtering just
prior to the ADC to limit input noise at the ADC, thereby
improving system signal to noise ratio. Both the unfiltered
13
IF IN–
14
and filtered outputs of the LT6402-20 can easily drive the
high impedance inputs of these differential ADCs. If the
filtered outputs are used, then cutoff frequency and the
type of filter can be tailored for the specific application if
needed.
Wideband Applications
(Using the +OUT and –OUT Pins)
In applications where the full bandwidth of the LT6402-20
is desired, the unfiltered output pins (+OUT and –OUT)
should be used. They have a low output impedance;
therefore, gain is unaffected by output load. Capacitance
in excess of 5pF placed directly on the unfiltered outputs
results in additional peaking and reduced performance.
When driving an ADC directly, a small series resistance
is recommended between the LT6402-20’s outputs and
the ADC inputs (Figure 4). This resistance helps eliminate
any resonances associated with bond wire inductances of
either the ADC inputs or the LT6402-20’s outputs. A value
between 10Ω and 25Ω gives excellent results.
–INB
–INA
49.9Ω
ZIN = 50Ω
DIFFERENTIAL
8
LT6402-20
15
IF IN+
–OUT
16
+INB
+INA
+OUT
5
49.9Ω
6402 F02
Figure 2. Input Termination for Differential 50Ω Input Impedance
13
IF IN–
ZIN = 50Ω
DIFFERENTIAL
14
–INA
100Ω
–OUT
8
–OUT
16
8
10Ω TO 25Ω
LT6402-20
LT6402-20
15
IF IN+
–INB
ADC
10Ω TO 25Ω
+INB
+INA
+OUT
+OUT
5
6402 F03
Figure 3. Alternate Input Termination for Differential 50Ω
Input Impedance
5
6402 F04
Figure 4. Adding Small Series R at LT6402 Output
640220fa
11
LT6402-20
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Filtered Applications
(Using the +OUTFILTERED and –OUTFILTERED Pins)
Filtering at the output of the LT6402-20 is often desired
to provide either anti-aliasing or improved signal to noise
ratio. To simplify this filtering, the LT6402-20 includes an
additional pair of differential outputs (+OUTFILTERED and
–OUTFILTERED) which incorporate an internal lowpass
filter network with a –3dB bandwidth of 75MHz (Figure 5).
These pins each have an output impedance of 50Ω. Internal capacitances are 14pF to VEE on each filtered output,
plus an additional 14pF capacitor connected differentially
between the two filtered outputs. This resistor/capacitor combination creates filtered outputs that look like a
series 50Ω resistor with a 42pF capacitor shunting each
filtered output to AC ground, giving a –3dB bandwidth of
75MHz.
The filter cutoff frequency is easily modified with just a
few external components. To increase the cutoff frequency,
simply add 2 equal value resistors, one between +OUT and
+OUTFILTERED and the other between –OUT and –OUTFIL-
TERED (Figure 6). These resistors are in parallel with the
internal 50Ω resistor, lowering the overall resistance and
increasing filter bandwidth. To double the filter bandwidth,
for example, add two external 50Ω resistors to lower the
series resistance to 25Ω. The 42pF of capacitance remains
unchanged, so filter bandwidth doubles.
To decrease filter bandwidth, add two external capacitors,
one from +OUTFILTERED to ground, and the other from
–OUTFILTERED to ground. A single differential capacitor
connected between +OUTFILTERED and –OUTFILTERED
can also be used, but since it is being driven differentially
it will appear at each filtered output as a single-ended
capacitance of twice the value. To halve the filter bandwidth, for example, two 42pF capacitors could be added
(one from each filtered output to ground). Alternatively
one 21pF capacitor could be added between the filtered
outputs, again halving the filter bandwidth. Combinations
of capacitors could be used as well; a three capacitor
LT6402-20
VEE
50Ω
LT6402-20
VEE
50Ω
8 –OUT
14pF
7 –OUTFILTERED
8 –OUT
14pF
14pF
7 –OUTFILTERED
50Ω
14pF
FILTERED OUTPUT
(37.5MHz)
50Ω
6 +OUTFILTERED
FILTERED OUTPUT
(75MHz)
14pF
14pF
14pF
14pF
6 +OUTFILTERED
VEE
14pF
5 +OUT
6402 F07
VEE
5 +OUT
Figure 7. LT6402-20 Internal Filter Topology Modified
for 1/2x Filter Bandwidth (3 External Capacitors)
6402 F05
Figure 5. LT6402-20 Internal Filter Topology –3dB BW ≈75MHz
LT6402-20
VEE
LT6402-20
8 –OUT
VEE
50Ω
50Ω
14pF
50Ω
14pF
8 –OUT
7 –OUTFILTERED
7 –OUTFILTERED
50Ω
6 +OUTFILTERED
14pF
14pF
FILTERED OUTPUT
(150MHz)
14pF
FILTERED OUTPUT
50Ω
6 +OUTFILTERED
14pF
50Ω
VEE
VEE
5 +OUT
6402 F06
Figure 6. LT6402-20 Internal Filter Topology Modified
for 2x Filter Bandwidth (2 External Resistors)
5 +OUT
6402 F08
Figure 8. LT6402-20 Output Filter Modified for Bandpass
Filtering (1 External Inductor, 1 External Capacitor)
640220fa
12
LT6402-20
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APPLICATIO S I FOR ATIO
solution of 14pF from each filtered output to ground plus
a 14pF capacitor between the filtered outputs would also
halve the filter bandwidth (Figure 7).
Bandpass filtering is also easily implemented with just a
few external components. An additional 560pF and 62nH,
each added differentially between +OUTFILTERED and
–OUTFILTERED creates a bandpass filter with a 26MHz
center frequency, –3dB points of 23MHz and 30MHz, and
1.6dB of insertion loss (Figure 8).
Output Common Mode Adjustment
The LT6402-20’s output common mode voltage is set by
the VOCM pin. It is a high-impedance input, capable of
setting the output common mode voltage anywhere in
a range from 1.1V to 3.6V. Bandwidth of the VOCM pin is
typically 200MHz, so for applications where the VOCM pin
is tied to a DC bias voltage, a 0.1µF capacitor at this pin is
recommended. For best distortion performance, the voltage
at the VOCM pin should be between 1.8V and 2.6V.
When interfacing with most ADCs, there is generally a
VOCM output pin that is at about half of the supply voltage
of the ADC. For 5V ADCs such as the LTC17XX family, this
VOCM output pin should be connected directly (with the
addition of a 0.1µF capacitor) to the input VOCM pin of the
LT6402-20. For 3V ADCs such as the LTC22XX families,
the LT6402-20 will function properly using the 1.65V from
the ADC’s VCM reference pin, but improved Spurious Free
Dynamic Range (SFDR) and distortion performance can
be achieved by level-shifting the LTC22XX’s VCM reference
voltage up to at least 1.8V. This can be accomplished as
shown in Figure 9 by using a resistor divider between the
LTC22XX’s VCM output pin and VCC and then bypassing
the LT6402-20’s VOCM pin with a 0.1µF capacitor. For a
common mode voltage above 1.9V, AC coupling capacitors
are recommended between the LT6402-20 and LTC22XX
ADCs because of the input voltage range constraints of
the ADC.
Large Output Voltage Swings
The LT6402-20 has been designed to provide the
3.2VP-P output swing needed by the LTC1748 family
of 14-bit low-noise ADCs. This additional output swing
improves system SNR by up to 4dB.
Input Bias Voltage and Bias Current
The input pins of the LT6402-20 are internally biased to
the voltage applied to the VOCM pin. No external biasing
resistors are needed, even for AC-coupled operation. The
input bias current is determined by the voltage difference
between the input common mode voltage and the VOCM
pin (which sets the output common mode voltage). For
example, if the inputs are tied to 2.5V with the VOCM pin
at 2.2V, then a total input bias current of 1mA will flow
into the LT6402-20’s +INA and +INB pins. Furthermore,
an additional input bias current totaling 1mA will flow into
the –INA and –INB inputs.
Application (Demo) Boards
The DC954A Demo Board has been created for stand-alone
evaluation of the LT6402-20 with either single-ended or
differential input and output signals. As shown, it accepts
a single-ended input and produces a single-ended output
so that the LT6402-20 can be evaluated using standard
laboratory test equipment. For more information on this
Demo Board, please refer to the layout and schematic
diagrams found later in this data sheet.
There are also additional demo boards available that
combine the LT6402-20 with a variety of different Linear
Technology ADCs. Please contact the factory for more
information on these demo boards.
3V
11k
1.9V
0.1µF
13
14
–INB
–INA
VOCM
+OUTFILTERED
0.1µF
31 1.5V
6
LT6402-20
15
IF IN
16
–OUTFILTERED
+INB
4.02k
2
10Ω
1
LTC22xx
10Ω
7
VCM
AIN+
2
AIN–
+INA
121Ω
6402 F9
Figure 9. Level Shifting 3V ADC VCM Voltage for
Improved SFDR
640220fa
13
LT6402-20
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TYPICAL APPLICATIO
Top Silkscreen
640220fa
14
LT6402-20
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PACKAGE DESCRIPTIO
UD Package
16-Lead Plastic QFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1691)
0.70 ±0.05
3.50 ± 0.05
1.45 ± 0.05
2.10 ± 0.05 (4 SIDES)
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
3.00 ± 0.10
(4 SIDES)
BOTTOM VIEW—EXPOSED PAD
PIN 1 NOTCH R = 0.20 TYP
OR 0.25 × 45° CHAMFER
R = 0.115
TYP
0.75 ± 0.05
15
16
PIN 1
TOP MARK
(NOTE 6)
0.40 ± 0.10
1
1.45 ± 0.10
(4-SIDES)
2
(UD16) QFN 0904
0.200 REF
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WEED-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
0.25 ± 0.05
0.50 BSC
640220fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
15
LT6402-20
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TYPICAL APPLICATIO
Demo Circuit DC954A Schematic (AC Test Circuit)
R18
0Ω
R17
0Ω
VCC
VCC
GND
VCC
1
SW1
TP1
ENABLE
2
3
R16
0Ω
2
2
C17
1000pF
1
1
C18
0.01µF
1
1
J1
–IN
T1
5 1:1 Z-RATIO
14
2
C1
0.1µF
R5
0Ω
16
2
R3
49.9Ω
9
VCCB VEEB
–INB
–OUT
–INA
–OUTFILTERED
+INB
+OUTFILTERED
+INA
VCCC
1
VCC
C10 2
0.01µF
1
10
ENABLE
VOCM
VCCA
+OUT
VEEA
2
3
4
2
C12
1000pF
C9 2
1000pF
1
1
C4
0.1µF
R10
8 24.9Ω
1
R8
[1]
7
R7
[1]
LT6402-20
15
3
VCC
11
VEEC
0dB
2
1
R1
[1]
13
C21
0.1µF
1
•
•
0dB
J2
+IN
R6
0Ω
2
1
4 M/A-COM
ETC1-1T
12
C2
0.1µF
6
R9
24.9Ω
5
L1
[1]
1
C11
[1]
2
R14
0Ω
R12
75Ω
2
J4
–OUT
T2
3 4:1 Z-RATIO 4
2
C8
[1]
1
R15
[1]
+18.8dB
+14dB
2
1
C3
0.1µF
1
R11
75Ω
MINI5
+8dB
CIRCUITS
TCM 4-19
J5
+OUT
2
1
VCC
2
1
•
R4
49.9Ω
•
R2
0Ω
2
C16
[1]
2
1
C22
0.1µF
R13
[1]
C13
0.01µF
R19
14k
J3
2
J6
TEST IN
T3
1:4
5
1
•
•
MINICIRCUITS
TCM 4-19
TP2
VCC
C5
0.1µF
1
C19, 0.1µF
2
1
4
C7
0.01µF
1
R21
[1]
2
C6
0.1µF
2
R22
[1]
4
J7
TEST OUT
2
1
2
1
3
1
T4
4:1
3
C20, 0.1µF
2
•
R20
11k
•
VOCM
MINI5
CIRCUITS
TCM 4-19
VCC
1
2
1
TP3
GND
C14
4.7µF
2
1
C15
1µF
NOTES: UNLESS OTHERWISE SPECIFIED,
[1] DO NOT STUFF.
1
6402 TA02
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1993-2
800MHz Differential Amplifier/ADC Driver
AV = 2V/V, NF = 12.3dB, OIP3 = 38dBm at 70MHz
LT1993-4
900MHz Differential Amplifier/ADC Driver
AV = 4V/V, NF = 14.5dB, OIP3 = 40dBm at 70MHz
LT1993-10
700MHz Differential Amplifier/ADC Driver
AV = 10V/V, NF = 12.7dB, OIP3 = 40dBm at 70MHz
LT5514
Ultralow Distortion IF Amplifier/ADC Driver
Digitally Controlled Gain Output IP3 47dBm at 100MHz
LT6600-5
Very Low Noise Differential Amplifier and 5MHz Lowpass Filter 82dB S/N with 3V Supply, SO-8 Package
LT6600-10
Very Low Noise Differential Amplifier and 10MHz Lowpass
Filter
82dB S/N with 3V Supply, SO-8 Package
LT6600-20
Very Low Noise Differential Amplifier and 20MHz Lowpass
Filter
76dB S/N with 3V Supply, SO-8 Package
LT6402-6
300MHz Differential Amplifier/ADC Driver
AV = 6dB, en = 3.8nV/√Hz at 20MHz, 150mV
LT6402-12
300MHz Differential Amplifier/ADC Driver
AV = 12dB, en = 2.6nV/√Hz at 20MHz, 150mV
LT6411
650MHz Differential ADC Driver/Dual Selectable Gain Amplifier 3300V/µs Slew Rate, 16mA Current Consumption, Selectable Gain:
AV = –1, +1, +2
640220fa
16 Linear Technology Corporation
LT 0706 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2005