Proceedings of the 14th International Middle East Power Systems Conference (MEPCON’10), Cairo University, Egypt, December 19-21, 2010, Paper ID 269.
Design of Integrated High Efficiency Two-Stage Point of
Load DC-DC Converter
Mohamed Saad1, IEEE Student Member, Mohamed Orabi1, IEEE Senior Member,
El-Sayed Hasaneen2, Ashraf Lotfi3, IEEE Senior Member
1
APEARC, South Valley University, Aswan 81542, Egypt
2
El-Minia University, El-Minia, Egypt
3
Enpirion Inc. New Jersey 08827, USA
orabi@ieee.org
ƒ
ƒ
Abstract - Recently, most of researches are directed toward
the design of small size and high efficiency power management
integrated circuits (PMICs). The advantage of small sizes
supports minimizing the PCB area. The high efficiency
advantage supports the increase of battery life and energy saving.
This paper presents a high efficiency two-stage voltage regulator
for the point-of-load (POL) applications. A 6V-to-1V converter is
divided into two conversion stages. The first stage is a high
efficiency switched capacitor converter to obtain 3V from the 6V
input. This low output voltage (3V) gives the chance to design
second stage buck converter with a very high efficiency and a
small footprint with 3-1V conversion. A detailed design of the
fully integrated two-stage converter is provided using H-Spice.
The results show a better performance for this combination than
using the regular design of one stage 6-1 buck converter. The
combined system achieves 93.6% peak efficiency and an average
efficiency of 91% over an output current range from 1A to 6A.
Reduced converter size & improved converter
Efficiency
Synchronous buck converter is the most common
topology used for step down voltage regulators for these
applications (POL) types. But as the available input voltage
increases in one direction and the output voltages decreases in
the other direction, the buck converter may fail to meet the
target of high efficiency as the operating duty cycle becomes
more and more small. A roughly speaking, 10% efficiency
difference can be achieved if the input voltage is half its value
(double the duty cycle). Therefore, using a converter with
voltage gain of 0.5 and efficiency over 90% can easy result in
better system efficiency.
Also, by simply decreasing the input voltage and using
low-voltage-rating devices, the synchronous buck elements
can be small in footprint. Therefore, in this paper, this idea has
been tested and applied. A simple and highly efficient stepdown converter is used as the first stage [2]. Referring to [3]
the first stage is best chosen as switched capacitor converter.
Switched capacitor converter has the following advantages:
ƒ High power density.
ƒ It can be optimized for high efficiency.
ƒ It is inductor-less which reduces the problem of
radiated EMI.
Index Terms – Dc-Dc converters; Buck converter; two-stage;
switched capacitor converter; POL, high efficiency.
I. INTRODUCTION
Many of researchers now pay more efforts in order to
design very thin and very efficient PMICs. Most of the
challenges facing the researchers are combining between the
small size and the high efficiency advantages. The small size
is reached by fully integration of most of the component used
in the Point Of Load (POL) converter. Adding multiple offchip components is not only difficult due to parasitic concerns,
but also adds cost to the platform by increasing PCB area and
package complexity. Increasing the efficiency can be a result
for minimizing the losses by optimizing the different
parameters of the POL converter designed.
Most of current industrial applications such as DSPs and
microprocessors have been improved from clock frequency
and capabilities point of view. However to get theses
improvement, the operation voltage is required to be reduced
without reducing the power consumption. In general, the main
requirements for any voltage regulator to feed the last
generation microprocessors and DSPs are [1]:
ƒ Low output voltage: 1 to 3.3 V.
ƒ Low Output voltage ripples, less than 5% or less.
ƒ High load current: 1 to 50 A.
ƒ High current slew rate: up to 5A/ns.
The output voltage of the switched capacitor is half of the
input voltage. As regulation task will be the responsibility of
the second stage, then first stage is kept unregulated for
simplicity and cost reduction. The first stage (switched
capacitor) is followed by a regulation stage which is buck
converter. The second stage is designed to have high
efficiency, tight regulation, fast response and low-voltage
devices operating at a high switching frequency to provide
high-bandwidth regulation and a small additional voltage stepdown. Since the regulation stage operates at a high frequency,
the size of its passive components can be made small [4].
In this paper, the design of two stage DC-DC converter is
discussed. First, the design and simulation of the first stage
buck converter are provided. Then, the design and simulation
of the second stage buck converter is described in section III.
In section IV, the total system connection and simulation
708
In the low-frequency limit, the output resistance is inversely
proportional to the energy-transfer capacitance values, and the
clock frequency [6],
results are shown. In section V, a comparison between the two
system approach and one stage synchronous buck converter is
provided from the efficiency point of view to prove the idea.
Finally, conclusion is given.
At high switching frequencies, the output resistance reaches a
minimum value Romin, which depends on the switch on
resistances, and which can be found using state-space
averaging. An analytical approximation for Ro(f) over wide
range of frequencies was proposed in [7]:
where the “corner” frequency fc is the corner frequency where
the low-frequency asymptote and the high frequency
asymptote have the same value [7]. From (2), it is clear that as
the switching frequency increases, the output impedance of the
SC converter decreases. For a given load Io, the conduction
loss Pc can be found as
Fig.1 Schematic diagram of the H-bridge switched capacitor converter.
II. DESIGN OF THE FIRST STAGE SWITCHED CAPACITOR
CONVERTER
Figure 1 shows the Switched Capacitor (SC) DC-DC step
down converter topology used in the design of the first stage.
This topology is called H-bridge topology [5]. In this topology
we have two capacitors CF1 and CF2. The switching network
enables series or parallel arrangement of the two capacitors to
obtain the required conversion ratio. The operation of the
circuit can be divided into phases. During the first phase, the
two flying capacitors are connected in series with the input
voltages. This phase is called the charging phase and during
this phase the each of the flying capacitors charges to a
voltage equals half of the input voltage. At the second phase,
the two flying capacitors are connected in parallel. This phase
is called the discharging phase and the load is supplied by the
required current through this phase. During charge phase,
series connection of the flying capacitors is reached by closing
the switches S1, S2 and opening switches S3, S4. During
discharge phase, parallel connection is reached by closing
switches S3, S4 and opening switches S1, S2.
The switches S1, S2, S3, and S4 are implemented using
standard CMOS technology MOSFETs for the purpose of
integration. As S1, S2 are turned on and off at the same time,
their gates are tied together and derived using the same gate
drive output. The same is true for switches S3, S4 which are
derived from another gate drive output.
It is required for the SC converter to convert from 6V-to3V and the second stage buck converter will fed from the SC
converter output and converts from 3V-to-1V with an
operation optimized at output current 6A. So for the buck
converter to give an output power of 6W with 3V input
voltage, it will sink an input current equals or greater than 2A.
Thus the design of the SC converter has been done under the
condition of output current 2A.
As stated in (3), the conduction loss is strongly depending on
the output impedance, so increasing the switching frequency
will give a significant rise in the efficiency values rather than
decreasing the total system solution.
Another type of losses that will affect the converter efficiency
is the switching losses. The switching losses are a natural
result of charging the parasitic capacitances present at each
node in the circuit with a continuous toggling voltage. The
toggling rate of this voltage is the clock frequency or
switching frequency of the converter.
Mainly, the switching losses can be given as the summation of
all parasitic capacitances losses like this:
Where Ci is the parasitic capacitance at the ith node in the
converter circuit, V is the voltage across this capacitance, and f
is the converter switching frequency. From (4), it is clear that
the effect of switching frequency on the switching losses will
be the opposite of its effect on the conduction losses. It is
complicated to trying to calculate the optimum frequency at
which the conduction and switching losses are equal. A scan
for resulted efficiency is applied for the range of 100-500 kHz
to choose the optimum switching frequency. The plot of
efficiency as a function of the output current at three different
switching frequencies is shown in Fig.2 for VIN=6V and
VOUT=3V.
709
(a) The output voltage average value
Fig.2 Efficiency as a function of output current for a three different switching
frequency values.
The efficiency plot shows that the best switching
frequency is 200 kHz. At this frequency, a peak efficiency of
97% can be reached at output current 2A. It is worth here to
recall what we have mentioned in the introduction section, that
we are in need for first stage with efficiency higher than 90%
to recover for single stage. Here, it is clear the advantage of
having 97%.
(b) The peak-to-peak output ripple
Both of the switching frequency and the value of flying
capacitors are affecting the value and ripple of output voltage.
For a suitable output ripple a capacitor has been chosen to be
47uF. This selected capacitors values give output voltage
ripple of 24mV. Of course this output ripple is very small and
this give the advantage of using a smaller capacitor, but the
output voltage is not regulated and minimizing the flying
capacitors values result in an increase in the output impedance
and hence a decrease in the output voltage value at the
optimum output current 2A. Using the chosen flying
capacitors value which is 47µF, the output voltage average
value is 2.98V with a ripple 24mV. Figure 3 (a) shows the Hspice based simulation results for the SC converter output
where (b) shows the peak-to-peak ripple.
Fig.3 the output voltage and peak-to-peak ripple.
The high frequency operation of the buck converter enables
the minimization of output LC filter; inductance and
capacitance values. The buck converter is design to work in
the continuous conduction mode (CCM). The minimum
inductance value is designed based on the (5), which
determines the critical inductance value to work in CCM [8]:
Where:
LMIN : is the minimum output inductance value.
D: is the duty cycle (1V/3V).
FSW : is the switching frequency (1MHz).
VO : is the required output voltage (1V).
ILoad : is the required output current (6A).
II. DESIGN OF THE SECOND REGULATION STAGE (BUCK
CONVERTER)
The output of the SC converter which is the first stage
will be approximately 3V. The synchronous buck converter is
used here to achieve the targets of regulation and adding extra
step down conversion. The buck converter receives the
unregulated 3V from the output of SC converter and produces
a regulated output voltage of 1V. The design of the buck
converter is optimized at 3V input voltage, 1V output voltage,
6A output current, and 1MHz switching frequency.
As a result, the minimum inductor that can be used is 56nH.
Indeed choosing higher values of inductance has a good effect
on reducing the inductor current ripple and to reduce the AC
conduction losses of the inductor [9]. In addition, the inductor
current ripple has the greatest effect on output voltage ripple.
The inductor current has two components, DC component and
AC component. The AC current which passes through the
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capacitor makes three voltage drops on the output capacitance
(CO), the equivalent series inductance (ESLO) and the
equivalent series resistance (ESRO). The total output ripple is
the summation of the three voltage drops. This is shown in
Fig. 4. In order to reduce the inductor current ripple as
possible, the inductor value is chosen to be 150nH.
Fig.5 The buck output voltage and output ripple
The optimization and maximum efficiency at the desired
output current 6A can be reached by taking care of both the
switching loss and conduction loss for the buck converter
PFET and NFET.
The switching loss has been reduced to almost small values by
well designing a good gate drive circuit. The conduction loss
which now is the significant loss in the buck circuit is
dependent mainly on the output current and the FETs onresistance.
The losses for the control FET is calculated as follows:
Fig.4 The inductor ripple effect on output voltage ripple
Also, the output capacitor can be determined from the
maximum output voltage ripple relation of ideal capacitor [9],
Where:
: is the maximum output voltage ripple.
Vo
: is the required output voltage (1V).
D: is the duty cycle (1V/3V).
Fsw : is the switching frequency (1MHz)
L
: is the output inductance value (150 nH).
C
: is the output capacitance.
where, Pon is the conduction loss, Psw is the total switching
loss, Qg is the total gate charge. The losses for synchronous
FET are calculated similarly.
The total loss first decrease with increasing die size, reach
a minimum point and then start increasing. For a smaller die,
the switching losses are small but the conduction losses are
very high. As the die size increases, the device on-resistance
reduces and gate capacitance goes up. This results in lower
conduction losses and higher switching losses [11].
From this equation, to obtain an output voltage ripple smaller
than 3%, the output capacitor must be larger than 19µF. Due
to the effect of capacitor's equivalent series inductance (ESL)
and equivalent series resistance (ESR) on output voltage
ripple, the capacitor has been chosen to be 47µF. The practical
datasheet values (ESL and ESR) of a commercial capacitor are
needed for simulation, so CM316X5R476M06A Murata
capacitor is chosen. The selected capacitor has the following
data [10]:
ƒ ESL = 0.4nH
ƒ ESR = 2.75mΩ
Actually, the die size is affected by the FETs. This means
that increasing the size of the FETs lowering the on-resistance
and decrease conduction loss. At the same time, increasing the
size of the FETs increases the gate capacitance value and
tends to increase the switching loss. At some point, the total
loss reaches a minimum beyond which the switching losses
become the dominant component. This point corresponds to
the optimum die and FETs size and varies from one
technology to another depending on the devices parameters
[11].
The output voltage of the buck converter is shown in Fig. 5.
The output ripple is also shown on the same figure.
At the standard CMOS technology, the optimum point is
reached and FETs size is optimized to get the minimum losses
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and the higher efficiency. The buck converter stage showed
efficiency 94.4% at the full output current 6A with an input
voltage 3V and output voltage 1V. Figure 6 shows a plot for
the buck converter efficiency vs. the output current. As clear
in the figure, the converter has peak efficiency 96% at output
current 3A. It is clear from Fig. 6 that these efficiency values will
give a significant rise in the total system (two-stage) efficiency,
especially at light load where the conventional one stage buck
converter system suffers from low efficiency.
Fig.7 Efficiency as a function of output current for the two-stage system.
Fig.6 Efficiency as a function of output current for the designed buck
converter.
III. TOTAL SYSTEM INTEGRATION AND TEST
After finishing the design of the first stage and second
stage individually with each stage optimized for output power
6W, the two stage connection and total system integration is
made.
The input voltage 6V of the total system is connected to the
SC converter input; the output of the SC converter is
connected to the input of the buck converter. A dynamic
current source of 6A representing the load is connected to the
output of the buck converter which is now the output of the
two-stage system.
Fig.8 Efficiency as a function of output current for a conventional buck
converter.
For comparison purpose, a one-stage buck converter has been
designed and simulated using an H-spice simulator. The buck
converter designed based on the following requirement:
• Input voltage 6V.
• Output voltage 1V.
• Full output current 6A.
• Very high frequency operation (1MHz).
The efficiency curve as a function of the output current for the
one-stage buck converter is plotted in Fig. 8. It is clear that
new system has better efficiency by at-least 5%.
Although the total efficiency of the system can be predicted by
multiplying the efficiency of the two stages for each output
current, an H-spice based simulation is made for the total
system to ensure its operation and performance. Fig. 7 shows
the efficiency of the total system as a function of the output
current ranging from 1A to 6A with a step current of 1A. It is
clear that the total system is very efficient. At full load, the
resulted efficiency is 91.31% which cannot be obtained using
conventional buck regulator. The peak efficiency of the twostage converter is 93.6% at output current 3A.
IV. CONCLUSION
The idea of two-stage high efficiency DC-DC converter is
investigated, and the design of each stage is explained
individually. The results of the new two-stage DC-DC
converter system give a significant rise in the efficiency at
both light-load and full-load. The proposed integrated system
is proved that it is a good replacement for the single buck
converter at higher step down conversion ratios.
These results prove that this two-stage system can be a good
replacement for the buck regulator if a large step down
conversion ratio is desired.
ILoad
1
2
3
4
5
6
Eff
90.12%
93.30%
93.60%
93.10%
92.29%
91.31%
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ACKNOWLEDGMENT
The authors would like to express their gratitude to
Enpirion Inc. for their support during this work based on its
collaboration project with APEARC.
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